Norsk Data ND-100 User manual

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0
Reference
Manual
ND-06.014.02
NORSK
DATA
A.S
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N D-100
Reference Manual
ND-06.014.02

'
"
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ND-100
Reference
Manual
ND-06.014.02
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iv
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Section:
1.1
1.2
1.2.1
1.2.2
1.2.2.1
1.2.3
1.2.3.1
1.2.3.2
1.2.3.3
1.2.3.4
1.3
1.4
1.5
1.5.1
1.5.2
1.5.3
1.6
1.6.1
1.6.2
1.7
1.8
1.8.1
1.8.2
1.8.3
2.1
TABLE OF CONTENTS
+ + +
Page:
INTRODUCTION TO ND-100 ................................................. 1—1
General Characteristics .................................................... 1—"1
I
ND-100 Functional Modules ............................................. 1L3
General ....................................................................... 1—3
ND-100
Central Processing Unit
(CPU)
Module ......... 1—5
CPU Characteristics .............................................. 1—6
ND-100 Architecture ................................................... 1 -—7
General ..................................................................
1—7
ND-100 Configuration Examples ........................... 1—8
Multiprocessor Systems ....................................... 1 —9
Remote
Operation ................................................. 1 —10
The Interrupt System ....................................................... 1 —11
The Memory Management
System ................................. 1—12
The Memory System ........................................................ 1 —-13
Main Memory
............................................................. 1—1’3
Cache Memory ........................................................... 1—13
Multiport Memory
....................................................... 1—13
The Input/Output System ................................................
1—14
Programmed Input/Output
—
PIO ............................. 1—14
Direct Memory Access
—
DMA ................................. 1—14
ND-100
Peripheral Equipment .........................................
1—15
ND-100 Software .............................................................. 1—16
The Operating System ................................................ 1—16
Supporting Software
.................................................. 1—17
Distributed Data Processing ....................................... 1—17
SYSTEM DESCRIPTION ........................................................ 2—1
Central Processor
.............................................................
2-1
ND-06.014.02

vi
Section: Page:
'
2.1.1
General ......................................................................
2—1
2.1.2
Internal Communication
............................................
2—3
2.1.3 The Address Arithmetic ..............................................
2—3
2.1.4 Instruction Fetch .......................................................
2—3
2.1.5
Prefetch ..................................................................... 2—3
2.1.6 Instruction Execution ................................................. 2—4
2.1.7 Main Arithmetic .......................................................... 2—4
2.1.8 The Register File .........................................................
2—6
2.1.9
Status Indicators ....................................................... 2—8
2.2
The Interrupt System ....................................................... 2—10
2.2.1
General ......................................................................
2—10
2.2.2 Functional Description ..............................................
2—12
2.2.3 The External Interrupt System ................................... 2—14
2.2.4 The Internal Interrupt System ....................................
2—16
2.2.4.1 The IIC and IIE Registers
.............................
'
........ 2—17
2.2.4.2
Internal Hardware Status Interrupts ....................
2—18
2.2.4.3 Reset of the IIC Register ..................................... 2—20
2.2.5 Programmming Control of the Interrupt
System ...... 2—21
2.2.5.1 Programmming the PID and PIE Registers .........
2—21
2.2.5.2 The WAIT, ION and IOF Instruction .....................
2—22
2.2.5.3 The Previous Level Register, PVL ........................
2—22
2.2.5.4 Vectored Interrupts and the IDENT Instructions
.2—23
—2.2.6 Initializing of the Interrupt System ...........................
2—24
2.3
The Memory Management System .................................
2—25
2.3.1 General ......................................................................
2—25
2.3.2 Memory Management Architecture
.......................... 2—26
2.3.3 The Paging System .....................................................
2—28
2.3.4 The Shadow Memory .................................................
2—30
2.3.5
The
Page Tables .. .......................................................
2—32
2.3.5.1 Page Used and Written in Page ..........................
2—34
2.3.5.2 Page
Table Selection ...........................................
2—34
2.3.6 Memory Protection
System ......................................
2—35
2.3.6.1 Page
Protection System .......................................
2—35
2.3.6.2
Ring Protection
System .......................................
2—37
2.3.7
Privileged Instructions ...............................................
2—39
2.3.8 Memory Management
Control and Status
............... 2—40
ND-06.014.02

Section:
2.3.8.1
2.3.8.2
2.3.8.3
2.3.9
2.4
2.4.1
2.4.2
2.4.2.1
2.4.2.2
2.4.2.3
2.4.2.4
2.4.3
2.4.4
2.4.4.1
2.4.4.2
2.4.5
2.4.5.1
2.21.5.2
2.4.6
2.4.6.1
2.4.6.2
2.4.6.3
2.4.6.3.1
2.4.6.3.2
2.5
2.5.1
2.5.2
2.5.3
2.5.4
2.5.5
2.5.6
2.5.6.1
2.5.6.2
2.5.6.3
2.5.7
vii
Page:
The PON and POF
Instructions ............................. 2—40
Paging
Control Registers ...................................... 2—41
Paging Status Register
.........................................
2—42
The SEX and REX
Instructions
................................... 2—43
ND-100 Memory
System ..................................................
2—44
General ......................................................................
2—44
ND-100 Memory
Architecture
.................................... 2—46
Local (Main)
Memory ............................................ 2—47
Memory
Module
Placement in Eurobus ............... 2—47
The Position Code
................................................. 2—47
The Thumbwheel Setting ...................................... 2—48
Memory
Error Correction ........................................... 2—50
Memory
Control and Status ....................................... 2—52
Error Correction Control Register (ECCR) ............
2—52
Memory Status Regsiters
(PEA and
PES) ............ 2—53
Multiport Memory
.......................................................
2—54
Big Multiport Memory
(BMPM) ............................ 2—54
Multiport Memory 4
(MPM4) ................................ 2—54
Cache Memory ...........................................................
2—55
Cache Memory
Architecture ................................. 2—55
Cache Memory
Organization ................................ 2—56
Cache Control and Status ......... -. ...........................
2—58
Cache Control ..................................................
2—58
Cache Status Register
.....................................
2—-59
ND-100
Input/Output
System
..........................................
2—60
General .......................................................................
2—60
ND-100
l/O Architecture ............................................. 2—61
ND‘100 Card Crate
—
Physical
Layout ......................
2—62
The ND-100
Bus ..........................................................
2—65
ND-1OO l/O System Function Description ..................
2—66
Programmed Input/Output
—
PIO .............................
2—67
The Input/Output
Instruction
—-
lOX ....................
2—67
Interface Channels and Registers ......................... 2—68
Control and Status Register .................................
2—7‘1
Direct
Memory
Access (DMA)
...................................
2—62
I
ND-06.014.02

Section:
2.5.7.1
2.5.7.2
2.5.7.2.1
2.5.7.2.2
2.5.7.2.3
2.5.7.2.4
2.5.8
2.5.8.1
2.5.8.2
2.5.8.3
2.5.9
2.5.9.1
2.5.9.2
2.6
2.6.1
2.6.2
3.1
3.1.1
3.1.1
3.1.2
3.1.2.1
3.1.2.2
3.1.2.3
3.1.2.4
3.1.2.5
3.1.2.6
3.2
3.2.1
3.2.1.1
3.2.1.2
3.2.1.3
viii
Page:
General ..................................................................
2—72
DMA Controller
Operation
....................................
2—72
Initialization
...........................................................
2—73
Transfer
.................................................................
2—73
Termination
and Status Check
.............................. 2—73
General
Considerations
.........................................
2—74
The I/O System
and the
Interrupt System ................ 2—75
General
..................................................................
2—75
Interrupt Level Usage
............................................ 2—75
Device
Interrupt Identification
.............................. 2—76
Programming
Specifications
for |/O
Device
on
the CPU Board
.......................................................
2—76
The Real-time Clock
..............................................
2-77
The Current Loop
Interface ...................................
2—77
ND-IOO
Bus Extender
(BEX)
............................................ 2—79
General
......................................................................
2—79
Bus Extender
Architecture
.........................................
2—79
ND-IOO INSTRUCTIONS
.......................................................
3—1
Introduction
to the Instruction
Repertoire ......................
3—1
General
.......................................................................
3—1
General
.......................................................................
3—1
Instruction and Data
Formats ....................................
3—3
Single Bit ...............................................................
3—3
8 Bit Byte
...............................................................
3—4
16 Bit Word ...........................................................
3—4
32 Bit
Double Word
............................................... 3—5
48
Bit Floating
Point Word .................................... 3—6
32
Bit Floating
Point Word ....................................
3—7
The Instruction Repertoire
...............................................
3—9
Memory Reference
Instructions
................................. 3—9
Addressing Structure
............................................ 3—9
Store Instructions ..................................................
3—18
Load Instructions ...................................................
3—20
ND-06.014.02

Section:
3.2.1.4
3.2.1.5
3.2.1.6
3.2.1.7
3.2.2
3.2.2.1
3.2.2.1
. 1
3.2.2.1.2
3.2.2.2
3.2.2.3
3.2.2.3.1
3.2.2.3.2
3.2.2.4
3.2.2.5
3.2.2.6
3.2.2.6.1
3.2.2.6.2
3.2.2.6.3
3.2.3
3.2.3.1
3.3
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.3.5.1
3.3.6
3.3.6.1
3.3.6.2
3.3.6.3
3.3.7
3.3.8
3.3.9
3.3.10
Page:
Arithmetical
and
Logical
Instructions
................... 3—21
Sequencing
Instructions
.......................................
3—24
Byte
Instructions
...................................................
3—26
Extended
BYTE-instructions
..................................
3—27
Register
Instructions
..................................................
3—30
Floating
Point
Conversion
Instructions
.........
-. ....... 3—30
Standard
48 Bit
Floating Point
Conversion
..... 3—30
Optional
32 Bit
Floating
Point Conversion
....... 3—32
Shift
Instructions
...................................................
3—33
Register
Operations
..............................................
3—36
ROP
—
Register
Operation
Instructions
.........
3—38
Extended
Register
Operation
Instructions
...... 3—45
Skip
Instructions
...................................................
3—47
Argument
Instructions
..........................................
3—50
Bit Operation
Instructions
.....................................
3—53
Bit
Skip Instructions
........................................
3—54
Bit Set
Instructions
..........................................
3—54
One Bit
Accumulator
Instructions
...................
3—55
System
Control
Instructions
.......................................
3-56
Monitor
Call
Instruction
...........................
3—56
Privileged
Instructions
....................................................
3—57
General
......................................................................
3—57
Register
Block
Instructions
........................................
3—57
Inter-level
Register
Instructions
.................................
3—59
Accumulator
Transfer
Instructions .............................
3-60
Input/Output
Control
Instructions
..............................
3—63
Extension
of the Device
Register Address
........... 3—64
System
Control
Instructions
.......................................
34-64
Interrupt
Control
Instructions
...............................
3—65
Memory
Managementlflontrol
Instructions
.......... 3—68
Wait
or Give
Up Priority
........................................
3—70
Examine
and
Deposit
..................................................
3—71
Load Writeable
Control Store
....................................
3—72
Customer
Specified
Instructions
................................
3—73
Physical
Memory
Read/Write
Instructions
................
3—74
ND-06.014.02

Section:
3.3.10.1
3.3.10.2
3.4
3.4.1
3.4.1.1
3.4.1.1.1
3.4.1.1.2
3.4.1.2
3.4.2
3.4.2.1
4.1
4.1.1
4.1.2
4.2
4.2.1
4.2.2
4.2.2.1
4.2.2.1.1
4.2.2.1.2
4.2.2.1.3
4.2.2.1.4
4.2.2.1.5
4.2.2.2
4.2.2.2.1
4.2.2.2.2
4.2.2.2.3
4.2.2.2.4
4.2.2.2.5
4.2.2.2.6
Page:
Format
of Instructions
...........................................
3—74
Addressing
............................................................
3—75
Instructions
in
the
«Commercial
Extended»
(CE)
Option
3—76
Decimal
Instructions
...................................................
3—76
Data
Formats
for
Decimal
Instructions
................
3—76
Packed
Decimal
Number
.................................
3—76
ASCII
Coded
Decimal
Number
........................
3—78
The
Decimal
Instructions
......................................
3—80
Stack
Handling
Instructions
.......................................
3—85
Data
Structure
Operated
upon
by
the
Instructions
..........................................................
3—85
OPERATOR'S
INTERACTION
................................................
4—1
Control
Panel
Push
Buttons
.............................................
4—1
The
Panel
Lock
Key
....................................................
4—3
Status
Indicators
........................................................
4—3
Microprogram
for
Operator’s
Communication
................
4—4
General
Considerations
..............................................
4—4
Control
Functions
.......................................................
4—6
System
Control
......................................................
4—6
Master
Clear
....................................................
4—6
Stop ..................................................................
4—6
ALD
Load
.........................................................
4—7
General
Load
....................................................
4—8
Leave
MOPC
...................................................
4—9
Program
Execution
...............................................
4—8
Start
Program
.................................................
4-8
Continue
Program
...........................................
4—8
Single
Instruction
...........................................
4—9
Instruction
Breakpoint
....................................
4—9
Manual
Instruction
..........................................
4—8
Single
I/O
Instruction
Function
......................
4—9
ND-06.014.02

Section:
4.2.2.3
4.2.2.3.1
4.2.2.3.2
4.2.2.3.3
4.2.3
4.2.3.1
4.2.3.1.1
4.2.3.1.2
4.2.3.1.3
4.2.3.1.4
4.2.3.1.5
4.2.3.1.6
4.2.3.2
4.2.3.2.1
4.2.3.2.2
4.2.3.2.3
42.3.24
42.3.25
4.2.3.3
4.2.3.3.1
4.2.3.3.2
4.2.3.3.3
4.2.3.3.4
4.2.4
4.2.4.1
4.2.4.2
4.2.4.3
4.2.5
4.2.5.1
4.2.5.2
4.2.5.3
4.3
4.3.1
4.3.2
xi
Page:
Miscellaneous
Functions
.......................................
4—10
Internal
Memory
Test
......................................
4—10
Delete
Entry
.....................................................
4—10
Current
Location
Counter
................................
4—10
Monitor
Functions
.......................................................
4—11
Memory
Functions
.................................................
4—11
Physical
Examine
Mode
...................................
4—11
Virtual
Examine
Mode
......................................
4—11
Memory
Examine
.............................................
4—12
Memory
Deposit
..............................................
4—12
Deposit
Rules
...................................................
4—13
Memory
Dump
.................................................
4—13
Register
Functions
................................................
4—14
Register
Examine
.............................................
4—14
Register
Deposit
..............................................
4—15
Register
Dump
-
RD
........................................
4—15
User
Register
-
U .............................................
4—15
Operator
Panel Switch
Register
-
OPR
........... 4—16
internal
Register
Functions
...................................
4—17
Internal
Register
Examine
................................
4—17
Internal
Register
Deposit
.................................
4—18
Internal
Register
Dump
-
IRD
..........................
4—19
A Scratch
Register
Dump
-
RDE .....................
4—19
Display
Functions
.......................................................
4—20
Displayed
Format ..................................................
4—20
Display
Memory
Bus .............................................
4—21
Display
Activity
......................................................
4—21
Bootstrap
Loaders
......................................................
4—22
Binary
Format
Load ...............................................
4—22
Mass
Storage
Load ..............................................
4—23
Automatic
Load
Descriptor
...................................
4—24
The
Display ......................................................................
4—25
General
.......................................................................
4—25
The
Different
Display
Functions
.................................
4—25
ND-06.014.02

Appendixes:
A.1
A.2
E.2
E.2.1
E.2.2
E.2.3
E.3
E.4
E.5
E.6
E.7
F.1
F.2
F.3
G.1
G.2
xii
Page:
ND-IOO INSTRUCTIONS .......................................................
A—I
ND-IOO Instruction Codes ................................................
A—1
ND-100 Instruction
Execution Times ...............................
A—12
MODEL 33 ASR/KSR
TELETYPE CODE (ASCII) IN
BINARY FORM ......................................................................
B—I
STANDDDDARD
ND-100 DEVICE REGISTER
ADDRESSES
ANDIDENT CODES
...............................................................
C—I
INTERNAL
REGISTERS
.........................................................
D—1
SWITCH
SETTINGS FOR THE DIFFERENT
ND- 100 MODULES ................................................................
E—1
Switches
on the CPU Module
(3002) ................................
E—I
ALD
—
Automatic Load Descriptor
...............................
E—I
Console:
Speed Setting for Console
Terminal .............
E—2
Switches
on Floppy and 4 Terminals Module
(3010)
........ 5—2
1 Floppy
Disk System ....................................................
E—3
2 Terminal
Group ...........................................................
E—3
3 Initial Baud Rate for Terminals
...................................
E-4
Switches on Memory
Modules (3005) ...............................
E—5
Switches on the 10MB
Disk Module (3004) ......................
E—6
Switch
Setting on the Pertec
magnetic
Tape Module (3006) ...........................................................
E—7
Switch
Setting on ND-100 Bus
Adapter (3008)
.................
E-8
Switch
Setting on Local l/O
Bus (3009) ............................
E—9
OPERAI | I IOR’S
COMMUNICATION INSTRUCTION
SURVEY ................................................................................
F—I
Control Functions
(Does not affect DISPLAY)
..................
F-—1
Display
Functions (Affects
only DISPLAY) ........................
F—1
Monitor
Functions (Also
shown on DISPLAY)
..................
F——2
ND-IOO
TECHNICAL
SPECIFICATIONS
.................................
G—I
Specifications-
....................................
'
...............................
G-I
Physical
..............................................................................
G—2
ND-06.014.02

1.1
1—1
INTRODUCTION
TO
ND-100
GENERAL
C HA
HA C
TERIS‘ TICS
ND-100
is a general purpose
computer
and
it is used in
many applications
like:
-
Commercial
data processing.
—
Research.
-—
Education.
—
Process
control.
ND-100
is completely
software
compatible
with
NORD 10/8
and runs the
same
operating
system,
SINTRAN
lll NS.
The ND-100
Central
Processing
Unit
(CPU)
is
placed
on a single
module. The word
length
is 16 bits
in parallel.
TERMINAL
Data
processing
application
Figure
7.7: The
Operating
System
S/NTRAN
III/VS
allows
the ND- 700
to be
used in many
Applicatidns.
N D-06.014.02

N
D-06.014.02

1
.2
ND-
700
FUNCTIONAL
MODULES
1 .2.1
General
A standard ND-100
printed board
module
size is 366.8
mm
x 280 mm.
The board
size, together
with the use
of Large
Scale
Integrated
(LSl)
circuits,
allows:
—
Small
physical
dimensions.
-
Closely related
functions
placed
on the same
module,
thus reducing
external
wiring to
a minimum.
Communication
between
ND-100
functional
modules
is done through
an advanced
high-speed
bus, called
ND-iOO
bus. The
ND-100 bus
is a printed
back plane. The
bus
is available in two
versions,
one for connecting
12 modules
and one for con-
necting 21 modules.
The two
versions are
mounted
in
different card crates and
dif-
ferent cabinets.
280 mm
4
H
368.8
mm
Figure
7.2: The Standard
ND- 100
Printed
Board
Module.
ND-06.014.02

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ND-06.014.02

1.2.2
ND- 700
Central
Processing
Unit (CPU)
Module
The CPU module
contains,
in addition to
the CPU
itself:
—
A real-time
clock.
—
A current
loop terminal interface
with switch
selectable speeds,
110
-
9600
baud/ bps
(bits per second).
'
—
Power fail and
automatic restart.
N D-06.014.02

1.2.2.1
1—6
CPU Characteristics
The Processor
ND-iOO
CPU
is a 16 bit parallel processor designed around the
bit slice ALU
(arith-
metic logic unit)
element.
The processor is controlled
by a microprogram. The following
is implemented
in
the
microprogram:
—-
All instructions.
—
Operator communication.
--
Built-in
test routines.
—
Bootstrap
loaders.
The microprogram
is physically located in a 2k word by 64 bit
Read Only
Memory
(ROM).
One microinstruction is fetched and executed in
the internal CPU
cycle
time.
The cycle
time is 150 ns for the fast CPU and 190 ns
for the slow version.
Instruction
Prefetch
A fast processor
should not have to wait for instructions.
In order to
reduce
instruction fetch waiting time,
the ND-lOO CPU will normally hold
two instruc-
tions, the current executing instruction and
the next one. This is
accomplished by
fetching
the next instruction while executing
the
current
instruction.
Special Feature
To allow dynamic
microprogramming, a 256 word
by
64 bit writeable
control
store
is available
as an option.
Instruction
Set and Data Format
Although a standard
ND-iOO
word
is 16
bits, the computer has a comprehensive
instruction set which includes
operations
on:
—
Bits.
—
Bytes.
—
Single words.
—
Double words.
—
Triple
words.
--
Register file.
—
Fixed
or floating
point arithmetic (32
-
or
48
-
bit word).
ND-06.014.02

1 .2.
3
ND- 700 Architecture
1.2.3.1
General
Figure
1.4 shows the ND-100
bus structure.
The main
highway for data and
addresses in
the system is the
ND-100
bus. Data
and address flow
are shown by
the arrows.
4
N040
Nome
i---—-......
oaw
“_
l
BUS
“"*’
A
<h——>
L
CPU
ICONTROL/
l
MODULE
IDRIVER
'---———
MMS
“-
MM
UL
.
ODULE
MODULES
MMS
=
Memory
Management
System
Figure 7.4: ND-
700 Bus Structure
Physically, the bus
is organized as
a printed
backplane containing
12 or 21 "plug
in”
positions
for module
connection.
All communication
between
ND-100 modules
except
CPU, MMS and
CACHE
communication,
is
provided by this
bus. That is, the ND-100
bus
connects the:
—
CPU to the memory
system (including
MMS
and CACHE).
—
CPU to the input/output
system.
—
DMA controllers
to the memory
system (DMA
=
Direct
Memory
Access). DMA controller
is a special
device interface
module.
A
bus control/driver,
which is an integrated
part
of the CPU,
controls the activity
on the bus. This
common bus architecture
has
several advantages:
—
Uniform
connection
for all modules makes
the
system.flexible
and easy to
expand.
—
No external wiring of
busses gives a
more reliable
system.
—
No overhead
in connecting several
busses
between source
and destination
makes a faster system (one crate
system
only).
ND-06.014.02