Nuvoton NAU88L24 User manual

Apr 11, 2022 Page 1 of 96 Rev 2.1
NAU88L24
Ultra-Low Power Audio CODEC with Stereo Class D Drivers and Ground-
Referenced Headphone Amplifier with Advanced Headset Detection
GENERAL DESCRIPTION
The NAU88L24 is an ultra-low power high performance audio codec designed for smartphone, tablet PC, and other
portable devices that supports both analog and digital audio functions. It includes one I2S/PCM interface, one digital
mixer, two high quality DACs, two high quality ADCs, two mono differential or one stereo differential analog microphone
inputs, four analog single-ended microphone inputs, four digital PDM microphone inputs, one single ended stereo
auxilary or one differential mono inputs, one differential HS mic input, one stereo 2.9W class D loudspeaker amplifier
driver for 4 Ω loading and 5V supply, and one stereo class G headphone amplifier with automatic headset detection.
The advanced on-chip signal processing engine that includes dynamic range compressors (DRC), 5-band parametric
equalizer (PEQ), and programmable high pass and notch filter block, can maximize audio quality and eliminate any
undesirable frequency components.
The NAU88L24 also has powerful headset detection that supports jack insertion / ejection, microphone detection,
distinct key / short key / long key / key release detection features as well as an integrated frequency locked loop (FLL)
to support various clocks.
FEATURES
DAC: 103dB SNR (A-weighted) @ 0dB gain, 1.8V
and -77dB THD @ 20mW and RL= 32Ω, DAC
playback to headphone output mode
ADC: 100dB SNR (A-weighted) @ 0dB MIC gain,
1.8V, Fs = 48KHz and -85dB THD, 1.8V, MIC gain
6dB, OSR 128x
1 Digital I2S/PCM I/O port
Dynamic Range Compressor (DRC)
5 Band Parametric Equalizer
1 Headset Microphone, 4 Analog or 4 Digital PDM
MIC input supports
Stereo .97W Class D Loudspeaker @ 4.2V, 8Ω,
1% THD+N (1.38W @ 5.0V, 8Ω, 1% THD+N)
Class G Headphone Amplifier (27mW @ 32Ω, 1%
THD+N)
Stereo Auxiliary Input
Sampling rate from 8K to 96 KHz
Headset Detection
Jack Insertion and Ejection Detection
MIC Detection and Distinct Keys Detection
Package:
QFN-48 (6X6mm, 0.4mm Pitch) package
56 Balls WLCSP package with 0.4mm Pitch
package
Applications
Tablets / Ultra-Portable Laptops
Smartphones
Audio Docking Systems
Portable Game Players
Cameras

Apr 11, 2022 Page 2 of 96 Rev 2.1
Block Diagram
Charge
Pump
ADC
Ʃ
Ʃ
Ʃ
Ʃ
MIC1+/DMCLK1
AUX_L/MONO+
MIC1-/DMDATA1
MIC2+/AUX_R/DMCLK2
MONO-/HSMIC+
MIC2-/DMDATA2
HSMIC-
ADC
MICBIAS
MICBIAS
ADC
MICDET
FLL
MUX
MCLK
BCLK
FS
SCLK
SDIO
GPIO1
IRQ
I2C Slave
& Registers
ADC Effect
Volume
HPF
NF
DRC
DMIC
Interface
& MUX
DMCLK1/2
DMDATA1/2
Digital Audio
Interface
DAC Effect
Volume
DRC
DACIN
ADCOUT
BCLK
FS
VDDC VDDB VSSD VDDA(2) VREF VSSA(2) VDDSPK(2) VSSSPK(2) VDDMIC VSSMIC
DAC
Ʃ
Ʃ
Ʃ
Ʃ
Jack
Detection
HPR
SPKOUTR+
SPKOUTR-
SPKOUTL+
SPKOUTL-
HPCOM
HPL
VDDCP
CPOUTP
VSSCP
CPCB
CPOUTN
CPCA
Selector/
Mixer
Selector/
Mixer
JKDET
DAC
QFN 48
Charge
Pump
MICBIAS
MICDET
FLL
MUX
MCLK
BCLK
FS
SCLK
SDIO
IRQ
ADC Effect
Volume
HPF
NF
DRC
DMIC
Interface
& MUX
DMCLK1/2
DMDATA1/2
DAC Effect
Volume
HPF
DRC
DACIN
ADCOUT
BCLK
FS
VDDC VDDB VSSD VDDA(2) VREF VSSA(2) VDDSPK(2)
VSSSPK(2)
VDDMIC
VSSMIC
VDDCP
CPOUTP
VSSCP
CPCB
CPOUTN
CPCA
JKDET
Digital Audio
Effects
5 Band PEQ
Mixers
Sidetone
Companding
I2S/PCM
Jack Detection
MICBIAS
ADC
I2C Slave
& Registers
Headset Detection
• Jack Insertion / Ejection
• MIC Detection
• Button Detection
• Speaker Impedance Detection
• Crosstalk Suppression
ADC
Ʃ
Ʃ
Ʃ
Ʃ
MIC1+/DMCLK1
AUX_L/MONO+
MIC1-/DMDATA1
MIC2+/DMCLK2
AUX_R/HSMIC+
MIC2-/DMDATA2
HSMIC-
ADC
Selector/
Mixer
DAC
Ʃ
Ʃ
Ʃ
Ʃ
HPR
SPKOUTR+
SPKOUTR-
SPKOUTL-
HPCOM
HPL
Selector/
Mixer
DAC
SPKOUTL+
IFSEL
VCCP1
GPIO4/SDO
MONO-
56 Balls WLCSP

Apr 11, 2022 Page 3 of 96 Rev 2.1
Table of Contents
BLOCK DIAGRAM ........................................................................................................................................2
PIN DIAGRAM-QFN48..................................................................................................................................6
PIN DIAGRAM-WLCSP.................................................................................................................................7
Ordering Information.................................................................................................................................................7
PIN DESCRIPTION-QFN48..........................................................................................................................8
PIN DESCRIPTION-56 BALLS WLCSP .....................................................................................................10
ELECTRICAL CHARACTERISTICS...........................................................................................................12
1GENERAL DESCRIPTION................................................................................................................15
1.1 Inputs.........................................................................................................................................................15
1.2 Outputs......................................................................................................................................................15
1.3 ADC, DAC and Digital Signal Processing..................................................................................................15
1.4 Digital Interfaces........................................................................................................................................15
2POWER SUPPLY..............................................................................................................................15
2.1 Power on and off reset...............................................................................................................................16
3INPUT PATH DETAILED DESCRIPTIONS ......................................................................................16
3.1 Analog Microphone Inputs .........................................................................................................................16
3.1.1 VREF.....................................................................................................................................................17
3.1.2 MIC Bias.............................................................................................................................................18
3.2 Digital MIC Inputs.......................................................................................................................................18
3.3 Line Inputs .................................................................................................................................................19
3.4 Programmable Gain Amplifier (PGA).........................................................................................................19
4ADC DIGITAL BLOCK.......................................................................................................................19
4.1 ADC Dynamic Range Compressor (DRC) .................................................................................................20
4.1.1 Level Estimation .................................................................................................................................20
4.1.2 Static Curve........................................................................................................................................20
4.2 ADC Digital Volume Control.......................................................................................................................22
4.3 ADC Programmable High Pass Filter.........................................................................................................22
4.4 Programmable Notch Filter........................................................................................................................23
4.5 ADC Path Digital Mixer..............................................................................................................................24
4.65-Band Equalizer .......................................................................................................................................24
4.7 Companding...............................................................................................................................................25
4.8 Additional ADC Application Notes..............................................................................................................25
5DAC DIGITAL BLOCK.......................................................................................................................25
5.1 DAC Dynamic Range Control (DRC) .........................................................................................................26
5.1.1 Level Estimation .................................................................................................................................26
5.1.2 Static Curve........................................................................................................................................26
5.2 DAC Digital Volume Control.......................................................................................................................27
5.3 DAC Soft Mute...........................................................................................................................................27
5.4 5-Band Equalizer .......................................................................................................................................28
5.5 DAC Path Digital Mixer with Side tone.......................................................................................................28
5.6 Companding...............................................................................................................................................29

Apr 11, 2022 Page 4 of 96 Rev 2.1
5.6.1 µ-law...................................................................................................................................................30
5.6.2 A-law...................................................................................................................................................30
5.7 Additional DAC Application Notes..............................................................................................................30
6CLOCKING AND SAMPLE RATES ..................................................................................................30
6.1 Frequency Locked Loop (FLL)...................................................................................................................32
7CONTROL INTERFACES.................................................................................................................34
7.1 2-Wire-Serial Control Mode (I2C Style Interface) .......................................................................................35
7.2 2-Wire Protocol Convention.......................................................................................................................35
7.3 2-Wire Write Operation..............................................................................................................................35
7.4 2-Wire Read Operation..............................................................................................................................36
7.5Digital Serial Interface Timing....................................................................................................................36
7.6 Software Reset ..........................................................................................................................................37
8DIGITAL AUDIO INTERFACES ........................................................................................................37
8.1 Right-Justified Audio Data..........................................................................................................................38
8.2 Left-Justified Audio Data............................................................................................................................38
8.3 I2S Audio Data...........................................................................................................................................38
8.4 PCM A Audio Data.....................................................................................................................................39
8.5 PCM B Audio Data.....................................................................................................................................39
8.6 PCM Time Slot Audio Data........................................................................................................................39
8.7 TDM I2S Audio Data..................................................................................................................................40
8.8 TDM PCM A Audio Data............................................................................................................................40
8.9 TDM PCM B Audio Data............................................................................................................................41
8.10 TDM PCM Offset Audio Data.....................................................................................................................41
9OUTPUTS..........................................................................................................................................43
9.1 Stereo Class D Speaker Outputs...............................................................................................................43
9.1.1 Differential Mixer.................................................................................................................................43
9.1.2 Device Protection................................................................................................................................44
9.1.3 Class D without filter...........................................................................................................................44
9.1.4 Class D Filters ....................................................................................................................................45
9.1.5 NAU88L24 EMI performance..............................................................................................................46
9.2 Class G Headphone Driver and Charge Pump..........................................................................................46
10 HEADSET DETECTION....................................................................................................................47
10.1 Jack Detection ...........................................................................................................................................47
10.2 Microphone Detection................................................................................................................................48
10.3 Key/Button Detection.................................................................................................................................48
10.3.1 SAR ADC............................................................................................................................................51
10.4 Jack Interrupt Sequence............................................................................................................................52
10.4.1 Jack Insert ..........................................................................................................................................52
10.4.2 Jack Eject ...........................................................................................................................................52
10.4.3 Short Key Press..................................................................................................................................52
10.4.4 Key Release .......................................................................................................................................52
11 BASIC REGISTER SEQUENCES.....................................................................................................53
11.1 To enable VREF and General Bias............................................................................................................53
11.2 Enable/Disable Input PGA.........................................................................................................................53

Apr 11, 2022 Page 5 of 96 Rev 2.1
11.3 Enable analog ADC ...................................................................................................................................53
11.4 Enable/Disable FLL....................................................................................................................................53
11.5 Enable/Disable DAC..................................................................................................................................54
11.6 Enable/Disable Class D Driver...................................................................................................................54
11.7 Enable/Disable Headphone .......................................................................................................................54
11.8 Enable DAC to Headphone Low Power MP3 Playback Mode ...................................................................55
11.9 Enable DAC to Class D Low Power MP3 Playback Mode.........................................................................55
11.10 Jack Detection ...........................................................................................................................................55
12 CONTROL AND STATUS REGISTERS ...........................................................................................57
13 TYPICAL APPLICATION DIAGRAM.................................................................................................90
14 PACKAGE INFORMATION...............................................................................................................91
14.1 QFN 48L 7X7MM^2 ...................................................................................................................................91
14.2 QFN48L 6x6MM^2.....................................................................................................................................92
14.3 WLCSP 56 Balls ........................................................................................................................................93
ORDERING INFORMATION.......................................................................................................................94
REVISION HISTORY ..................................................................................................................................95
IMPORTANT NOTICE ................................................................................................................................96

Apr 11, 2022 Page 6 of 96 Rev 2.1
Pin Diagram-QFN48
Top View
1
1213 24
36
25
48 37
VSSSPK
SPKOUTL-
VDDSPK
SPKOUTR-
VSSSPK
SPKOUTR+
VDDSPK
IRQ
GPIO1
SDIO
SCLK
FS
CPOUTP
VDDA
VSSA
VREF
MICDET
VDDMIC
MICBIAS
VDDA
VSSA
MIC1-/DMDATA1
MIC1+/DMCLK1
AUX_L/MONO+
VSSCP CPOUTN CPCB
CPCA HPL HPR HPCOM TEST VSSSPK VDDSPK VDDSPK
SPKOUTL+
MONO-/HSMIC+
MIC2-/DMDATA2
MIC2+/AUX_R/DMCLK2
HSMIC-
JKDET
VDDC
VSSD
VDDB MCLK
BCLK
DACIN
ADCOUT
Note: NAU88L24IG (6mm X 6mm QFN 48 pin) have same pin diagram and pin descriptions

Apr 11, 2022 Page 7 of 96 Rev 2.1
Pin Diagram-WLCSP
Top View
VDDB
ADC
OUT
DACIN
FS
VREF
IRQ
MCLK
SPK
VDD
SPK
VSS HPR
HPL
MIC
BIAS
MIC
DET
VDD
MIC
CP
OUTN
CP
OUTP
CPCB
BCLK IFSEL
HP
COM
CPCA
GP2/
JKDET
GP4/
SDO
SCLK
GP1/
CSB
SPK
VDD
SPK
VSS
SPK
VDD
SPK
VSS SPK
VDD VSS
CP
VCC
P1
F
E
D
C
B
A
G
H
1234567
TEST
0.4mm
0.4mm
3.66mm
3.22mm
VSSA
AUXL/
MONO+
VDDA
VDDA
MIC2-/
DMDATA2
HSMIC+
MIC2+/
DMCLK2
MIC1+/
DMCLK1
VSSA
MIC1-/
DMDATA1
AUX_R/
MONO-
HSMIC-
VSSD
VDDC
SPKR+
SPKR-
SPKL-
SPKL+
SDIO
Ordering Information
Part Number
Dimension
Package
Package
Material
NAU88L24YG
7 x 7 mm
QFN-48
Green
NAU88L24IG
6 X 6 mm
QFN-48
Green
NAU88L24VG
3.22 X 3.66 mm
56 Balls WLCSP
Green

Apr 11, 2022 Page 8 of 96 Rev 2.1
Pin Description-QFN48
Pin #
Name
Type
Functionality
1
AUX_L/MONO +
Analog Input
PGA Mono+ or Left channel Auxiliary Analog
Input
2
MIC1+/DMCLK1
Analog Input / Digital
Output
PGA MIC1+ Analog Input or Digital Microphone 1
Clock Output
3
MIC1-/DMDATA1
Analog Input / Digital
Input
PGA MIC1- Analog Input or Digital Microphone 1
Data Input
4
VSSA
Ground
Analog Supply Ground
5
VDDA
Supply
Analog Supply
6
MICBIAS
Analog Output
Microphone Bias Output
7
VDDMIC
Supply
Microphone supply
8
MICDET
Analog Input
Microphone button detection input
9
VREF
Analog I/O
Internal DAC & ADC voltage reference decoupling
I/O
10
VSSA
Ground
Analog Supply Ground
11
VDDA
Supply
Analog Supply
12
CPOUTP
Analog I/O
Charge Pump positive voltage
13
VSSCP
Ground
Charge Pump Supply ground
14
CPOUTN
Analog I/O
Charge Pump negative voltage
15
CPCB
Analog I/O
Charge Pump switching capacitor node B
16
CPCA
Analog I/O
Charge Pump switching capacitor node A
17
HPL
Analog Output
Headphone left channel output
18
HPR
Analog Output
Headphone right channel output
19
HPCOM
Analog Input
Headphone ground reference
20
TEST
N/C
Class-D amplifier Test point
21
VSSSPK
Ground
Class-D amplifier supply ground
22
VDDSPK
Supply
Class-D amplifier supply
23
VDDSPK
Supply
Class-D amplifier supply
24
SPKOUTL+
Analog Output
Class-D amplifier Left Channel positive Output
25
VSSSPK
Ground
Class-D amplifier supply ground
26
SPKOUTL-
Analog Output
Class-D amplifier Left Channel negative Output
27
VDDSPK
Supply
Class-D amplifier supply
28
SPKOUTR-
Analog Output
Class-D amplifier Right Channel negative Output
29
VSSSPK
Ground
Class-D amplifier supply ground
30
SPKOUTR+
Analog Output
Class-D amplifier Right Channel positive Output
31
VDDSPK
Supply
Class-D amplifier supply
32
IRQ
Digital Output
Programmable Interrupt Output
33
GPIO1
Digital I/O
General Purpose IO (I2C)
34
SDIO
Digital I/O
Serial Data for I2C or SPI
35
SCLK
Digital Input
Serial Data Clock for I2C or SPI
36
FS
Digital I/O
Frame Sync input or output for I2S or PCM data
37
ADCOUT
Digital Output
Serial Audio data Output for I2S or PCM data
38
DACIN
Digital Input
Serial Audio data input for I2S or PCM data
39
BCLK
Digital I/O
Serial data bit clock input or output for I2S or PCM
data
40
MCLK
Digital Input
CODEC Master clock input
41
VDDB
Supply
Digital IO Supply
42
VSSD
Ground
Digital IO ground

Apr 11, 2022 Page 9 of 96 Rev 2.1
43
VDDC
Supply
Digital core supply
44
JKDET
Analog Input
Jack detect input
45
HSMIC-
Analog Input
Headset Microphone negative Analog input
46
MIC2+/AUX_R /DMCLK2
Analog Input / Digital
Output
PGA MIC2+ or AUXR Analog Input or Digital
Microphone 2 Clock Output
47
MIC2-/DMDATA2
Analog Input / Digital
Input
PGA MIC2- Analog Input or Digital Microphone 2
Data Input
48
MONO-/HSMIC+
Analog Input
PGA Mono-, or Headset Microphone positive
Analog Input
Note: Analog I/O supply by VDDA, and Digital I/O supply is VDDB. Pins 2,3, 46,47 are connected to VDDA

Apr 11, 2022 Page 10 of 96 Rev 2.1
Pin Description-56 Balls WLCSP
Pin #
Name
Type
Functionality
A1
GPIO4/SDO
Digital I/O
General Purpose IO / 3 Wire Data Output
A2
DACIN
Digital Input
Serial Audio data input for I2S or PCM data
A3
VDDB
Supply
Digital IO Supply
A4
VSSD
Ground
Digital IO ground
A5
HSMIC-
Analog Input
Headset Microphone negative Analog input
A6
MIC2+/DMCLK2
Analog Input / Digital
Output
PGA MIC2+ Analog Input or Digital Microphone
2 Clock Output
A7
MIC2-/DMDATA2
Analog Input / Digital
Input
PGA MIC2- Analog Input or Digital Microphone
2 Data Input
B1
SCLK
Digital Input
Serial Data Clock for I2C or SPI
B2
ADCOUT
Digital Output
Serial Audio data Output for I2S or PCM data
B3
MCLK
Digital Input
CODEC Master clock input
B4
VDDC
Supply
Digital core supply
B5
JKDET
Analog Input
General purpose IO or Jack detect input
B6
AUX_R/HSMIC+
Analog Input
Right channel Auxiliary Analog Input or Headset
Microphone positive Analog Input
B7
AUX_L/MONO +
Analog Input
PGA Mono or Left channel Auxiliary Analog
Input
C1
SDIO
Digital I/O
Serial Data for I2C or SPI
C2
FS
Digital I/O
Frame Sync input or output for I2S or PCM data
C3
BCLK
Digital I/O
Serial data bit clock input or output for I2S or
PCM data
C4
IFSEL
Digital I/O
Select Control Interface for 3 wire or 2 wire mode
C5
MONO-
Analog Input
PGA Mono
C6
MIC1+/DMCLK1
Analog Input / Digital
Output
PGA MIC1+ Analog Input or Digital Microphone
1 Clock Output
C7
VSSA
Ground
Analog Supply Ground
D1
GPIO1/CSB
Digital I/O
General Purpose IO (I2C) or Chip Select Bar (SPI)
D2
IRQ
Digital Output
Programmable Interrupt Output
D5
MIC1-/DMDATA1
Analog Input / Digital
Input
PGA MIC1- Analog Input or Digital Microphone
1 Data Input
D6
MICBIAS
Analog Output
Microphone Bias Output
D7
VDDA
Supply
Analog Supply
E1
VDDSPK
Supply
Class-D amplifier supply
E2
SPKOUTR+
Analog Output
Class-D amplifier Right Channel positive Output
E3
TEST
N/C
Class-D amplifier Test point
E5
VREF
Analog I/O
Internal DAC & ADC voltage reference
decoupling I/O
E6
VDDMIC
Supply
Microphone supply
E7
MICDET
Analog Input
Microphone button detection input
F1
VSSSPK
Ground
Class-D amplifier supply ground
F2
SPKOUTR-
Analog Output
Class-D amplifier Right Channel negative Output
F3
VDDSPK
Supply
Class-D amplifier supply
F4
HPL
Analog Output
Headphone left channel output
F6
VSSA
Ground
Analog Supply Ground
F7
VDDA
Supply
Analog Supply
G1
VDDSPK
Supply
Class-D amplifier supply
G2
SPKOUTL-
Supply
Class-D amplifier Left Channel negative Output
G3
VSSSPK
Ground
Class-D amplifier supply ground
G4
HPR
Analog Output
Headphone right channel output

Apr 11, 2022 Page 11 of 96 Rev 2.1
G5
CPCA
Analog I/O
Charge Pump switching capacitor node A
G6
CPOUTP
Analog I/O
Charge Pump positive voltage
G7
VCCP1
Supply
Charge Pump Supply
H1
VSSSPK
Ground
Class-D amplifier supply ground
H2
SPKOUTL+
Analog Output
Class-D amplifier Left Channel positive Output
H3
VDDSPK
Supply
Class-D amplifier supply
H4
HPCOM
Analog Input
Headphone ground reference
H5
CPOUTN
Analog I/O
Charge Pump negative voltage
H6
CPCB
Analog I/O
Charge Pump switching capacitor node B
H7
VSSCP
Ground
Charge Pump Supply ground
Note: Analog I/O supply by VDDA, and Digital I/O supply is VDDB. Pins A6,A7, C6, D5 are connected to
VDDA

Apr 11, 2022 Page 12 of 96 Rev 2.1
Electrical Characteristics
Conditions: Shutdown ModeVDDA= VDDB = VDDC = 1.8V; VDDSPK = VDDMIC= 4.2V.
RL(Loudspeaker) = 8 Ω+68uH, RL(Headphone) = 32 Ω, f = 1kHz, MCLK=12.288MHz, unless otherwise specified. Limits
apply for TA= 25°C
Symbol Parameter Conditions Typical Limit Units
(Limit)
ISD Shutdown Current
V
DD
A
0.2
1
µA
VDDA when VDDC=1.2V
18.2
V
DD
B
0.2
1
V
DD
C
2
10
VDDSPK
0.2
1
VDDMIC
0.2
1
IDD
Standby Mode
MCLK off, Jack Insertion IRQ enabled
5
µA
DAC Speaker Amplifier Output
POOutput Power
DAC Input, V
DD
SPK
= 4.2V, f = 1kHz,
20kHz BW
RL = 4Ω, THD+N = 1%
1.6 W
RL = 8Ω, THD+N = 1% .97 W
V
DD
SPK = 5.0V, f = 1kHz, 20kHz BW
RL = 8Ω, THD+N = 1%
1.38 W
THD+N
Total Harmonic Distortion +
Noise
RL = 8Ω, f = 1kHz, PO= 300mW 0.013 %
SNR Signal to Noise Ratio
P
O
= 1W, V
DD
SPK
= 4.2V, DAC Input,
f = 1kHz, A-Weighted
100 dB
PSRR Power Supply Rejection Ratio
f
RIPPLE
= 217Hz, V
RIPPLE
= 200mV
PP
Input Referred, SPK_GAIN = 0dB
DAC Input, DAC_Gain = 0dB, Ripple
Applied to VDDSPK = 4.2V
80 dB
ηEfficiency VDDSPK= 4.2V, at 1% THD, RL = 8Ω 86 %
XTALK Channel Crosstalk
Left Channel to Right Channel, P
O
=
500mW, f = 1kHz
-100 dB
DAC Headphone Amplifier Output
POOutput Power
Stereo R
L
= 32Ω, DAC Input, CPV
DD
=
1.8V, f = 1kHz, 20kHz BW, THD+N =
1%
27 mW
Pc Power consumption
MP3 Playback in Quiescent, VDDC =
1.2V, RL= 32 ohm, fs = 44.1KHz
6 mW
MP3 Playback with 1mW/Channel,
1KHz Stereo Output, VDDC = 1.2V, RL
= 32 ohm, fs = 44.1KHz
14.5 mW
THD+N
Total Harmonic Distortion +
Noise
RL = 32Ω, f=1kHz, PO= 20mW -77 dB
SNR Signal to Noise Ratio
VOUT = 1V
RMS
, DAC Input, DAC_Gain
= 0dB, HP_Gain = 0dB, Digital Zero
Input, f = 1kHz, A-Weighted
103 dB
PSRR Power Supply Rejection Ratio
f
RIPPLE
= 217Hz, V
RIPPLE
= 200mV
P_P
Input Referred, HP_GAIN = 0dB
DAC Input, DAC_Gain = 0dB Ripple
Applied to VDDA
80 dB
VOS Output Offset Voltage
HP_Gain = 0dB, DAC_Gain
= 0dB,
DAC Input
±0.25 ±1 mV
XTALK Channel Crosstalk
Left Channel to Right Channel, P
O
=
3mW, f= 1kHz
-75 dB
Loading Capacitance External capacitance at HPL and HPR <500 pF

Apr 11, 2022 Page 13 of 96 Rev 2.1
Symbol Parameter Conditions Typical Limit Units
(Limit)
ADC
THD+N
ADC Total Harmonic Distortion +
Noise
MIC Input, MIC_GAIN = -3dB, VIN =
1Vrms, f = 1kHz, Fs = 48kHz
-85 dB
SNR Signal to Noise Ratio
Reference = VOUT(0dBFS), A-
Weighted, MIC Input, MIC Gain =
0dB,fs = 8kHz, Mono Differential Input
99 dB
Reference = VOUT(0dBFS), A-
Weighted, MIC Input, MIC Gain =
6dB,fs = 8kHz, Mono Differential Input
98
Reference = VOUT(0dBFS), A-
Weighted, Stereo Input, Gain = 0dB,fs
= 48kHz
100 dB
PSRR Power Supply Rejection Ratio
V
RIPPLE
= 200mV
PP
applied to V
DD
A,
fRIPPLE = 217Hz, Input Referred,
MIC_GAIN = 0dB Differential Input
65 dB
FSADC
ADC Full Scale Input Level
VDDA= 1.8V
1
VRMS
Digital I/O
Parameter Symbol Comments/Conditions Min Max Units
Input LOW level VIL
VDDB = 1.8V
0.33*VDDB
V
VDDB = 3.3V
0.37*VDDB
Input HIGH level VIH
VDDB = 1.8V
0.67*VDDB
V
VDDB = 3.3V
0.63*VDDB
Output HIGH level VOH
I
Load
=
1mA
VDDB = 1.8V
0.9*VDDB
V
VDDB = 3.3V
0.95*VDDB
Output LOW level VOL
I
Load
=
1mA
VDDB = 1.8V
0.1*VDDB
V
VDDB=3.3V
0.05*VDDB

Apr 11, 2022 Page 14 of 96 Rev 2.1
Recommended Operating Conditions
Condition Symbol Min Typical Max Units
Digital Supply Range
VDDC
1.1
1.2
1.98
V
Digital Supply Range for FLL
operation and for Fs > 48KHz
V
DD
C
1.61
1.8
1.98
V
Digital I/O Supply Range
VDDB
1.6
1.8
3.6
V
Analog Supply Range
VDDA
1.6
1.8
2.0
V
Headphone Supply Range
VDDA
1.6
1.8
2.0
V
Loudspeaker Supply Range
VDDSPK
2.5
4.2
5.0
V
Microphone Bias Supply Voltage
VDDMIC
2.5
4.2
5.0
V
Temperature Range
TA
-40
+85
°C
CAUTION: The following conditions needed to be followed for regular operation: VDDMIC >VDDA -1.2V; VDDB > VDDC
– 0.6V.
Absolute Maximum Ratings
Parameter Min Max Units
Digital Supply Range
-0.3
2.2
V
Digital I/O Supply Range
-0.3
6.0
V
Analog Supply Range
-0.3
2.2
V
Headphone Supply Range
-0.3
2.2
V
Loudspeaker Supply Range
-0.3
6.0
V
Microphone Bias Supply Voltage
-0.3
6.0
V
Voltage Input Digital Range
DGND - 0.3
VDD + 0.3
V
Voltage Input Analog Range
AGND - 0.3
VDD + 0.3
V
Junction Temperature, TJ
-40
+150
°C
Storage Temperature
-65
+150
°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods. Exposure to such conditions may
adversely influence product reliability and result in failures not covered by warranty.
CAUTION: The following conditions need to be followed for maximum ratings: VDDMIC >VDDA -1.2V; VDDB > VDDC –
0.6V.

Apr 11, 2022 Page 15 of 96 Rev 2.1
1General Description
NAU88L24 is Nuvoton’s generation of ultra-low power CODECs that have both analog and digital blocks
operating at 1.8V and a digital core that is able to operate at 1.2V. This CODEC includes new DSP
functions including DRC (Dynamic Range Compression), equalizer, notch filters, and high pass filters. The
Loudspeaker and MIC bias supplies have also been upgraded to support higher voltages up to 5V.
1.1 Inputs
The NAU88L24 provides multiple analog inputs to acquire and process audio signals from microphones or
other sources with high fidelity and flexibility. There is a left and right input path with four input pins each that
can be used to capture signals from single-ended and differential sources. Each channel has a fully
differential programmable gain amplifier (PGA), which can be configured to mix any combination of the four
inputs. The outputs of the PGAs connect to the ADCs.
There are also four alternative digital microphone inputs that use the two stereo inputs MIC1+/- and MIC2+/-
as DMCLK1/2 and DMDATA1/2, respectively. DMCLK outputs select between the stereo microphones
depending on the phase of the clock that has a maximum frequency of 3.25MHz.
1.2 Outputs
NAU88L24 has two pairs of outputs: stereo Class D speaker outputs and ground-referenced Class G
headphone outputs that are fed by two DACs. The stereo class D amplifier has a gain range from 0dB to
24dB, and the headphone amplifier has a gain range of -30dB to 6dB.
The Class D speaker amplifier is powered by a separate power supply VDDSPK, which can go up to 5V.
This amplifier is capable of delivering up to 2.9W into a 4Ω load with a 5V supply.
The Class G headphone amplifier is powered by the charge pump output voltages CPOUTP and CPOUTN.
When there is no loading the CPOUTP is equal to VDDA, and CPOUTN is equal to –VDDA.
1.3 ADC, DAC and Digital Signal Processing
The NAU88L24 has two independent high quality ADCs and DACs. These are high performance 24-bit
sigma-delta converters, which are suitable for a very wide range of applications.
The ADCs and DACs have functions that individually support analog mixing and routing. The ADC and DAC
blocks also support advanced digital signal processing subsystems that enable a very wide range of
programmable signal conditioning and signal optimizing functions. All digital processing is done with 24-bit
precision to minimize processing artifacts and maximize the audio dynamic range supported by the
NAU88L24.
The ADCs and DACs can be enabled to support dynamic range compressors (DRC), high pass filters, and
notch filters that are highly versatile. The DRC can be programmed to limit the maximum output level and/or
boost a low output level. The high pass filters are intended for DC-blocking or low frequency noise reduction,
such as reducing unwanted ambient noise or “wind noise” on a microphone input. The notch filter can also
be programed to greatly reduce a specific frequency band or frequency.
The digital signal processing subsystem also provides a 5-Band Equalizer that can be applied to either the
ADC audio path or the DAC audio path, but not both simultaneously.
1.4 Digital Interfaces
Command and control of the device is accomplished by using a 2-wire serial control interface. This simple,
but highly flexible interface is compatible with most commonly used command and control serial data
protocols and host drivers.
The digital audio I/O data streams transfer separately from command and control using either I2S or PCM
audio data protocols. When in PCM mode, the NAU88L24 can support time-division multiplexing (TDM)
allowing for up to 4 concurrent PCM input and output channels.
These simple but highly flexible interface protocols are compatible with most commonly used serial data
protocols, host drivers, and industry standard I2S and PCM devices.
2Power Supply
This NAU88L24 has been designed to operate reliably using a wide range of power supply conditions and
power-on/power-off sequences. However, because of existence of ESD protection diodes between the
supplies, that will have impact on the application of the supplies. Because of these diodes, the following
conditions need to be met:

Apr 11, 2022 Page 16 of 96 Rev 2.1
VDDMIC > VDDA-1.2V and VDDB > VDDC – 0.6V.
Application Notes:
•To reduce leakage, GPIO_SEL REG0X1A [6] needs to set to 1’b.
2.1 Power on and off reset
The NAU88L24 includes a power on and off reset circuit on chip that resets the internal logic to its default
state when the VDDA and VDDC supplies power up. This reset function will be automatically and internally
generated when the power supplies are too low for reliable operation of the internal logic circuitry. VDDA
and VDDC must drop below approximately 1.0Vdc and 0.55Vdc, respectively. Note that this is much lower
than the required voltage for normal operation and the values here are mentioned only as general insight into
the system design.
When VDDA and VDDC drop below their threshold values, the reset is held on until the power supplies
return to a minimum voltage specified in the parameter table. Once these voltages are reached, the reset is
held on for a minimum of 6 µs and then it is released. At this point, the registers can be written to through
the control interface. Note that it is recommended to write to register 0x00 twice upon power up. This will
reset all registers to their default state.
An additional internal RC filter based circuit has been added to help the circuit respond to faster ramp rates
(~10µs) and generate the desired reset period width (≥6 µs). This filter is also used to eliminate any supply
glitches (typically 50ns) that could cause a false reset condition.
Application Notes:
•VDDA ramp up time for a guaranteed power on reset needs to be less than 50msec. The VDDA ramp down
time for a guaranteed power off reset needs to be less than 125msec. If the ramp down rate is too slow (no
pull down), then we can enable the minimum VREF impedance by BIAS_ADJ.VMIDSEL
REG0X66[5:4]=11 with BIAS_ADJ.VMIDEN REG0X66[6]=1, before shutdown in order to discharge
VDDA quickly.
3Input Path Detailed Descriptions
The NAU88L24 provides multiple inputs to acquire and process audio signals from microphones or other
sources with high fidelity and flexibility. There is a left and right input path with four input pins each, which
can be used to capture signals from single-ended and differential sources. Each channel has a fully
differential programmable gain amplifier (PGA), which can be configured to mix any combination of the four
inputs. The outputs of the PGAs are then fed into the ADCs.
All inputs are maintained at a DC bias of approximately ½ of the VDDA supply voltage. Connections to these
inputs should be AC-coupled by means of DC blocking capacitors suitable for the device application.
The NAU88L24 features two low-noise and differential microphone input pairs that are connected to a PGA
gain stage. This differential input structure is essential in noisy digital systems where amplification of low-
amplitude analog signals is necessary such as in portable digital media devices and cell phones.
Differential inputs are very useful to reduce ground noise in systems in which there are ground voltage differs
between different chips and other components. When properly implemented, the differential input
architecture offers an improved power-supply rejection ratio (PSRR) and higher ground noise immunity.
3.1 Analog Microphone Inputs
The NAU88L24 Analog microphone inputs can be setup in five different configurations:
1. Two differential analog microphones: MIC1+/MIC1- and MIC2+/MIC2-.
2. One pair of stereo analog microphones: MIC1± and MIC2±.
3. Four single ended analog microphones: MIC1+, MIC1-, MIC2+, and MIC2-.
4. One differential head set microphone (HSMIC+/HSMIC-), one MONO input or single-ended AUX_L, plus two
differential analog microphones.
5. Two single-ended head set microphones: HSMIC+ and HSMIC-.
The analog microphone inputs are followed by different attenuation stages before they are routed to the
variable PGA (Programmable Gain Amplifier) stage. The analog microphone inputs MIC1± and MIC2± are
routed through a 0dB or -6dB attenuation stage dependent on PGA_GAIN.M6DBL REG0X67[8] and
PGA_GAIN.M6DBR REG0X67[0], respectively. The rest of the inputs are routed through a variable
attenuation stage with a range from -46.5dB to 0dB dependent on
FEPGA_ATTENUATION.FEPGA_ATTNR REG0X7A[12:8]and FEPGA_ATTNL.FEPGA_ATTNL
REG0X7A[4:0]. By default, both types of inputs are attenuated by 0dB.

Apr 11, 2022 Page 17 of 96 Rev 2.1
After the attenuation stage, the inputs are routed through switches that can be set depending on application
requirements. Once the signal is through the switches, all input configurations are routed through an input
mixer and then to a programmable gain amplifier (PGA) that ranges from 0dB to 36dB in 2dB steps. This
amplifier can be set using FEPGA_II.FEPGA_GAINR REG0X78[9:5]and FEPGA_II.FEPGA_GAINL
REG0X78[4:0].
Application Notes:
•Each input has an input impedance of about 12kΩ.
•If the application has single ended MIC inputs, then the inputs can be tied off to VREF as single ended
inputs. FEPGA_SE.FEPGASEL REG0X79[3:0]and FEPGA_SE.FEPGASER REG0X79[11:8]are to set
left and right channel, respectively.
•When using single ended inputs, they should be AC coupled to ground to have better common-mode noise
rejection.
•If the application has large decoupling capacitors on the inputs, there is an option to pre-charge the
capacitors to minimized pops and clicks during startup. Please see register FEPGA_II.ADC_CTRL
REG0X78[15:10]for more details.
•Both MIC and Line inputs can be used simultaneously.
MONO-/HSMIC+
DMCLK1
FEPGA_ATTNL
M6DBL
Ʃ
Analog MIC Input Path
00XX
XX00
FEPGASEL
FEPGA_GAINL
AUXL±
0XX1
0X1X
FEPGA_MODEL
DMCLK1
DMDATA1
DMCLK2
DMDATA2
DMIC
Interface
ADCDATA
DMIC1EN/DMIC2EN
Digital MIC Input Path
To Left Audio
ADC
MONO-/HSMIC+
DMCLK2
FEPGA_ATTNR
M6BBR
Ʃ
00XX
XX00
FEPGASER
FEPGA_GAINR
AUXR±
Register: FEPGA_II
Register:
FEPGA_ATTENUATION
0XX1
0X1X
FEPGA_MODER
Register: FEPGA
Register: FEPGA_SE
To Right Audio
ADC
AUX_L/MONO+
MIC1-/DMDATA1
HSMIC-
MIC2-/DMDATA2
MIC1+
MIC2+/AUX_R
MIC1-
DMDATA1
MIC2-
DMDATA2
Figure 1: Microphone Input Block Diagram with Registers
3.1.1 VREF
The NAU88L24 includes a mid-supply, reference circuit that produces voltage close to VDDA/2 that is
decoupled to VSS through the VREF pin by means of an external bypass capacitor. Because VREF is used as

Apr 11, 2022 Page 18 of 96 Rev 2.1
a reference voltage for the majority of the NAU88L24, a large capacitance is required to achieve good power
supply rejection at low frequency, typically 4.7µF is used.
VREF voltage can be enabled by setting BIAS_ADJ.VMIDEN REG0X66[6] and the output impedance can
be set using BIAS_ADJ.VMIDSEL REG0X66[5:4].
Application Notes:
•Larger capacitances can be used but it will increase the rise time of VREF and delay the line output signal.
However, a pre-charge circuit has been included to help reduce the rise time.
•Due to the high impedance of the VREF pin, it is important to use a low leakage capacitor.
•A pre-charge circuit has been implemented to reduce the VREF rise time. Once charged, this can be disabled
using BOOST.PVDMFST REG0X76[13]to save power or prevent rapid changes in level due to fluctuations
in VDDA.
VMIDSEL
VREF Resistor Selection
VREF Impedance
00
Open, no resistor selected
Open, no impedance installed
01
50kOhm
25kOhm
10
250kOhm
125kOhm
11
5kOhm
2.5kOhm
Table 1: VREF Impedance Selection
VMIDEN
VDDA Pin
VREF Pin
VSSA Pin
4.7µF
Pre-Charge
VMIDSEL
5, 50, 250 kΩ
PDVMDFST
Register: BIAS_ADJ
Register: BOOST
Exterior
Connections
Figure 2: VREF Circuitry
3.1.2 MIC Bias
The NAU88L24 provides one MIC bias pin, which can be used to power electret and digital microphones.
This pin can be enabled by using MIC_BIAS.POWERUP REG0X74[8] and the level can be set by using
MIC_BIAS.MICBIASLVL1 REG0X74[2:0].
Application Notes:
•It is recommended that the microphones do not draw more than 4mA from the MICBIAS pin
•Low noise or low power mode can be enabled by setting MIC_BIAS.LOWNOISE REG0X74[10]to 1 or 0,
respectively.
•There is an internal tie-off option that can save the need to install an external resistor for connecting the
microphones. This can be enabled using MIC_BIAS.INT2KB REG0X74[14].
•If MICBIAS is used to power digital microphones, MIC_BIAS.MICBIASLVL1 REG0X74[2:0] set to 000
(VDDA) and the capacitor can be 100nF or 200nF. But then MICBIAS can only be used in low power mode.
If MICBIAS is used to power analog microphones, it is possible to omit the capacitor, but then the
MIC_BIAS.NOCAP REG0X74[6] bit has to be set high to ensure stability. If a capacitor is used,
MIC_BIAS.NOCAP REG0X74[6] has to be low to ensure stability. In this case a capacitor value of 1uF to
4.7uF can be used.
3.2 Digital MIC Inputs
In addition to analog inputs, the NAU88L24 is setup to handle up to four digital MIC inputs using the
DMCLK1/2 and DMDATA1/2 pins that are multiplexed with the MIC1/2+ and MIC1/2- pins, respectively.
Both DMDATA inputs are able to handle two digital microphones by selecting them alternately for each half
of the clock cycle.

Apr 11, 2022 Page 19 of 96 Rev 2.1
Application Notes:
•The clock phase for the selection of the digital MIC is configurable using
ENA_CTRL.DMIC_LCH_EDGE_ADC_CH01 REG0X01[14]and
ENA_CTRL.DMIC_LCH_EDGE_ADC_CH23 REG0X01[15].
•The DMCLK rate can be selected using CLK_DIVIDER.CLK_DMIC_SRC REG0X03[12:10].
•Both digital MIC inputs can be used simultaneously. However, both digital MIC and analog MIC inputs
cannot.
3.3 Line Inputs
In addition to the MIC inputs, the right and left ADC channels can be setup to accept line inputs in the
following configurations:
1. One pair of single ended stereo AUX inputs: AUX_L/AUX_R
2. Two single ended MONO inputs: MONO+ and MONO-
3. One differential MONO input: MONO±
The single ended operation and pre-charge option described in the analog MIC input section are also
available for line inputs because they follow similar data paths to the MIC inputs. Exclusively AUX_R, the
line inputs are routed through a variable attenuation stage with a range from -46.5dB to 0dB dependent on
FEPGA_ATTENUATION.FEPGA_ATTNR REG0X7A[12:8]and
FEPGA_ATTENUATION.FEPGA_ATTNL REG0X7A[4:0]. By default, both channels are attenuated by
0dB.
Application Notes:
•Both Line and analog MIC inputs can be used simultaneously
•AUX shared with analog MIC inputs, its attenuation is -6dB or 0dB.
3.4 Programmable Gain Amplifier (PGA)
Each input channel (Left and Right) has a dedicated fully differential PGA amplifier used for signal
conditioning before it is fed into the ADC. Both PGAs can be individually enabled or disabled using
POWER_UP_CONTROL.PUPR REG0X7F[13]and POWER_UP_CONTROL.PUPLREG0X7F[12]and
are controlled using FEPGA.FEPGA_MODER REG0X77[7:4]and FEPGA.FEPGA_MODEL
REG0X77[3:0].
Application Notes:
•The PGA can accept either differential or single ended input configurations.
•The gain for the Right and Left PGA can be set using FEPGA_II.FEPGA_GAINR REG0X78[9:5]and
FEPGA_II.FEPGA_GAINL REG0X78[4:0], respectively.
•The PGA can be set into a Low or High power mode using BIAS_ADJ.BIASADJ REG0X66[1:0].
•Both MIC and Line inputs can be connected to the PGA simultaneously.
4ADC Digital Block
ADC Digital Path
Channel 0 and 1 Only
ƩΔ
ADC
DECM X2
Channel
DECM X2
Channel
DRC X4
Channel
(0-3)
DRC X4
Channel
(0-3)
High Pass
Filter X4
Channel
(0-3)
High Pass
Filter X4
Channel
(0-3)
Notch
Filter
Notch
Filter
5 Band
Equalizer
5 Band
Equalizer
Digital
Audio
Interface
Volume
Control
X4
Channel
(0-3)
Volume
Control
X4
Channel
(0-3)
Digital
MIC
Interface
HPF X4
Channel
(0-3)
HPF X4
Channel
(0-3)
DECM X2
Channel
DECM X2
Channel
AUXL-
DMIC1
AUXR+
DMIC2
DMIC4
DMIC3
Channel 2 and 3 Only
Figure 3: ADC Digital Path
The ADC digital block takes the output of the 24-bit Analog-to-Digital converter and preforms signal
processing aimed at producing a high quality audio sample stream to the audio path digital interface.The
figure above shows the various steps associated with the ADC digital path. This block can be enabled for
channels 0 through 3 by using ENA_CTRL.ADC_CH(3/2/1/0)_EN REG0X01[3:0].
Oversampling is used to improve noise and distortion performance; however this does not affect the final
audio sample rate. ADC_FILTER_CTRL.ADC_RATE REG0X24[1:0]can be used to set the ADC OSR
and ADC_FILTER_CTRL.SMPL_RATE REG0X24[7:5]should be set to the value closest to the actual
sample rate.

Apr 11, 2022 Page 20 of 96 Rev 2.1
The polarity of either ADC output signal can be changed independently on either ADC logic output as a
feature sometimes useful in management of the audio phase. This feature can help minimize any audio
processing that may be otherwise required as the data is passed to other stages in the system.
Application Notes:
•The definitions for channel 0 through 3 can be seen below in the table below. Also note that for channel0/1,
each channel can only be used in either Analog mode or Digital mode, not both at the same time.
•The ADC coding scheme is in twos complement format.
•The full-scale input level is proportional to VDDA. For example, with a 1.8V supply voltage, the full-scale
level is 1.0VRMS.
•Four PDM microphones can be enabled using ENA_CTRL.ADC_CH(3/2/1/0)_DMIC_MODE
REG0X01[9:6]for ADC channel 3 through 0, respectively.
•The polarity of the four digital microphones can be set using
ENA_CTRL.DMIC_LCH_EDGE_ADC_CH(23/01)REG0X01[15:14].This can help minimize any
unnecessary audio processing as data is passed to other stages in the system.
•ADC path connects with DAC path by setting PORT0_I2S_PCM_CTRL_1.ADDAP REG0X1C[7]=1
•ADCL out and ADCR out has one sample time difference
CH
Analog Inputs
Digital Inputs
0
MIC1±/AUX_L/MONO+
Digital MIC 0 (DMCLK1/DMDATA1)
1
MIC2±/AUX_R/MONO-/HSMIC±
Digital MIC 1 (DMCLK1/DMDATA1)
2
Digital MIC 2 (DMCLK2/DMDATA2)
3
Digital MIC 3 (DMCLK2/DMDATA2)
Table 2: ADC Channel Input Definitions
4.1 ADC Dynamic Range Compressor (DRC)
The NAU88L24 includes DRCs for the four channels in the ADC. However, to control the DRC, the four
channels have been paired and denoted as CH01 or CH23 in the register map for channel 0/1 and channel
2/3, respectively. Similarly, the DAC left and right audio channel controls have been paired.
The DRC function consists of level estimation and static curve control.
4.1.1 Level Estimation
The NAU88L24 uses Peak level estimation that depends on the attack and decay time setting. The attack
times settings are grouped to channel 0/1 and 2/3 and can be set by using
DRC_ATKDCY_ADC_CH01.DRC_PK_COEF1_ADC_CH01 REG0X3B[15:12]and
DRC_ATKDCY_ADC_CH23.DRC_PK_COEF1_ADC_CH23 REG0X3F[15:12], respectively. The decay
times are similarly set using DRC_ATKDCY_ADC_CH01.DRC_PK_COEF2_ADC_CH01
REG0X3B[11:8]and DRC_ATKDCY_ADC_CH23.DRC_PK_COEF2_ADC_CH23 REG0X3F[11:8],
respectively.
BITS
DRC_PK_COEF1_ADC_CH##
DRC_PK_COEF2_ADC_CH##
0000
TS
63*TS
0001
3*Ts
127*Ts
0010
7*Ts
255*Ts
0011
15*Ts
511*Ts
0100
31*Ts
1023*Ts
0101
63*Ts
2047*Ts
0110
127*Ts
4095*Ts
0111
255*Ts
8191*Ts
Table 3: ADC Level Estimation Attack and Decay Time Register Settings
Application Notes:
•Time constant Ts shown in the register map is the sampling time given by 1/(Sampling Frequency)
4.1.2 Static Curve
The DRC static curve supports five programmable sections and can be enabled by using
DRC_KNEE_IP12_ADC_CH01.DRC_ENA_ADC_CH01 REG0X38[15]and
DRC_KNEE_IP12_ADC_CH23.DRC_ENA_ADC_CH23 REG0X3C[15]for channel 0/1 and 2/3,
respectively. The figure below shows the five programmable sections.