Apr 11, 2022 Page 4 of 96 Rev 2.1
5.6.1 µ-law...................................................................................................................................................30
5.6.2 A-law...................................................................................................................................................30
5.7 Additional DAC Application Notes..............................................................................................................30
6CLOCKING AND SAMPLE RATES ..................................................................................................30
6.1 Frequency Locked Loop (FLL)...................................................................................................................32
7CONTROL INTERFACES.................................................................................................................34
7.1 2-Wire-Serial Control Mode (I2C Style Interface) .......................................................................................35
7.2 2-Wire Protocol Convention.......................................................................................................................35
7.3 2-Wire Write Operation..............................................................................................................................35
7.4 2-Wire Read Operation..............................................................................................................................36
7.5Digital Serial Interface Timing....................................................................................................................36
7.6 Software Reset ..........................................................................................................................................37
8DIGITAL AUDIO INTERFACES ........................................................................................................37
8.1 Right-Justified Audio Data..........................................................................................................................38
8.2 Left-Justified Audio Data............................................................................................................................38
8.3 I2S Audio Data...........................................................................................................................................38
8.4 PCM A Audio Data.....................................................................................................................................39
8.5 PCM B Audio Data.....................................................................................................................................39
8.6 PCM Time Slot Audio Data........................................................................................................................39
8.7 TDM I2S Audio Data..................................................................................................................................40
8.8 TDM PCM A Audio Data............................................................................................................................40
8.9 TDM PCM B Audio Data............................................................................................................................41
8.10 TDM PCM Offset Audio Data.....................................................................................................................41
9OUTPUTS..........................................................................................................................................43
9.1 Stereo Class D Speaker Outputs...............................................................................................................43
9.1.1 Differential Mixer.................................................................................................................................43
9.1.2 Device Protection................................................................................................................................44
9.1.3 Class D without filter...........................................................................................................................44
9.1.4 Class D Filters ....................................................................................................................................45
9.1.5 NAU88L24 EMI performance..............................................................................................................46
9.2 Class G Headphone Driver and Charge Pump..........................................................................................46
10 HEADSET DETECTION....................................................................................................................47
10.1 Jack Detection ...........................................................................................................................................47
10.2 Microphone Detection................................................................................................................................48
10.3 Key/Button Detection.................................................................................................................................48
10.3.1 SAR ADC............................................................................................................................................51
10.4 Jack Interrupt Sequence............................................................................................................................52
10.4.1 Jack Insert ..........................................................................................................................................52
10.4.2 Jack Eject ...........................................................................................................................................52
10.4.3 Short Key Press..................................................................................................................................52
10.4.4 Key Release .......................................................................................................................................52
11 BASIC REGISTER SEQUENCES.....................................................................................................53
11.1 To enable VREF and General Bias............................................................................................................53
11.2 Enable/Disable Input PGA.........................................................................................................................53
