Nuvoton N9H30 Series User manual

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Application Note for 32-bit NuMicro®Family
Document Information
Abstract
The N9H30 hardware development guide is intended for hardware
system designers who require a hardware implementation overview
for N9H30 based system.
The features include a basic 12 MHz external crystal for system
operation, and a crystal of 32.768 kHz for RTC circuitry, USB 2.0
Host reference design, USB 2.0 device reference design, 12-bit
SARADC reference design, I2C, I2S for audio codec reference
design, Smart Card Interface, LCD interface and UART (universal
asynchronous receiver/transmitter) connections.
The N9H30 series has rich memory interfaces, SD, eMMC, NAND
Flash, SPI Flash and EBI interface for system booting, data storage
and files accesses.
This design guide can be apply to all N9H30 series packages.
Apply to
N9H30 Series.
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of NuMicro microcontroller and microprocessor based
system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com
N9H30 Series Hardware Development Guide

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Table of Contents
1POWER SUPPLIES.......................................................................................................4
1.1 Power Supply Scheme................................................................................................................4
1.2 RESET............................................................................................................................................6
1.3 Power on setting........................................................................................................................10
1.4 Power Operating Modes ...........................................................................................................12
2CLOCK CIRCUITRY ...................................................................................................13
2.1 External Crystal Sources..........................................................................................................13
2.2 PCB Design Guide.....................................................................................................................14
3SAR_ADC.....................................................................................................................15
3.1 Analog Signals...........................................................................................................................15
3.2 Features.......................................................................................................................................15
3.3 Block Diagram............................................................................................................................15
3.4 Input Signal Impedance (Excluding ADC 0)..........................................................................17
3.4.1High Speed Mode (1 MSPS)........................................................................................................ 18
3.4.2Low Speed Mode (200 KSPS)..................................................................................................... 18
3.4.3Application Circuit for Battery Voltage Detection ...................................................................... 18
3.4.4Key Pad Scan................................................................................................................................. 19
3.4.5Application Circuit for Key Pad Scan .......................................................................................... 19
4RTC................................................................................................................................21
4.1 RTC Power Backup & Power Saving......................................................................................21
5USB BUS.......................................................................................................................22
5.1 USB Device .................................................................................................................................22
5.1.1High Speed USB Termination...................................................................................................... 22
5.1.2REXT and USB Power.................................................................................................................. 23
5.2 USB PCB Layout Guideline......................................................................................................23
5.2.2Through Hole Consideration for D+ and D- ............................................................................... 25
5.2.3Signal Trace for D+ and D-........................................................................................................... 26
5.2.4High Speed USB Trace Spacing ................................................................................................. 26
5.2.5High Speed USB Trace Length Matching.................................................................................. 27
5.2.6High Speed USB Trace Length Guidelines................................................................................ 27
5.2.7Layout Stacking.............................................................................................................................. 27
5.2.8EMI/ESD Considerations.............................................................................................................. 28
5.2.9EMI - Common Mode Chokes...................................................................................................... 28
5.2.10 ESD ........................................................................................................................................ 31

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6REFERENCE DESIGN ...............................................................................................32

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1 Power Supplies
This chapter describes design considerations related to the N9H30 series power supply scheme
and power operating modes.
Power Supply Scheme
The N9H30 series should be supplied by a stabilized power; VDD33, VDD12, MVDD, AVDD,
RTCVDD, USB0_VDD, USB1_VDD, USBPLL0, USBPLL1 and PLLVDD
Some points need to take care when using these power rails:
VDD33 pin must be powered by 3.0V~3.6V and with external decoupling capacitors.
(place one 0.1uF capacitor for each VDD33 pin is recommended)
VDD12 pin must be powered by 1.2V5and with external decoupling capacitors. (place
one 0.1uF and one buck 10uF capacitor for each VDD12 pin is recommended)
MVDD pin must be powered by 1.8V0.1V and with external decoupling capacitors. (place
one 0.1uF and one buck 10uF capacitor for each MVDD pin is recommended)
AVDD pin must be powered by 3.0V~3.6V and with external decoupling capacitors. (place
one 0.1uF capacitor and a buck 10uF capacitor for each AVDD pin is recommended)
RTCVDD is an independent power domain, it can be powered by 3.6V~2.0V and with a
0.1uF decoupling capacitor.
PLLVDD is a phase lock loop power pin which should be supplied by 1.2V5and with
external decoupling capacitors. (place one 0.1uF capacitor and a buck 10uF capacitor is
recommended)
USB0VDD is USB port 0 PHY power pin which should be supplied by 3.3V10and with
external decoupling capacitors. (place one 0.1uF capacitor and one buck 10uF capacitor is
recommended)
USBPLL0 is USB port 0 core power pin which should be supplied by 1.2V5and with
external decoupling capacitor. (place one 0.1uF capacitor and one buck 10uF capacitor is
recommended)
USB1VDD is USB port 1 PHY power pin which should be supplied by 3.3V10and with
external decoupling capacitors. (place one 0.1uF capacitor and one buck 10uF capacitor is
recommended)
USBPLL1 is USB port 1 core power pin which should be supplied by 1.2V5and with
external decoupling capacitor (place one 0.1uF capacitor and one buck 10uF capacitor is
recommended).

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The following is power supply scheme of N9H30 series.
Figure 1.1-1 Power Supply Scheme
10uF
10uF
4.7uF
0.1uF
0.1uF
2.2uF
10uF
0.1uF
0.1uF
AVSS
VD33
VD12
MVDD
RTCVDD
AVDD33
PLL_VDD12
USBPLL0
USBPLL1
RTCVDD
AVDD
MVDD
VDD12
VDD33
USB1_VDD
USB0_VDD
10uF
10uF
0.1uF
0.1uF
10uF
PLLVS
PLLVS
USBPLLVS
10uF
10uF
0.1uF
PLLVD12
USBPLL0VD12
USB0_VDD
USB1_VDD
USBPLL1VD12
0.1uF
0.1uF
AVSS
USBPLLVS
USBPLLVS
USBPLLVS
PLLVSS
VSS
PLLVS
AVSS
AVSS
USBPLLVSS
USBPLLVS

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RESET
Hardware Reset Conditions:
Power-on Reset (POR)
Low level on the nRESET Pin (nRST)
Watch-dog time-out reset (WDT)
Low voltage reset (LVR)
The internal Power on Reset (POR) circuit without any external resistor or capacitor supports a
power on ratio within 1V/0.1us~1V/100ms. The reset signal may not be available if the power
rises too fast or too slow and the ratio goes beyond the range 1V/01us~1V/100ms.
CHARACTERISTICS
SYMBOL
MIN
TYP
MAX
UNIT
CONDITION
Power Supply
VDD
2
3.3
3.6
V
Ramp ratio 1.0V/100ms
Reset Trigger Level
Vtr
1.05
1.57
1.98
V
Ramp ratio 1.0V/0.11us
Vtf
1
1.64
1.98
V
Reset Delay Time
Tdelay
85
150
7500
us
Table 1.2-1 Internal Power-On Characteristics
Figure 1.2-1 POR Waveform

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Table 1.2-2 Power-On Reset at POR33
Figure 1.2-2 Power-On Reset at POR33
Table 1.2-3 Power-On Reset at POR12
POR_OUTB
AVDD
Vrr
Tr
TPOR
POR_EN = Low POR_EN = High
Symbol
Parameter
Min.
Typ.
Max
.
Unit
Test Condition
AVDD
3.3V power
3.3
V
-
Tr
Power Rising
Rate Voltage
1V/1u
S
-
-
V
AVDD rising from 0V
to 3.3V
Vrr
Active level
1.65
1.82
2.0
V
Power slew rate is
3.3V/20mS.
Tpor
POR output low
duration
5.2
uS
-
Symbol
Parameter
Min.
Typ.
Max.
Unit
Test Condition
CoreVDD
1.2V power
1.2
V
-
Tr
Power Rising Rate
Voltage
1V/1u
S
-
-
V
-
Vrr
Active level
0.63
0.76
0.86
V
Power slew rate is
1.2V/20mS.
Tpor
POR output low
duration
4.25
uS
-

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POR12
_OUTB
CoreVDD
Vrr
Tr
TPOR
POR_EN = Low POR_EN = High
Table 1.2-4 Power-On Reset at POR12
The purpose of Watchdog Timer (WDT) is to perform a system reset when system runs into an
unknown state. This prevents system from hanging for an infinite period of time. Besides, this
Watchdog Timer supports the function to wake-up system from Idle/Power-down mode.
18-bit free running up counter for WDT time-out interval
Selectable time-out interval (24~ 218) and the time-out interval is 0.48828125 ms ~ 8 s if
WDT_CLK = 32.768 kHz
System kept in reset state for a period of (1 / WDT_CLK) * 63
Supports selectable WDT reset delay period, including 1024+2、128+2、16+2 or 1+2
WDT_CLK reset delay period
Supports WDT time-out wake-up function only if WDT clock source is selected as 32 kHz
low-speed oscillator.
Supports to force WDT enabled after chip powered on or reset by setting WDTON in
PWRON register

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The Low Voltage Reset (LVR) and the Low Voltage Detector (LVD) both will generate logic high
or logic low output for digital core once the monitored power, VDD, surpasses or falls below their
detection level. The block diagram as Figure
CHARATERISTICS
SYMBOL
MIN
TYP
MAX
UNIT
CONDITION
Analog Power
AVDD
2.97
3.3
3.63
V
Core Power
VDD12
1.14
1.2
1.26
V
LVD Detect Levels
VDET_LVD1
2.34
2.6
2.86
V
LVD_SEL=0, VDD rises
VDET_LVD2
2.295
2.55
2.805
V
LVD_SEL=0, VDD falls
VDET_LVD3
2.52
2.8
3.08
V
LVD_SEL=1, VDD rises
VDET_LVD4
2.475
2.75
3.025
V
LVD_SEL=1, VDD falls
LVR Detect Levels
VDET_LVR1
2.16
2.4
2.64
V
VDD rises
VDET_LVR2
2.115
2.35
2.585
V
VDD falls
LVR Output Delay
Tdelay
100
320
600
uS
VDD rises @ 3V/10us
Table 1.2-5 Internal LVR/LVD Characteristics
Figure 1.2-3 4 LVR and LVD Timing Waveform
Note:
1. When testing the features of LVD/LVR detect levels, the power-up or power-down speed of VDD should be slower
than 500mS/2V.
2. When testing the output delay of LVR, the power-up speed of VDD should be faster than 10uS/3V.

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Power on setting
The power-on setting is used to configure the chip to enter the specified state when the chip is
powered up or reset. Since each pin of power on setting has an internal pulled-up resistor when
in reset period. If the application needs to set the configuration to “0”, the proper pull-down must
be added resisters for corresponding configuration pins.
The entire configuration table is listed below:
Note:
a. 1 = open, 0 = pulled down.
b. PA [9:0] = CFG [9:0]
PA.1
PA.0
Booting From
0
0
USB.
0
1
eMMC Flash.
1
0
NAND Flash.
1
1
SPI Flash.
Table 1.3-1 System Power-On Setting Guide for Booting Mode
PA2
System Clock Source
0
12 MHz crystal.
1
PLL output.
Table 1.3-2 System Power-On Setting Guide for System Clock Source
PA3
Watch Dog Setting
0
Disable after power on.
1
Enable after power on.
Table 1.3-2 System Power-On Setting Guide for Booting Mode
PA4
Setting PJ[4:0]
0
As GPIO pin.
1
As JTAG interface.
Table 1.3-3 System Power-On Setting Guide for booting mode.
PA5
UART Debug Message

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0
Output turn on.
1
Output turn off.
Table 1.3-4 System Power-On Setting Guide for Booting Mode
PA7
PA6
NAND Flash Page Size
0
0
2K page.
0
1
4K page.
1
0
8K page.
1
1
None.
Table 1.3-5 System Power-On Setting Guide for NAND Flash Page Size
PA9
PA8
NAND Flash ECC Type
0
0
BCH 12T.
0
1
BCH 15T.
1
0
BCH 24T.
1
1
None.
Table 1.3-6 System Power-On Setting Guide for NAND Flash ECC Type.

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Power Operating Modes
The N9H30 series has four kinds of operating modes:
Normal mode: CPU runs normally and all clocks are ON.
Idle mode: CPU entering Sleep mode while CPU clock stops and other clocks are ON.
Power-down mode: All clocks stop, except LXT and SRAM retention.
Deep Power-down mode:
As the control flow chart below, under Normal mode the CPU and the peripheral device works
normally; under Idle mode the CPU stops to work and the peripheral device works normally; under
Power-down mode both the CPU and the peripheral device stop, the high frequency crystal and
oscillator input will be disabled to reduce power consumption. While low frequency crystal and
oscillator can be enabled by program control to support the peripheral functions (e.g. RTC,
Watchdog Timer) to work in Power-down mode, which is the best power saving mode.
Figure 1.4-1 Power Operating Modes

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2 Clock Circuitry
This chapter describes that design considerations for N9H30 series CLK oscillation installation.
External Crystal Sources
There are two external clock sources for the N9H30 series:
Main CLK source with 12 MHz for PLL controller
32.768 kHz CLK source for RTC counter
The oscillators of 12 MHZ CLK and RTC_32K are connected with a quartz X’tal and two capacitors
externally.
Xin Xout Chip internal
Board
Cin Cout
RfClock
out
Figure 2.1-1 Crystal Oscillator Circuit
Cin, Cout: External capacitors
Rf: Built-in feedback resistor
X’tal: External X’tal
The external crystal oscillator and two capacitors are connected to the pad “Xin” and pad “Xout”.
The capacitance value of the two capacitors may be changed for differential crystal oscillator from
different vender.
Main Clock: 12 MHz Crystal
For Cin and Cout is recommended to use high-quality ceramic capacitors in the 5 pF-to-20 pF
range, designed for high-frequency applications and selected to meet the requirement of crystal.
PCB and N9H30 package capacitances should be calculation size to Cin/Cout. Cin and Cout
usually have same value.
The crystal manufacturer typically specifies a load capacitance combination of Cin/Cout.
For PCB layout, 12 MHZ crystal, Cin/Cout and related components all must be placed to be close
to N9H30 ASAP to get that optimum performance and stability for system running. (Typically,
package capacitance is 2pF around)

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Board Parameter
Symbol
Value
XIN, XOUT Capacitance
Cin, Cout
5~20pF
Table 2.1-1 12MHz Cin, Cout & Rf Recommend Value
RTC Clock: 32.768 kHz Crystal
For Cin and Cout are recommended to use high-quality ceramic capacitors in the 15pf-to-33pf
range, designed for RTC applications and selected to meet the requirements of the crystal.
Cin and Cout, usually have same value. The crystal manufacturer typically specifies a load
capacitance that combination of Cin and Cout.
For getting accuracy 32.768 kHz, you can use timer counter machine to calibrate Cin and Cout
value or alternative use software skill that adjust N9H30 RTC frequency compensation register
to approach.
For PCB layout that XTAL, Cin/Cout and related components should be placed to be close to
N9H30 ASAP to get the optimum accuracy and stability.
Board Parameter
Symbol
Value
RTC_IN, RTC_OUT Capacitance
Cin, Cout
15~33pf
Table 2.1-2 32.768 kHz Cin, Cout & Rf Recommend Value
PCB Design Guide
Applications requiring low power oscillators on the N9H30 series must take PCB layout into
consideration. The oscillators on the N9H30 series consume very little current, and it sometimes
makes the oscillator circuit sensitive to neighboring circuits. The following lists some PCB design
guidelines:
Keep PCB trace as short as possible because the longer trace leads will increase parasitic
capacitance and might induce coupling issue.
Reduce power supply noise; connect a de-coupling capacitor between VDD and VSS will
suppress from system power traces.
Place oscillator module correctly to prevent noise source from influencing of oscillator
block and Xin/ Xout pins.
The load capacitors Cin/ Cout should be placed close to the crystal pins, and the trace
length should be as short as possible.

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3 SAR_ADC
This chapter describes design considerations related to the N9H30 ADC.
Analog Signals
The analog-to-digital converter contains one 12-bit Successive Approximation Register analog-
to-digital converter (SAR A/D converter) with eight input channels. The A/D converter supports
two operation modes: 4-wire or 5-wire mode.The ADC is especiallysuitable to act as touch screen
controller. Battery voltage detection could beeasily accomplished by the SAR ADC. It has keypad
interrupt signal generator.
Features
Resolution: 12-bit resolution.
DNL: +/-1.5 LSB, INL: +/-3 LSB.
Dual Data Rates: 1MSPS/200KSPS.
Analog Input Range: VREF to AGND, could be rail-to-rail.
Analog Supply: 2.97-3.63V.
Digital Supply: 1.2V.
8 Single-Ended Analog inputs.
Compatible with 4-wire or 5-wire Touch Screen Interface.
Touch Pressure Measurement for 4-wire touch screen application.
Direct Battery Measurement.
Keypad Interrupt Generator.
Auto Power Down.
Low Power Consumption: 4850uW(@1MSPS) / 2170uW(@200KSPS), < 1uA
Block Diagram
The SAR-ADC supports 8 input channels. The channel selection is controlled by the IN_SEL[2:0].
ADC.0 can support battery voltage detection. Therefore, it includes the block “Resistor Divider &
Switch”. ADC.1 is for high speed sampling rate (1MSPS). ADC2 are for low speed sampling rate
(200KSPS), and ADC.0 needs lengthy sampling time because it entrains 10 kΩ resistances.
ADC.2 is also for keypad application. Remaining channel of ADC[7:3] is for touch panel
application.
IN_SEL[2:0]
ADC Input Channel
Description
000 (ADC0)
VBT
Intended for battery voltage detection. It includes
an inherent resistor divider and a switch.

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001 (ADC1)
VHS
ADC high speed input port.
VHS = 1, it supports 1MS/S.
VHS = 0, it supports 200KS/S.
010 (ADC2)
A_2
A low speed input which could support 200KS/S;
Keypad signal input pin.
011 (ADC3)
VSENSE
The input port is intended for 5-wire touch screen
detection.
100 (ADC4)
YM
ADC analog input.
If used in touch screen, it should connect to the
negative end of Y axis.
If used in 5-wire touch screen, it could connect to
lower-left electrode.
101 (ADC5)
YP
ADC analog input.
If used in touch screen, it should connect to the
positive end of Y axis.
If used in 5-wire touch screen, it could connect to
upper-right electrode.
110 (ADC6)
XM
ADC analog input.
If used in touch screen, it should connect to the
negative end of X axis.
If used in 5-wire touch screen, it could connect to
lower-right electrode.
111 (ADC7)
XP
ADC analog input.
If used in 4-wire touch screen, it should connect
to the positive end of X axis.
If used in 5-wire touch screen, it could connect to
upper-left electrode.
Table 3.3-1 ADC Input Channel Selection Table

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Resistor divider
& switch
8 Channel
MUX
Keypad
VREF AVDD
Internal
SAR ADC
12
AVDD
ADC0
ADC1
ADC2
ADC3
ADC5
ADC7
ADC4
ADC6
Figure 3.3-1 ADC Functional Block Diagram
Input Signal Impedance (Excluding ADC 0)
The input current on analog input pins depends on analog input voltage and sampling rate. In the
sampling mode, the input current charges the internal sampling capacitor. After the capacitor is
fully charged, the current will be off. The internal sampling capacitor must be charged to 12-bit
settling level at sampling time, under afore mentioned condition.
The signal source impedance connected to analog input needs to satisfy thefollowing expression:
Csamp
Rref
Ron
Rsrc
N9H30 Internal
Outside Source
ADCx
Figure 3.5-1 Simplified Sampling Diagram
0.69*(12+1)*Csamp*1.1*(Rsrc+Ron+Rref) < (1/Fclk)*3
Rref: The equivalent resistance value from the ADC input end.
Csamp: On chip sample and hold capacitance.
Ron: On chip 8 channels input resistance.
Rsrc: Signal source resistance.
Vsrc: Signal source voltage level.
Fclk: ADC clock (Fclk = Sample rate * 16)

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3.4.1 High Speed Mode (1 MSPS)
Csamp = 25.6pF
Fclk = 16 MHz
Rref: 300
Ron: 20
0.69*(12+1)*Csamp*1.1*(Rsrc+Ron+Rref) < (1/Fclk)*3
→ Rsrc < 422
3.4.2 Low Speed Mode (200 KSPS)
Csamp = 25.6pF
Fclk = 3.2 MHz
Rref: 300
Ron: 20
0.69*(12+1)*Csamp*1.1*(Rsrc+Ron+Rref) < (1/Fclk)*3
→ Rsrc < 2111
3.4.3 Application Circuit for Battery Voltage Detection
The analog input is from VBAT and the external discrete components prevent battery leakage from
VBAT when system is under power off states.
VBAT
7.5KR
2.5KR
0.125V to 1.375V
Core ADC
VDD33
100K
5.1K±1%
5.5V ~ 1V
Battery
Figure 3.5.3-1 Battery Voltage Detection Application Circuit
Note: This IP entails 10K resistance, so lengthy sampling time is needed.

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3.4.4 Key Pad Scan
This signal is designed for Key Pad Scan from A_2.
Figure 3.5.4-1 Key Pads Detection Diagram
Note: If a user applies the keypad using this structure and meanwhile, he/she needs the interrupt
generator, please make sure Res1≦20Kand Res2＜5.6*Res1. Moreover, a 0.01uF cap is
recommended at A_2 on board.
If a user does not need the interrupt generator, please ignore the requirement for Res1 and
Res2.
3.4.5 Application Circuit for Key Pad Scan
Figure 3.4-1 Key Pad Scan Application Circuit
A_2 = 0.825V when K1 + K2 switch is pressed.
A_2 = 0.99V when K1 + K3 switch is pressed.
A_2 = 1.0607V when K1 + K4 switch is pressed.
A_2 = 1.1V when K1 +K5 switch is pressed.
A_2 = 1.125V when K1 + S6 switch is pressed.

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A_2 = 1.2375V when K1 switch is pressed.
A_2 = 1.4143V when K2 switch is pressed.
A_2 = 1.98V when K3 switch is pressed.
A_2 = 2.2846V when K4 switch is pressed.
A_2 = 2.475V when K5 switch is pressed.
A_2 = 2.6053V when K6 switch is pressed.