Nuvoton NuMicro MA35D1 BSP User manual

MA35D1 BSP
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MA35D1 BSP USER MANUAL
NuMicro®Family
Arm®Cortex®-A35-based Microprocessor
MA35D1 BSP
User Manual
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of NuMicro® microcontroller and
microprocessor based system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com

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Table of Contents
1OVERVIEW......................................................................................................3
2BSP FEATURES..............................................................................................4
2.1 Supported Platforms ..................................................................................................... 4
2.2 BSP Contents................................................................................................................. 4
2.3 Repositories ................................................................................................................... 5
3DEVELOPMENT BOARD SETUP...................................................................6
3.1 Power on Setting ........................................................................................................... 6
3.2 Hardware Connection ................................................................................................... 7
3.2.1 COM Port...........................................................................................................................7
3.2.2 ICE interface ...................................................................................................................10
4DEVELOPMENT ENVIRONMENT SETUP....................................................12
4.1 Linux Development Environment .............................................................................. 12
4.1.1 Install Required Packages for Build Host ...................................................................12
4.1.2 Install Linaro GCC compiler ..........................................................................................12
4.2 Coretx-M4 firmware Development Environment..................................................... 13
4.3 BSP Installation............................................................................................................ 13
5MA35D1 BOOT SOURCE..............................................................................14
5.1 Boot from USB............................................................................................................. 14
5.2 Boot from NAND Flash ............................................................................................... 15
5.3 Boot from SPI NAND Flash........................................................................................ 17
5.4 Boot from SPI NOR Flash .......................................................................................... 18
5.5 Boot from eMMC and SD Card ................................................................................. 19
5.5.1 Backup Boot from SD0 Interface..................................................................................20
6BOOTING PREBUILD IMAGES ....................................................................21
6.1 SOM Board................................................................................................................... 21
6.1.1 Boot from SD Card Flash ..............................................................................................21
6.1.2 Boot from SPI NAND Flash...........................................................................................21
6.1.3 Boot from NAND Flash ..................................................................................................22
6.2 IoT Demo Board .......................................................................................................... 22
6.2.1 Boot from SPI NAND Flash...........................................................................................22
6.2.2 Boot from SD Card Flash ..............................................................................................22
6.2.3 Boot from NAND Flash ..................................................................................................23
7REVISION HISTORY .....................................................................................24

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1 OVERVIEW
The MA35D1 series microprocessor is based on a poweful Armv8-A architecture dual-core ARM
Cortex-A35 with TrustZone®, which features 32 KB I-cache, 32 KB D-cache, and 512 KB L2 Cache.
The internal 64/32-bit CPU core operates up to 1 GHz supporting secure boot.
The MA35D1 also embeds a ARM Cortex-M4 processor core running at 180 MHz with 16 KB / 16 KB I
and D Cache for expansible system DRAM access, Floating Point Unit, Memory Protect Unit and a
dedicated 128 KB SRAM for code excuting. Cortex-M4 rela time processpr (RTP) provides a Real-
Time process ability in whole system design and communicates with Cortex-A35 by a mailbox
architecture.
This document introduces the MA35D1 board supporting package (BSP). Chapter 2 describes the
features of MA35D1 BSP. Chapter 3 introduces the setting of DEV board and chapter 4 introduces the
develop environment setup for MA35D1 BSP. Chapter 5 describes different boot source of MA35D1.
Chapter 6 lists the steps to bring up MA35D1 system with pre-built images provided in the BSP.
There are other reference documents describing each BSP components in detail. Please refer to the
following documents for the detailed information of each topic.
UM_EN_MA35D1_Yocto
UM_EN_MA35D1_Buildroot
UM_EN_MA35D1_TF-A
UM_EN_MA35D1_OP-TEE
UM_EN_MA35D1_U-boot
UM_EN_MA35D1_Linux_BSP
UM_EN_MA35D1_NuWriter
UM_EN_MA35D1_RTP

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2 BSP FEATURES
This BSP supports Linux operating system for MA35D1. The peripheral drivers are also included in the
BSP allowing applications to access them. The image reside at EL3 as secure monitor is BL31 from
Trusted Firmware-A (TF-A), which is included. And this BSP includes OP-TEE to provide the secure
service provided in secure EL1. Also U-Boot is provided as a loader to load the Linux kernel.
This BSP also provided applications components allowing users to build up a system easily. For
example, this BSP provides Qt for HMI system development, provides lighttpd for web server
applications. And GStreamer is included for H.264 and JPEG playback.
A bare-metal CMSIS based package is provided for develop the firmware for Cortec-M4 in MA35D1.
The structure of this package is aligned with other CMSIS BSPs for NuMicro MCUs allowing existed
users to migrate to MA35D1 as smooth as possible.
To allow users to managed all packages mentioned above, a Yocto project or a buildroot project is
used for create the Linux distributions.
There’s also a NuWriter tool support storage device programming. A pintool supports pin configuration
for MA35D1, and NuEclipse, an IDE for develop Cortex-M4 real time processor firmware.
2.1 Supported Platforms
This BSP supports following platform. Users could base on the platforms to develop their own system:
MA35D1 HMI Board
MA35D1 IoT Board
2.2 BSP Contents
The following lists the components of this BSP and their description.
Component
Description
Yocto
Version 3.1.3 (Dunfell). A Linux Foundation collaborative open source project to
create the Linux distributions.
Buildroot
A tool that simplifies and automates the process of building a complete Linux
system for an embedded system, using cross-compilation.
Linux
Version 5.4. An open source operating system based on GPLv2 license.
U-Boot
Version 2020.07. An open source bootloader based on GPLv2+ license
OP-TEE
Version 3.9.0. An open source trusted execution environment.
TF-A
Version 2.3. A BSD-3-Clause license reference implementation of secure world
software.
M4 BSP
CMSIS library 4.5.0 and standard driver for RTP baremetal/FreeRTOS firmware
development.
NuWriter
A GUI and command line tool supports firmware update and OTP programming

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for MA35D1.
Pin Tool
A pin configuration tool that can generate dts file for MA35D1.
NuEclipse
Includes a series of Eclipse plug-ins and tools. The plug-ins allow the user to
create, build, and debug ARM-based projects within the Eclipse framework
Table 2-1 BSP Content List
2.3 Repositories
The following lists the repositories holds the MA35D1BSP source code. Users can use git command to
clone the source to their local directory.
Component
URL
Yocto
https://github.com/OpenNuvoton/MA35D1_Yocto-v3.1.3
Buildroot
https://github.com/OpenNuvoton/MA35D1_Buildroot.git
Linux
https://github.com/OpenNuvoton/MA35D1_linux-5.10.y.git
U-Boot
https://github.com/OpenNuvoton/MA35D1_u-boot-v2020.07.git
OP-TEE
https://github.com/OpenNuvoton/MA35D1_optee_os-v3.9.0.git
TF-A
https://github.com/OpenNuvoton/MA35D1_arm-trusted-firmware-v2.3.git
NuWriter
https://github.com/OpenNuvoton/MA35D1_NuWriter.git
M4 BSP
https://github.com/OpenNuvoton/MA35D1_RTP_BSP.git
Table 2-2 Repository Link

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3 DEVELOPMENT BOARD SETUP
3.1 Power on Setting
There are several boot options can be decided by power on setting of MA35D1. For example, the boot
source, ECC bit to use, SD interface selection, etc. Table 3-1 lists the power on setting for MA35D1.
The power on setting should be set according to the boot scenario desired before reset or power on
the system.
Pin
Description
PG[0]
Secure Boot Disable Bit
0 = Secure Boot Enabled.
1 = Secure Boot Disabled.
PG[1]
Boot Source Interface IO Voltage
0 = Boot source interface IO voltage is 3.3V.
1 = Boot source interface IO voltage is 1.8V.
PG[3:2]
Boot Source Selection
00 = Boot from SPI Flash.
01 = Boot from SD/eMMC.
10 = Boot from NAND Flash.
11 = Boot from USB.
PG[5:4]
If BTSRCSEL = 10, the Boot from NAND Flash. NAND Flash Page Size Selection
00 = Ignore.
01 = NAND Flash page size is 2 KB.
10 = NAND Flash page size is 4 KB.
11 = NAND Flash page size is 8 KB.
If BTSRCSEL = 11, the Boot from USB
00 = USBD booting.
01 = USBH port0 boot.
10 = USBD booting.
11 = USBH port1 boot.
PG[7:6]
Miscellaneous Configuration
If BTSRCSEL = 01, Boot from SD/eMMC.
00 = SD0/eMMC0 4-bit mode booting.
01 = SD1/eMMC1 4-bit mode booting.
10 = eMMC0 8-bit mode booting.
11 = eMMC1 8-bit mode booting.
If BTSRCSEL = 10, the Boot from NAND Flash.
00 = Ignore.
01 = ECC is BCH T12.
10 = ECC is BCH T24.
11 = No ECC.
If BTSRCSEL = 00, the Boot from SPI Flash.
00 = SPI-NAND Flash with 1-bit mode booting.
10 = SPI-NOR Flash with 1-bit mode booting.
If BTSRCSEL = 11, the Boot from USB.
MISCCFG[0]:
0 = over-current low active detect.
1 = over-current high active detect.
Table 3-1 Power on Setting

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3.2 Hardware Connection
All boards manufactured by Nuvoton come alone with two USB device ports. One for download
firmware and the other is VCOM for debugging. NuWriter tool comes alone with GUI and command
line interface provided for firmware download. Please refer to MA35D1 NuWriter User Manual for the
usage of NuWriter tool.
3.2.1 COM Port
The VCOM baud rate and line configuration is fixed at 115200 8-n-1. There are several free terminal
tools that can be used to communicate with MA35D1. Below use Tera Term as an example to
configure the VCOM port. First launch Tera Term and click “Setup” as shown in Figure 3-1, and then
click “Serial port…” in pull-down menu as shown in Figure 3-2. The last step is to select the correct
port number and line configuration. The port number is COM3 in Figure 3-3 but may change from PC
to PC. The reset of the setting should keep the same as the example.
Figure 3-1 Launch Tera Term

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Figure 3-2 Setup Serial Port
Figure 3-3 Select Port Number
For engineers to develop on a native Linux machine where, Putty could be an alternative for Tera
Term which does not support Linux platform. To use putty, first launch it and select the connection
interface. The example in Figure 3-4 uses /dev/ttyUSB0, this may vary on different computer. Then
configure the UART interface to 115200-8n1 as shown in Figure 3-5.

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Figure 3-4 Select Connection

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Figure 3-5 Configure Serial Interface
3.2.2 ICE interface
Some of the platforms provide JTAG interface which could be used to debug Cortex-A35 or Cortex-
M4. This is a 20-pin socket with fool-proof connector on EVB board as shown in Figure 3-6. Users
could use Nuvoton Nu-Link2 Pro, J&D Tech CodeViser, or other debugger supports CoreSight SoC-
400.

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Figure 3-6 ICE Interface

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4 DEVELOPMENT ENVIRONMENT SETUP
This section describes the steps to build up the BSP dev elopement environment without using Yocto
or Buildroot. Please refer to MA35D1 Yocto User Manual or MA35D1 Buildroot User Manual for setting
up the development environment using Yocto or Buildroot.
4.1 Linux Development Environment
Except for Coretx-M4 bare-metal firmware, the development environment in based on Linux system.
Both native or client OS in virtual machine could be used. This chapter describes the setting for the
Linux platform based on Ubuntu distribution. For users using other distribution such as Fedora,
CentOS, the settings and operating procedures are alike except the package management system is
DNF instead of APT.
4.1.1 Install Required Packages for Building Host
Not every required packaged for building MA35D1 are install by default and have to be installed
manually. Here is the command to install required package building MA35D1 BSP on an Ubuntu
system.
$ sudo apt install gawk wget git-core diffstat unzip texinfo gcc-multilib \
build-essential chrpath socat cpio python3 python3-pip python3-pexpect \
xz-utils debianutils iputils-ping python3-git python3-jinja2 libegl1-mesa \
libsdl1.2-dev pylint3 xterm xsltproc docbook-utils fop dblatex xmlto \
libncurses5-dev patch
4.1.2 Install Linaro GCC Compiler
Without using Yocto or Buildroot, it is necessary to install a cross compiler to build the firmware
packages. It is recommended to use the GCC compiler provided by Linaro. Go to the download URL:
https://www.linaro.org/downloads/ and select binary format for aarch64-linux-gnu as shown in Figure
4-1.
Figure 4-1 Linaro Download Webpage
Then select the Linux x86_64 version to install in your Linux machine.

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Figure 4-2 Linaro Tool Chain Download Selection
4.2 Coretx-M4 firmware Development Environment
Keil uVision, IAR Embedded Workbench, and NuEclipse are used as bare metal firmware
development environment. NuEclipse supports both Windows®and Linux operating system while Keil
uVision and IAR Embedded Workbench are available on Windows®only. For detail information of
CM4 firmware develop, please refer to MA35D1 RTP User Manual.
4.3 BSP Installation
The MA35D1 supports Yocto project and Buildroot. Both include the MA35D1 TF-A, U-Boot, Linux
kernel, OP-TEE and RTP, and can build images for booting from the MA35D1 SD0, SD1, SPI Flash,
or NAND Flash.
To develop solution with Yocto, please refer to MA35D1 Yocto User Manual.
To develop solution with Buildroot, please refer to MA35D1 Buildroot User Manual.

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5 MA35D1 BOOT SOURCE
The MA35D1 supports booting from different storage devices. It can boot from NAND Flash, SPI NOR
Flash, SPI NAND Flash, SD card, eMMC, USBH with specific mass storage. The MA35D1 also
supports booting from USBD mode what can load firmware to execute from computer. The USBD
mode can be used for programming other storage devices, or to load image to debug during project
develop stage.
After system reset, Internal Boot Rom (IBR) is the first code been executed and it check the Power-
On-Setting and OTP setting to determine the device to load code from. If secure boot is enabled,
images stored in storage devices are encrypted and signed. IBR checks the integrity of boot images,
and only execute the images if they pass the verification.
5.1 Boot from USB
The MA35D1 bootloader supports USB boot (USBH or USBD). USBH boot supports USB 2.0 mass
storage device only. A specific storage should be FAT MBR format. IBR will get information from
sector 2 (offset 0x400) and sector 3 (offset 0x600).
IBR can enter USBD mode based on Power-On-Setting and OTP setting, or because it cannot find
any valid boot info in the storage device specified by Power-On-Setting and OTP. To setup an USB
connection between MA35D1 and computer, Nuvoton provides a tool named NuWriter. This tool first
loads a system initial firmware to MA35D1, and then send a second firmware named xusb.bin to take
over the USB connection and storage access on MA35D1 after the system initial firmware finish
execution. Figure 5-1 illustrates MA35D1 USB boot flow.

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Start
Initial USB Device
Connect to
PC?
Download DDR
Initial DRAM
yes
no
Download xusb.bin
(update firmware) to
DRAM
Jump to image
Boot OK
USB boot
Initial USB Host
EHCI
Read header 0 (sector 2)
Check header
CRC
Image loaded from
MSC device
match
Jump to image
Boot OK
fail
Read header 1 (sector 3)
Load new header
images
USBD USBH
SD backup
enabled
yes
SD backup
boot
First time?
yes
WFI
no
USBD boot
Figure 5-1 Boot from USB Flow
5.2 Boot from NAND Flash
The MA35D1 supports booting from NAND Flash. It supports NAND Flash with 2K, 4K, or 8K page
size with 8-bit ECC, 12-bit ECC, 24-bit ECC, or no ECC for the NAND Flash contains its own ECC
logic. After boot up, IBR uses ONFI and NAND Flash ID to determine the page size and ECC to use.
But users could use Power-On-Setting or OTP to overwrite the NAND Flash attribute detect result. IBR
can only access the NAND Flash using correct attribute, otherwise it’ll report ECC uncorrectable error.
Figure 5-2 illustrates MA35D1 NAND boot flow.

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Start
Supported ID?
Enable NAND
Page size 2KB + 64
ECC–BCH8
Get NAND Device ID
Read ONFI
ONFI supported?
Ignore outside
setting?
(page size / ECC)
Use outside setting
Set Page size
Set ECC
Read header 0
(block 0~3)
Read header 1
(block 0~3)
Check header
CRC
Image loaded
match
Jump to image
Boot OK
Load new header
images
yes
no
yes
fail
no
no
yes
SD backup
enabled
yes
SD backup
boot
First time?
yes
WFI
no
USBD boot
Figure 5-2 Boot from NAND Flash Flow

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5.3 Boot from SPI NAND Flash
The MA35D1 supports booting from SPI NAND Flash using QSPI0 interface. Compared to parallel
NAND Flash, SPI NAND uses less pins to connect with microprocessors. So microprocessors can
save the pins for other purpose.
Depending on the Power-On-Setting and OTP, IBR can set the SPI clock to 50 MHz or 30 MHz and
read data from SPI Flash using 1-bit mode or quad mode.
Please note that the MA35D1 only supports SPI NAND Flash that contains its own ECC control logic.
Figure 5-3 illustrates MA35D1 SPI NAND boot flow.

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Start
Enable QSPI clock
Set 1-bit MFP
Set QSPI clock (OTP)
QSPI control setting
Reset NAND
(0xff)
Get status
(0xf)
Check R/B# status
(0xC0) bit 0
Read header 0 (block 0~3)
one page data
Read 512 bytes
ready
busy
Check header
CRC
Get SPI information (page
size, spare area, …)
Image loaded from
SPI flash
1-bit mode Enable quad mode
Image loaded from
SPI flash
Disable QSPI quad mode
match
4-bit mode
Jump to image
Boot OK
fail
Read header 1 (block 0~3)
one page data
Read 512 bytes
Load new header
images
SD backup
enabled
yes
SD backup
boot
First time?
yes
WFI
no
USBD boot
Figure 5-3 Boot from SPI NAND Flash Flow
5.4 Boot from SPI NOR Flash
The MA35D1 also supports booting from SPI NOR Flash using QSPI0 interface. Like booting from SPI
NAND, IBR can set the SPI clock to 50 MHz or 30 MHz and read data from SPI Flash using 1-bit
mode or quad mode. IBR reads SPI Flash offset 0 to find the boot info marker to boot the system.
Figure 5-4 illustrates MA35D1 SPI NOR boot flow.

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Start
Enable QSPI clock
Set 1-bit MFP
Set QSPI clock (OTP)
QSPI control setting
Read header 0 (offset 0)
512 bytes by 1-bit mode
Check header
CRC
Image loaded from
SPI flash
Enable quad mode
Image loaded from
SPI flash
Disable QSPI quad mode
match
1-bit mode
4-bit mode
Jump to image
Boot OK
fail
Read header 1 (offset
0x1000) 512 bytes by 1-bit
mode
Load new header
images
SD backup
enabled
yes
SD backup
boot
First time?
yes
WFI
no
USBD boot
Figure 5-4 Boot from SPI NOR Flash Flow
5.5 Boot from eMMC and SD Card
The last boot source supports by MA35D1 is eMMC and SD card. User can use Power-On-Setting or
OTP to assign the boot interface to be SD0/eMMC0 or SD1/eMMC1. After reset, IBR reads eMMC/
SD card offset 0x400 to find the boot info marker to boot the system. Figure 5-5 illustrates MA35D1
eMMC/SD card boot flow.

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Start
Enable SD0 clock
Set SD0 MFP
Set SD0 clock to 200kHz
Configure SD0
Is SDHC / SD /
eMMC?
Set SD clock to 20MHz
SD0 setting (data width,
block size)
Read header 0 (sector 2)
Check header
CRC
Image loaded from SD
match
Jump to image
Boot OK
yes
Unknown
WFI
no
fail
Read header 1 (sector 3)
Load new header
images
SDH boot
SD0
Enable SD1 clock
Set SD1 MFP
Set SD1 clock to 200kHz
Configure SD1
SD1
Is SD0 backup
boot?
WFI
yes
USBD boot
no
Figure 5-5 Boot from eMMC/SD Card Flow
5.5.1 Backup Boot from SD0 Interface
The MA35D1 supports a backup boot feature. If the system boot from an interface other than SD0
interface is failed due to image header check failed. IBR will try to the image stores in SD0 if a valid
image header can be found. This feature can be enabled by an OTP setting and is a handy feature to
recover a system which the boot image in its main storage device is damaged.