Nuvoton NuSpeech Series Product manual

N5132 Technical Reference Manual
November 7, 2014 Page 1 of 20 Rev. 1.0
NuSpeech N5132 Technical Reference Manual
NuSpeechFamily
N5132 High Sound Quality Voice Synthesizer
Technical Reference Manual
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of NuVoice microcontroller based
system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com

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Table of Contents
Table of Contents.....................................................................................................................2
List of Tables.............................................................................................................................3
List of Figures...........................................................................................................................3
1General Description .....................................................................................................4
2Features.........................................................................................................................4
3Pin Configuration ..........................................................................................................5
3.1 Pin Assignment (SOP20)................................................................................................ 5
3.2 Pin Description................................................................................................................ 5
4SPI interface..................................................................................................................7
4.1 SPI Command Summary................................................................................................ 8
4.2 The command protocol type ......................................................................................... 10
4.3 The limitations of SPI command protocol..................................................................... 14
4.3.1 The maximum SPI bus serial clock rate .......................................................................14
4.3.2 Intervals between successive SPI commands..............................................................14
4.3.3 Send PLAY commands continually...............................................................................14
4.3.4 How to wake up N5132 ................................................................................................15
5Status Register ...........................................................................................................16
6The Calibration of System Clock..............................................................................17
7Application Circuit.......................................................................................................18
8Revision History..........................................................................................................19

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List of Tables
Table 4-1: The SPI command summary .......................................................................................... 8
Table 6-1: The method to enable the output of 250 Hz clock........................................................ 17
List of Figures
Figure 4-1: N5132 supports SPI bus protocol –Mode 3.................................................................. 7
Figure 4-2: The common features of all command protocol types................................................... 9
Figure 4-3: N5132 receives the PLAY command correctly............................................................ 10
Figure 4-4: The N5132 will not execute this PLAY command. ...................................................... 10
Figure 4-5: The desired protocol sequence for READ_ID command. ........................................... 11
Figure 4-6: The N5132 does not execute the READ_ID command............................................... 11
Figure 4-7: Open the Product ID menu.......................................................................................... 12
Figure 4-8: The SPI bus timing of READ_ID command................................................................. 12
Figure 4-9: N5132 receives a valid command based on the command protocol 1........................ 13
Figure 4-10: N5132 will not execute the received command once ABANDON-code is received.. 13
Figure 4-11: The SPI bus serial clock rate can be up to 12.5KHz................................................. 14
Figure 4-12: The intervals between two successive SPI transitions must be longer than 1 ms.... 14
Figure 4-13: Send STOP command to terminate the previous playback. ..................................... 15
Figure 4-14: The method to wake up N5132 from standby mode. ................................................ 15
Figure 7-1: The application circuit for 3 batteries........................................................................... 18
Figure 7-2: The application circuit for 2 batteries........................................................................... 18

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1 GENERAL DESCRIPTION
The N5132 is a high sound quality Voice Synthesizer with advanced 5-bit MDPCM algorithm. It
includes 4-bit C with SPI interface to communicate with external MCU and PWM output to playback
voice..
Note1: Please refer to data sheet for electrical related spec and typical applications.
2 FEATURES
Wide operation voltage: 2.2~5.5V
Embedded 2M-bit OTP
System clock: 8MHz generated by ring oscillation
Hardware synthesis 1 channel with 5-bit MDPCM data format
–The voice file will be encoded to MDPCM data format by playlist editor tool.
–The playlist editor tool possesses friendly GUI to allow user to define voices combination.
Built-in PWM to drive speaker directly
Provide Watch Dog Timer
Low Voltage Reset (LVR) to avoid lock up
Provide SPI interface to communicate with external MCU
The N5132 operates in SPI bus protocol mode 3 only.
The N5132 will serve as a slave device while external microcontroller is a master.
The SPI bus serial clock rate can be up to 12.5KHz
Package type:
–SOP 20-pin
–Die form

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3 PIN CONFIGURATION
3.1 Pin Assignment (SOP20)
3.2 Pin Description
Name
Type
Power
Description
1. SPI interface
SSB (BP10)
I/O
VDD
The chip select pin of SPI interface.
The alternate function is used to program OTP memory.
SCLK (BP11)
I/O
VDD
The serial clock pin of SPI interface.
The alternate function is used to program OTP memory.
MISO (BP12)
I/O
VDD
The master data input/slave data output pin of SPI interface.
The alternate function is used to program OTP memory.
MOSI (BP13)
I/O
VDD
The master data output/slave data input pin of SPI interface.
The alternate function is used to program OTP memory.
2. Oscillator
OSC
I
V33O
Ring oscillator input. Connect one resistor of 150K ohm to VSS.
3. Speaker Driver
PWM+
O
VDD_SPK
PWM drive positive output.
PWM-
O
VDD_SPK
PWM drive negative output.
VDD_SPK
P
-
Power supply for PWM drive.
VSS_SPK
P
-
Ground for PWM drive.
4. Power
VDD1
P
-
Power supply for BP32 and BP33. It must connect to VDD.
N5132
(SOP20)
1
NC
VSS1
VDD1
PWM+
5
VDD_SPK
PWM-
TEST
VSS_SPK
11 BP11
V33O
BP10
BP12
BP13
VSS
OSC
10
15
VDD
/RESET
VPP
BP33 (CLK250HZ output)
BP32 (0: Enable CLK250HZ output)
20
(SSB) (SCLK)
(MISO)
(MOSI)

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VSS1
P
-
Ground pin. It must connect to VSS.
VDD
P
-
Power supply.
VSS
P
-
Ground pin.
V33O
Pout
VDD
3.3V regulator output. It is for chip internal use only, cannot connect to
external device.
VPP
P
-
Power supply 7.5V input for OTP memory programming.
NC for normal operation.
5. Other
/RESET
I
VDD
Chip reset input pin with Schmitt trigger, internal pull-high.
TEST
I
VDD
Test pin, internal pull-high.
The alternate function is used to program OTP memory.
BP32
I
VDD1
To connect BP32 to GND will enable the output of 250 Hz clock at BP33. But
the BP32 setting can take effect only when the SPI CLK250HZ_EN command
is not issued from host MCU. Please refer to Chapter 6 for detailed
description.
BP33
O
VDD1
This pin will output 250 Hz clock for calibration once SPI command
CLK250HZ_EN is received, or BP32 is connected to GND. Please refer to
Chapter 6 for detailed description.
This pin will change to input type when the N5132 enters standby mode.

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4 SPI INTERFACE
The N5132 uses an industry standard SPI interface to communicate with microcontroller host.
However, the SPI bus protocol includes 4 modes. But the N5132 operates in mode 3 only.
These SPI modes determine the relationship between the serial clock and the data bits. Many
common microcontrollers contain built-in hardware SPI ports. Some of these controllers make the SPI
mode fully programmable, others allow a more limited selection. In order to have direct compatibility
with the N5132, the user should select Mode 3. Attempting to communicate in modes other than 3 will
cause the N5132 to behave unpredictably.
In some cases, users will be emulating the SPI protocol in software using general-purpose port pins.
In this case, the software can be written to manipulate the port pins to achieve the correct relationship.
The correct relationship for Mode 3 is shown in the Figure 4-1.
Figure 4-1: N5132 supports SPI bus protocol –Mode 3
For mode 3, the SSB signal must fall low prior to the first falling edge of SCLK. The data input at MOSI
pin is latched on the rising edge of serial clock (SCLK) and data output at MISO pin shifts out on the
falling edge of SCLK. Finally the SSB is raised to high level to close this SPI transaction.
SSB
SCLK
MOSI
MISO
MSB
Shift out
Shift in
MSB
LSB
LSB

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4.1 SPI Command Summary
The microcontroller host can send commands through the SPI interface to achieve the intended
functions. The SPI commands supported by the N5132 are listed in Table 4-1.
Table 4-1: The SPI command summary
Command
Format
Function description
Command Protocol
1.
END
0x01
END-code at the end of SPI transaction
All protocol types
2.
READ_ID
0x10
Read identification typed in playlist generation
Protocol type 2
3.
READ_STATUS
0x11
Query the value of status register of N5132
Protocol type 3
4.
PLAY
0x7F
Play the selected playlist specified by the
INDEX byte which follows the PLAY command.
The INDEX byte indicates the playlist number.
Protocol type 1
5.
STOP
0x80
Stop playback
Protocol type 3
6.
PWR_DOWN
0x82
N5132 enters standby mode. N5132 will
consume minimum power.
Protocol type 3
7.
CLK250HZ_EN
0x83
Enable the output of 250 Hz clock at BP33 pin
Protocol type 3
8.
CLK250HZ_DIS
0x84
Disable the output of 250 Hz clock at BP33 pin
Protocol type 3
9.
ABANDON
0xE0
ABANDON-code at the end of SPI transaction.
All protocol types
10.
VOL1
0xF1
Small volume
Protocol type 3
11.
VOL2
0xF2
Set volume larger than VOL1 setting
Protocol type 3
12.
VOL3
0xF3
Set volume larger than VOL2 setting
Protocol type 3
13.
VOL4
0xF4
Full volume
Protocol type 3
The N5132 incorporates three types of command protocol to send the SPI commands. A complete
explanation of the command protocol types is described in the section 4.2. But all the command
protocol types possess the common features listed below.
The SPI command is shifted into the first byte of SPI transaction. And the command’s MSB bit is
the first bit to be sent by the microcontroller host.
The value of status register of N5132 is always shifted out as the first byte at MISO pin. And the
MSB of status register is the first bit to be shifted out by the N5132.
The received SPI command by N5132 will be returned to MISO pin after status byte

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Figure 4-2: The common features of all command protocol types
SSB
SCLK
MOSI
MISO
MCU
HOST
Command returned
. . . . . .
(Feature 1)
(Feature 2)
(Feature 3)
0 1 2 4 5 6 73 8 9 10 12 13 14 1511
command
76543210
STATUS
76543210

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4.2 The command protocol type
The N5132 incorporates the command protocols to prevent inadvertent write cycles caused by
spurious system level signals that may exist during power transition. The feature of command protocol
allows microcontroller host to examine in time whether or not the N5132 receives the instructions
correctly.
Command protocol type 1
This command protocol 1 is applied to PLAY command only. The Figure 4-3 shows that the PLAY
command is transmitted successfully. The host can close the SPI transaction after sending three bytes
and N5132 will execute the PLAY command to play the selected playlist specified by the INDEX. The
INDEX byte indicates the playlist number.
Figure 4-3: N5132 receives the PLAY command correctly.
If the PLAY command is not returned correctly, the microcontroller should send an ABANDON-code
following the INDEX byte. The N5132 will not execute the PLAY command. The command protocol to
abort this PLAY command is shown in Figure 4-4.
Figure 4-4: The N5132 will not execute this PLAY command.
SSB
SCLK
MOSI
MISO
MCU
HOST INDEXPLAY command
STATUS
END-code
(0x01)
INDEX
returned
PLAY command
returned
108 9 11 12 13 14 150 1 2 3 4 5 6 7
SSB
SCLK
MOSI
MISO
MCU
HOST INDEXPLAY command
STATUS INDEX
returned
Wrong
command
108 9 11 12 13 14 150 1 2 3 4 5 6 7
ABANDON-code
(0xE0)

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Command protocol type 2
This command protocol 2 is applied to READ_ID only. The READ_ID command is used to read the 4
bytes of product ID bonded to the set of playlists. When user creates the playlists using the playlist
editor tool, user can assign 4-byte hexadecimal codes as the specified product ID at the same time. In
order to do validation of connected chip, the microcontroller host can compare the product ID by using
the READ_ID command. Once READ_ID command is received at the beginning of SPI transaction,
N5132 will shift out the product ID following the returned command. The desired protocol sequence is
shown in Figure 4-5.
Figure 4-5: The desired protocol sequence for READ_ID command.
The microcontroller host can terminate this SPI transaction using the command scheme shown in
Figure 4-6 if the returned command is wrong.
Figure 4-6: The N5132 does not execute the READ_ID command.
To create your product ID, on the Project tab, click the ‘Set product ID’menu (Figure 4-7). On the
menu, type 8 alphanumeric characters as your product ID related to this created project. The Figure
4-8 shows the SPI bus timing to shift the 8 alphanumeric characters to host MCU in detail.
SSB
SCLK
MOSI
MISO
MCU
HOST 0x**
Command
returned
READ_ID
command
STATUS
0x**
ID[23:16]
0x**
ID[15:8] ID[7:0]
0x**
ID[31:24]
01234567
END-code
(0x01)
108 9 11 12 13 14 15
0x** = means do not care
SSB
SCLK
MOSI
MISO
MCU
HOST 0x**
Wrong
command
READ_ID
command
STATUS 0x**
01234567 108 9 11 12 13 14 15
ABANDON-code
(0xE0)
0x** = means do not care

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Figure 4-7: Open the Product ID menu.
Figure 4-8: The SPI bus timing of READ_ID command.
SSB
SCLK
MOSI
MISO
HOST
MCU 0x**
0x10
0x10
STATUS
0x**
0xC3
0x**
0xB2
0x01
0xA1
READ_ID command
ID[31:24]
ID[23:16]
ID[15: 8]
ID[ 7: 0]
0x**
0xD4
0x** = means do not care

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Command protocol type 3
For the other commands except PLAY and READ_ID commands, the command protocol 3 can
achieve the intended functions. The protocol timing is illustrated in Figure 4-9. The microcontroller host
can send the command followed by one END-code and then closes this SPI transaction. The first byte
shifted out at MISO pin by the N5132 is the value of status register which will be described in section
4.4. The second byte shifted out by N5132 is the received command at MOSI pin. So microcontroller
host can examine the returned command to know whether or not the N5132 receives the command
correctly in time. In most cases the microcontroller can acknowledge that this SPI transaction is valid
by closing this SPI transaction after sending an END-code.
Figure 4-9: N5132 receives a valid command based on the command protocol 1.
By contrast, if N5132 returns a wrong command which is not the same to what microcontroller sends,
the microcontroller host can expect the interference occurs at SPI bus, and N5132 does not receive
the command correctly. Then microcontroller can send an ABANDON-code following the END-code to
abort this SPI transaction. While the N5132 receives the ABANDON code, it will not execute the
received wrong command. So this protocol scheme with ABANDON-code can offer protection against
mis-operation. The protocol scheme with ABANDON-code is shown in Figure 4-10.
By comparing to Figure 4-10 and Figure 4-6, the microcontroller host always sends END-code
following the command in this protocol sequence.
Figure 4-10: N5132 will not execute the received command once ABANDON-code is received.
SSB
SCLK
MOSI
MISO
MCU
HOST
Command
returned
Command
STATUS
0 1 2 3 4 5 6 7 108 9 11 12 13 14 15
END-code
(0x01)
SSB
SCLK
MOSI
MISO
MCU
HOST
Wrong
command
Command
STATUS 0x01
returned
01234567 109 11 12 13 14 158
END-code
(0x01)
ABANDON-code
(0xE0)

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4.3 The limitations of SPI command protocol
Users need to notice three operating limitations to use the SPI command protocol of N5132.
4.3.1 The maximum SPI bus serial clock rate
The N5132 can tolerate 12.5 KHz of SPI bus serial clock rate maximally, i.e. the microcontroller host
cannot send the serial clock too quick. The maximum clock rate is 12.5 KHz.
Figure 4-11: The SPI bus serial clock rate can be up to 12.5KHz.
4.3.2 Intervals between successive SPI commands
The SPI transaction is designed to send one command and it may apply certain command protocol
type suitable to the command. When microcontroller host wants to send commands continually, the
intervals between two successive SPI transitions must be longer than 1ms. Otherwise both successive
commands will be ignored by the N5132.
Figure 4-12: The intervals between two successive SPI transitions must be longer than 1 ms.
4.3.3 Send PLAY commands continually
Before the PLAY command is issued, the STATUS register should be check to ensure the previous
playback is completed. If the speech is still busy, and the microcontroller host wants to terminate the
previous playback, then STOP command should be issued prior to next PLAY command.
SSB
SCLK
MOSI
MISO
MCU
HOST
Command returned
Command
STATUS
. . . . . .
0 1 2 4 5 6 73 8 9 10 12 13 14 1511 The microcontroller host cannot send
the serial clock beyond 12.5 KHz.
SSB
SCLK
MOSI
MISO
MCU
HOST Command 1
STATUS
0 1 2 4 5 6 73 0 1 2 4 5 6 73
Command 2
STATUS
³1 ms

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Figure 4-13: Send STOP command to terminate the previous playback.
4.3.4 How to wake up N5132
The N5132 will enter standby mode to consume minimum power after it receives the PWR_DOWN
command. User should notice there is not a specified command to wake up the N5132 from standby
mode. The method to wake up N5132 is to send two successive commands. The N5132 will ignore
the first command and execute the second command. So the first command is a redundant command
and the second command is what microcontroller host would really intend to issue.
Figure 4-14: The method to wake up N5132 from standby mode.
SSB
SCLK
MOSI
MISO
MCU
HOST
Command
returned
STOP command
STATUS
0 1 2 3 4 5 6 7 108 9 1112 13 14 15
END-code
(0x01)
INDEXPLAY command
STATUS
END-code
(0x01)
INDEX
returned
PLAY command
returned
108 9 1112 13 14 150 1 2 3 4 5 6 7
INDEXPLAY command
STATUS
END-code
(0x01)
INDEX
returned
PLAY command
returned
108 9 1112 13 14 150 1 2 3 4 5 6 7
³1 ms
playback is still busy
³1 ms
Command
returned . . . . . .
SSB
SCLK
MOSI
MISO
MCU
HOST
Wrong
command
Command
STATUS
0 1 2 3 4 5 6 7 108 9 11 12 1314 15
STATUS
END-code
(0x01)
01234567
N5132 enters
standby mode ³1 ms
Command
returned
PWR_DOWN
Command
STATUS
0 1 2 3 4 5 6 7 108 9 11 12 1314 15
END-code
(0x01) . . . . . . Command . . . . . .
The redundant
command.
The second command
is what microcontroller
host would really
intend to issue.

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5 STATUS REGISTER
The N5132 has one status register indicating the real-time operating status. It is an 8-bit register and
the MSB bit is the first bit to be shifted out at the beginning of SPI transfer.
Status Register
7
6
5
4
3
2
1
0
SP_BUSY
VALID
Reserved
VOL
Bits
Description
[7]
SP_BUSY
Playback status
0 = N5132 has stopped playing speech.
1 = N5132 is playing speech.
[6]
VALID
The result of SPI command in previous SPI transaction
0 = The previous SPI command is an invalid command. The reason
may be one of below three conditions.
(1) The first byte of previous SPI transfer is not the specified
SPI command.
(2) Wrong command protocol type.
(3) The INDEX value following PLAY command is greater than
the number of available playlists.
(4) The last byte of previous SPI transfer is the ABANDON code
(0xE0), so the previous SPI command is not executed.
1 = The command in previous SPI transaction is received correctly
and N5132 has executed completely.
[5:3]
Reserved
Reserved.
[7:0]
VOL
The volume level of PWM drive
1 = Small volume.
2 = Volume larger than VOL=1 setting.
3 = Volume larger than VOL=2 setting.
4 = Full volume.

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6 THE CALIBRATION OF SYSTEM CLOCK
The desired system clock of N5132 is 8,192 KHz. The system clock is generated by the ring oscillator
which connects 150K ohm resistor at OSC pin to ground. That 150K ohm resistor is labeled as Rosc.
Somehow the built-in ring oscillation circuit may vary from lot to lot. In this case, the 8,192 KHz of
system clock will relate to different Rosc value. The N5132 has one method to calibrate the system
clock. The BP33 will output 250 Hz clock signal when the system clock operates at 8,192 KHz exactly.
When the clock frequency of BP33 signal is more than 250 Hz, it means the system clock is more than
8,192 KHz. In this case, Rosc can be changed to a higher value of 150K ohm. On the other hand,
when the clock frequency of BP33 signal is less than 250 Hz, it means the system clock is less than
8,192 KHz, then Rosc can be changed to a lower value of 150K ohm.
The BP33 is a pull-high input pin by default. In order to facilitate measurement the N5132 provides two
schemes to enable the output of 250 Hz clock signal. One method is to connect BP32 to low and
another method is to send the CLK250HZ_EN command through the SPI command protocol. One is
hardware method and the other is software method to do the same function. These two methods may
conflict at the same time. So the Table 6-1 comes out a truth table to enable the output of 250 Hz
clock.
Table 6-1: The method to enable the output of 250 Hz clock.
The interpretation of Table 6-1 is that the SPI command CLK250HZ_EN will force the output of 250 Hz
clock at BP33 no matter the setting of BP32 pin. The BP32 setting can take effect only when the
CLK250HZ_EN command is not issued or the clock output function is disabled after CLK250HZ_DIS
command is issued.
The 250 Hz clock can occur at BP33 continually no matter playback occurs or not when the clock
output is enabled using the above scheme.
BP32
1
0
1/0
SPI command
CLK250HZ_EN
BP33
250Hz clock
CLK250HZ_DIS No clock
250Hz clock
Ignore
N5132 pins

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7 APPLICATION CIRCUIT
Figure 7-1: The application circuit for 3 batteries.
Figure 7-2: The application circuit for 2 batteries.
1 NC
VSS1
VDD1
PWM+
5 VDD_SPK
PWM-
TEST
VSS_SPK
11BP11
V33O
BP10
BP12
BP13
VSS
OSC
10
15
VDD
/RESET
VPP
BP33
BP32 20
(SSB) (SCLK)
(MISO)
(MOSI)
N5132
(SOP20)
Microcontroller
Host
150 ohm
0.1uF
0.1uF 4.7uF
VCC
VCC
VCC
0.1uF
SPEAKER
1 NC
VSS1
VDD1
PWM+
5 VDD_SPK
PWM-
TEST
VSS_SPK
11BP11
V33O
BP10
BP12
BP13
VSS
OSC
10
15
VDD
/RESET
VPP
BP33
BP32 20
(SSB) (SCLK)
(MISO)
(MOSI)
N5132
(SOP20)
Microcontroller
Host
150 ohm
0.1uF
0.1uF 4.7uF
VCC
VCC
VCC
0.1uF
VCC
SPEAKER

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8 REVISION HISTORY
VERSION
DATE
PAGE/
CHAP.
DESCRIPTION
V1.0
Nov., 2014
-
Initial release.

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Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all
types of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay
claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the
damages and liabilities thus incurred by Nuvoton.