Nuvoton NuMicro NUC980 Series Guide

Application Note for 32-bit NuMicro™Family
Document Information
Abstract
This document introduces how to use the NUC980 series and
describes the minimum hardware resources required to develop a
basic system.
Apply to
NUC980 Series
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of NuMicro microprocessor based system
design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com
NUC980 Series Hardware Design Guide

Table of Contents
1POWER SUPPLIES................................................................................................................ 6
1.1 Power Supply Scheme ................................................................................................................6
1.1.1NUC980 Power Scheme...................................................................................................................7
1.2 Power Operating Modes.............................................................................................................. 7
1.3 DC Electrical Characteristics.....................................................................................................9
1.4 RTCVDD....................................................................................................................................... 11
1.4.1RTC Power Backup & Power Saving............................................................................................11
2RESET....................................................................................................................................... 12
2.1 POR............................................................................................................................................... 12
2.2 nRST............................................................................................................................................. 15
2.3 WDT .............................................................................................................................................. 16
2.4 LVR ............................................................................................................................................... 17
3POWER SEQUENCE...........................................................................................................18
3.1 Power-on Sequence................................................................................................................... 18
3.1.1Condition-1........................................................................................................................................18
3.1.2Condition-2........................................................................................................................................19
3.2 Power-down Sequence ............................................................................................................. 20
4POWER ON SETTING.........................................................................................................21
5CLOCK......................................................................................................................................25
5.1 External Crystal Sources.......................................................................................................... 25
5.2 HXT, High Speed XTAL 12MHz ................................................................................................ 26
5.3 LXT, Low Speed XTAL 32.768 KHz.......................................................................................... 27
6EXTERNAL BUS INTERFACE (EBI)..............................................................................28
6.1 EBI Block Diagram..................................................................................................................... 28
6.2 EBI Pin Configuration................................................................................................................ 29
6.3 EBI Connectivity......................................................................................................................... 31
7SAR_ADC................................................................................................................................32
7.1 ADC Features.............................................................................................................................. 32

7.2 ADC Selection of Input Signals ............................................................................................... 33
7.3 Selection of Reference Voltage ............................................................................................... 34
7.4 ADC Characteristics .................................................................................................................. 35
7.5 Typical Connection and Application Note............................................................................. 36
8USB............................................................................................................................................37
8.1 USB Termination ........................................................................................................................ 38
8.2 USB REXT and USB Power....................................................................................................... 40
8.3 PCB Layout Considerations..................................................................................................... 41
8.3.1Layout Guidelines ............................................................................................................................41
8.3.2Through Hole Consideration for D+ and D- .................................................................................43
8.3.3USB Full Speed Signal Trace for D+ and D- ...............................................................................43
8.3.4USB High Speed Trace Spacing ...................................................................................................44
8.3.5High Speed USB Trace Length......................................................................................................45
8.3.6PCB Stacking for USB.....................................................................................................................45
8.3.7USB EMI/ESD Considerations.......................................................................................................46
8.3.8EMI - Common Mode Chokes........................................................................................................46
8.3.9USB ESD solution............................................................................................................................49
9ETHERNET..............................................................................................................................50
9.1 RMII PHY layout guideline (refer to IC+ IP101G design guide) .......................................... 51
9.2 Power and Ground..................................................................................................................... 53
9.3 Trace Routing ............................................................................................................................. 53
9.3.1Avoid right angle signal trace.........................................................................................................53
9.3.2For Tx+/−, Rx+/− traces ..................................................................................................................53
9.3.3For W & W’ need better isolation, ex: shielding with GND.........................................................54
9.3.4Never running noisy digital signals in parallel with TX+/- and RX+/-........................................54
9.3.5Keep the distance between Tx+/- & Rx+/- differential pairs for good isolation.......................55
9.4 Better Analog Performance...................................................................................................... 57
9.5 ESD Protecting ........................................................................................................................... 57
10 CAPTURE SENSOR INTERFACE...................................................................................58
10.1 Pin Configuration ....................................................................................................................... 58
10.2 Reference Connection............................................................................................................... 59
10.3 PCB Design Considerations..................................................................................................... 60
11 QUAD SERIAL PERIPHERAL INTERFACE (QSPI) .................................................62
11.1 Pin Configuration ....................................................................................................................... 62
11.2 QSPI Reference Connection..................................................................................................... 62
11.3 PCB Layout Considerations for QSPI Flash.......................................................................... 63
11.3.1 Power Supply Decoupling.....................................................................................................63
11.3.2 Clock Signal Routing..............................................................................................................63
11.3.3 Data Signal Routing...............................................................................................................64

11.3.4 Recommendations .................................................................................................................64
12 CONTROLLER AREA NETWORK (CAN) INTERFACE..........................................65
12.1 Pin Configuration ....................................................................................................................... 65
12.2 Reference Connection............................................................................................................... 66
12.3 CAN BUS Layout Recommendations ..................................................................................... 67
13 FMI NAND & SD/EMMC INTERFACES.........................................................................68
13.1 Pin Configuration ....................................................................................................................... 68
13.2 FMI Reference Connection....................................................................................................... 70
13.3 General PCB Signal Routing Guidelines................................................................................ 71
14 I²C, SPI & I²S INTERFACES..............................................................................................72
14.1 Pin Configuration ....................................................................................................................... 72
14.2 Reference Connection............................................................................................................... 74
14.3 PCB Layout Considerations..................................................................................................... 77
14.3.1 I²C.............................................................................................................................................77
14.3.2 SPI............................................................................................................................................77
14.3.3 I²S .............................................................................................................................................77
15 UART & SMART CARD INTERFACE (ISO/IEC 7816-3) .........................................78
15.1 Pin Configuration ....................................................................................................................... 78
15.2 Reference Connection............................................................................................................... 82
16 REFERENCE SCHEMATIC ...............................................................................................85
System Block Diagram.............................................................................................................. 85
GPIO Pin Assignment List........................................................................................................ 86
System Power Supply ............................................................................................................... 87
NUC980 Main Chip ..................................................................................................................... 88
Power CAP Filter........................................................................................................................ 89
RESET, Power-ON Setting, XTAL & Debugging ................................................................... 90
NAND Flash................................................................................................................................. 91
Ethernet RMII PHY + RJ45 ........................................................................................................ 92
I²C Interface................................................................................................................................. 93
LED indication ............................................................................................................................ 94
UART Interface............................................................................................................................ 95
SPI Interface................................................................................................................................ 96
USB HS HOST & Device............................................................................................................ 97

USB1.1 FS HOST lite.................................................................................................................. 98

1 Power Supplies
This section describes design considerations related to the NUC980 series power supply
scheme and power operating modes.
1.1 Power Supply Scheme
The NUC980 series should be supplied by a stabilized power; VDD33, VDD12, MVDD,
AVDD, RTCVDD, USB0_VDD, USB1_VDD, USBPLL0, USBPLL1 and PLLVDD
Some points need to take care when using these power rails:
VIO_VDD pin must be powered by 3.3V10and with external decoupling capacitors.
(place one 0.1uF capacitor for each VDD33 pin is recommended)
VCORE_VDD pin must be powered by 1.2V10and with external decoupling
capacitors. (place one 0.1uF with MLCC and one buck 10uF with Tantalum capacitor for
each VDD12 pin is recommended)
MVDD pin must be powered by 1.8V0.1V and with external decoupling capacitors.
(place one 0.1uF with MLCC and one buck 10uF with Tantalum capacitor for each
MVDD pin is recommended)
AVDD pin must be powered by 3.3V10and with external decoupling capacitors.
(place one 0.1uF capacitor and a buck 10uF capacitor for each AVDD pin is
recommended)
RTCVDD is an independent power domain, it can be powered by 3.6V~2.0V and place
with a 0.1uF decoupling capacitor.
PLLVDD is a phase lock loop power pin which should be supplied by 1.2V10and
with external decoupling capacitors. (place one 0.1uF capacitor and a buck 10uF
capacitor is recommended)
USB0VDD is USB port 0 PHY power pin which should be supplied by 3.3V10and
with external decoupling capacitors. (place one 0.1uF capacitor and one buck 10uF
capacitor is recommended)
USB0PLLVDD is USB port 0 core power pin which should be supplied by 1.2V10
and with external decoupling capacitor. (place one 0.1uF capacitor and one buck 10uF
capacitor is recommended)
USB1VDD is USB port 1 PHY power pin which should be supplied by 3.3V10and
with external decoupling capacitors. (place one 0.1uF capacitor and one buck 10uF
capacitor is recommended)
USB1PLLVDD is USB port 1 core power pin which should be supplied by 1.2V10
and with external decoupling capacitor. (place one 0.1uF capacitor and one buck 10uF
capacitor is recommended)

1.1.1 NUC980 Power Scheme
Figure 1-1 Power Supply Scheme
1.2 Power Operating Modes
The NUC980 provides power management scenarios, including Power-down, Idle and
Normal Operating modes, to manage the power consumption. The peripheral clocks can be
Enabled/Disabled individually by controlling the corresponding bit in CLKSEL control
register. User can turn-off the unused modules’ clock for power saving.
Normal mode: In this mode, CPU run normally and clocks of all functionalities are on.
The clock frequency of CPU, DRAM, AHB peripherals and APB peripherals are 300
MHz, 150 MHz, 150 MHz and 75 MHz, respectively.
Idle mode: When CPU is not busy, user can put ARM926EJ-S™ processor into a low-
power state by the wait for interrupt instruction. In this mode, the clocks of all
functionalities are on. The clock frequency of DRAM, AHB peripherals and APB
peripherals are 150 MHz, 150 MHz and 75 MHz.
Power-down mode: In this mode, all clocks (clocks for all functionalities, CPU and the
HXT (12 MHz) stop, except LXT (32.768 kHz), with SRAM retention.
The mechanisms shown below could wake chip up from Power-down mode:
1. EINT0, EINT1, EINT2 or EINT3 (External Interrupt) pin toggled.
2. GPIO pin toggled.
3. Timer 0/1/2/3/4/5 timeout or capture interrupt is active.
4. WDT time-out interrupt is active.
10uF
10uF
10uF
0.1uF
0.1uF
0.1uF
10uF
0.1uF
0.1uF
VD33
VD12
MVDD
RTCVDD
AVDD33
PLLVDD
USB0PLLVDD
USB1PLLVDD
RTCVDD
AVDD
MVDD
VCORE_VDD
VIO_VDD
USB1VDD
USB0VDD
10uF
10uF
0.1uF
0.1uF
10uF
10uF
10uF
0.1uF
PLLVDD
USBPLL0
USB0VDD
USB1VDD
USBPLL1
0.1uF
0.1uF
USBPLLVSS
USBPLLVSS
PLLVSS
VSS
PLLVSS
AVSS
AVSS
USBPLLVSS
USBPLLVSS

5. RTC alarm or relative alarm interrupt is active.
6. UART 0/1/2/3/4/5/6/7/8/9
–UARTx_nCTS pin toggleed (x is 0, 1, 2, 3, 4, 5, 6, 7, 8 or 9).
–UARTx_RXD pin goes low level (x is 0, 1, 2, 3, 4, 5, 6, 7, 8 or 9).
–Received data FIFO reached threshold.
–Received data FIFO threshold time-out.
–RS-485 address match (AAD Mode).
7. I2C slave mode address match.
8. EMAC 0/1 received a Magic Packet.
9. HSUSBD detected a VBUS change event or USB bus RESET/RESUME event.
10. USB 1.1 Full Speed host controller detected a connect/dis-connect/remote-wakeup event.
11. CANx_RXD pin goes low level (x is 0, 1, 2 or 3).
12. SDH detected card pulg/un-plug event or SDIO card interrupt.
Figure 1-2 Power Operating Modes

1.3 DC Electrical Characteristics
Table 1-3 DC electrical characteristics
Parameter
Sym.
Specification
Test Conditions
MIN.
TYP.
Max.
Unit
Core Operation voltage
VDD12
1.14
1.2
1.32
V
I/O Operation Voltage
VDD33
2.97
3.3
3.63
V
Memory I/O Operation Voltage
for DDR or DDR2
MVDD (1)
1.70
1.8
1.90
V
Memory I/O Operation Voltage
for SDR Type SDRAM
MVDD (2)
2.97
3.3
3.63
V
Battery Operation Voltage
VBAT33
2.0
3.3
3.63
V
USB Operation Voltage (1)
VUSB0_VDD12
VUSB1_VDD12
1.14
1.2
1.32
V
USB Operation Voltage (2)
VUSB0_VDD33
VUSB1_VDD33
2.97
3.3
3.63
V
Power Ground
VSS
AVSS
-0.3
V
Analog Operating Voltage
AVDD33
2.97
3.3
3.63
V
Analog Reference Voltage
AVref
0
AVDD33
V
Current Consumption of
Normal Operating Mode 1
IVDD12
150
mA
VDD12 = 1.2V
MVDD = 1.8V
VDD33 = 3.3V
TA = 25C, FOSC = 12 MHz
Frequency of CPUCLK/DDR_CLK is
300/150 MHz.
All IPs on, all GPIO are input with
pull-up.
IMVDD_1
50
mA
IUSB0_VDD12_1
7.5
mA
IUSB1_VDD12_1
7.5
mA
IUSB0_VDD33_1
35
mA
IUSB1_VDD33_1
35
mA
IVBAT33_1
100
uA
Current Consumption of
Power Down Mode
ISTDBY_VDD12
3
mA
VDD12 = 1.2V
ISTDBY_MVDD
6
mA
MVDD = 1.8V
ISTDBY_VDD33
5
A
VDD33 = 3.3V
ISTDBY_USB0_VDD33
0
A
VUSB0_VDD33 = 3.3V
ISTDBY_USB1_VDD33
0
A
VUSB1_VDD33 = 3.3V
ISTDBY_USB0_VDD12
2.5
A
VUSB0_VDD12 = 1.2V
ISTDBY_USB1_VDD12
2.5
A
VUSB1_VDD12 = 1.2V
ISTDBY_AVDD33
25
A
AVDD33 = 3.3V
ISTDBY_VBAT33
100
A
VBAT33 = 3.3V

Parameter
Sym.
Specification
Test Conditions
MIN.
TYP.
Max.
Unit
System Power Off & RTC VBAT33
Power only
IVBAT33
10
uA

1.4 RTCVDD
NUC980 series is built-in a Real Time Clock (RTC) which is operated by the independent
power supply while the system power is off. The RTC uses a 32.768 KHz external crystal.
This section will describe that design considerations related to the RTCVDD.
1.4.1 RTC Power Backup & Power Saving
For some applications requiring operation with either an external power supply or a battery
backup, it is recommend to implement with a simple diode OR circuitry as the below figure
shown. The diode D1 prevents current from flowing into the CR2032 (3V) battery from LDO
when the external power is supplied.
Low forward voltage Schottky diodes are used to minimize the voltage dropout from the
diode and ensure that the LDO output will be a little higher than CR2032 (3V). This solution
can save CR2302 BAT power life time and provided proper powered to RTCVDD.
When external power is removed and the voltage is dropping lower than VBAT, the CR2032
(3V) battery will start supplying power to NUC980.
To avoid RTCVDD power dropping causes RTC data loss by different power supply
switching through diodes, at least place a 100nF capacitance to VBAT with C1.
The following shows the RTC backup power block diagram for design reference.
3.3V Power
Regulator
Vin RTCVDD
Vo =
3.3V
D2
D1 C1
100nF
Figure 1.4 RTC Power Backup Block

2 RESET
Hardware Reset conditions can be issued by one of the below listed events. For these reset
event flags can be read by RSTSTS register.
Power-on Reset (POR).
Low level on the nRESET Pin (nRST).
Watch-dog time-out reset (WDT).
Low voltage reset (LVR).
2.1 POR
NUC980 provides POR12 for Core power and POR33 for I/O power to guarantee low level
logic output state during the first power up phase.
The Power on Reset (POR) function without external resistor or capacitor could reset the
logic elements to their known state if power on slew rate was ≧1V/1us. The reset signal may
not be available if the power rising rate was too fast.
For detail behaviors and electrical characteristics, it could be refer to the following waveforms
and tables.
Figure 2.1-1 POR12/ POR33 Block

Figure 2.1-2 Power-On Reset at POR12
Table 2.1-1 POR12 Electrical Characteristics
SYMBOL
Description
Min.
Typ.
Max.
Unit
Condition
DVDD
Power Supply
1.2
V
Tr
Power rising rate
1V/1us
Vrr
Active level
0.63
0.76
0.86
V
Power slew rate is
1.2V/20mS@25℃
POR_ENB=0
TPOR
POR output low duration
4.25
uS
Power DVDD(rise) at
Vrr to POR(rise) at 1/2
DVDD (DVDD slew
rate=1V/1uS)
AVDD up to 3.3V@25℃

Figure 2.1-3 Power-On Reset at POR33
Table 2.1-2 POR33 Electrical Characteristics
SYMBOL
Description
Min.
Typ.
Max.
Unit
Condition
DVDD
Power Supply
3.3
V
Tr
Power rising rate
1V/1us
Vrr
Active level
1.65
1.83
2.0
V
Power slew rate is
3.3V/20mS@25℃
POR_ENB=0
TPOR
POR output low duration
5.2
uS
Power AVDD(rise) at
Vrr to POR(rise) at 1/2
AVDD (AVDD slew
rate=1V/1uS)
AVDD up to 3.3V@25
℃

2.2 nRST
Except for typical R & C elements tied to nRST pin is necessary that we also suggest to
adding an auxiliary circuit as the following figure to ensure that system robustness.
Note. About related components parameters use please refer to the below circuitry shows on.
Figure 2.2-1 nRST External CKT
Table 2.2-1 nRESET Characteristics
Symbol
Parameter
Min.
Typ.
Max.
unit
Test Conditions
VILR
Negative going threshold
(Schmitt input), nRESET
-
-
0.3*VDD
V
VDD33 = 3.3V
VIHR
Positive going threshold
(Schmitt Input), nRESET
0.7*VDD
-
-
V
VDD33 = 3.3V
RRST
Internal nRESET pin pull up resistor
-
-
84
KΩ
1. VDD33=3.63V, apply
/RESET pin Vin=
3.63V and measure
the input current
2. Reverse the current
to Resistor value,
R=V/I

2.3 WDT
The purpose of Watchdog Timer (WDT) is to perform a system reset when system runs into
an unknown state. This prevents system from hanging for an infinite period of time. Besides,
this Watchdog Timer supports the function to wake-up system from Idle/Power-down mode.
20-bit free running up counter for WDT time-out interval
Selectable time-out interval (24 ~ 220) and the time-out interval is 0.48828125ms ~ 32s
if WDT_CLK = 32.768 kHz
System kept in reset state for a period of (1 / WDT_CLK) * 63
Supports selectable WDT reset delay period, including 1026、130、18 or 3 WDT_CLK
reset delay period
Supports to force WDT enabled after chip powered on or reset by setting WDTON
(Power-on setting, SYS_PWRON [3]).
Supports WDT time-out wake-up function only if WDT clock source is selected as LXT
(32 KHz low-speed oscillator).

2.4 LVR
The Low Voltage Reset (LVR) and the Low Voltage Detector (LVD) both will generate logic
high or logic low output for digital core once the monitored power, VDD, surpasses or falls
below their detection level. The block diagram as Figure,
Table 2.4-1 Internal LVR/LVD Characteristics
Symbol
Parameter
Min.
Typ.
Max
Unit
Test Conditions
VADD33
Operation Voltage
2.97
3.3
3.63
V
-
TA
Temperature
-40
-
85
C
-
VTH_LVD
LVD Threshold Voltage
2.295
2.55
2.805
V
LVD_SEL (SYS_LVRDCR[9]) =
0
2.475
2.75
3.025
V
LVD_SEL (SYS_LVRDCR[9]) =
1
VTH_LVR
LVR Threshold Voltage
2.115
2.35
2.585
V
-
Figure 2.4-1 LVR and LVD Timing Waveform
Note:
1. When testing the features of LVD/LVR detect levels, the power-up or power-down speed of VDD should be
slower than 100mS/2V.

3 Power sequence
3.1 Power-on Sequence
3.1.1 Condition-1
If TIO ≥ TMVDD ≥ TCORE, the time of delay gap between < 0.5mS is prefer.
Note.
1. The time of delay gap is meaning that timing between TIO with Tcore.
2. When the time of delay gap < 0.5mS could prevent that transient phenomenon while power-on.
Figure 3.1-1 RESET vs. Power-on Sequence (I)

3.1.2 Condition-2
If TCORE ≥ TMVDD ≥ TIO, it is acceptable as the below waveform, the time of delay gap
between < 1mS is prefer.
Note.
1. The time of delay gap is meaning that timing between Tcore with TIO.
2. The time of delay gap < 1mS is prefer although NUC980 have that protection for latchup
prevention.
Figure 3.1-2 RESET vs. Power-on Sequence (II)

3.2 Power-down Sequence
The sequence doesn’t care.
Note.
1. TCORE represents VDD12 powered time for Core power
2. TMVDD represents MVDD powered time for MVDD power
3. TIO represents VDD33 powered time for I/O power