Nuvoton ISD91300 Series Product manual

ISD91300 Series Technical Reference Manual
Sep 9, 2019 Page 1of 466 Revision 1.13
ISD91300 SERIES TECHNICAL REFERENCE MANUAL
ISD ARM®Cortex®-M0 SoC
ISD91300 Series
Technical Reference Manual
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of ISD91300 series microcontroller
based system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact:Nuvoton Technology Corporation.
www.nuvoton.com

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TABLE OF CONTENTS
LIST OF FIGURES ...................................................................................8
LIST OF TABLES.....................................................................................................12
1GENERAL DESCRIPTION...................................................................................13
2FEATURES ..........................................................................................................14
3ABBREVIATIONS ................................................................................................18
4PARTS INFORMATION LIST AND PIN CONFIGURATION................................19
4.1 ISD91300 Product Selection Guide ...........................................................19
4.2 Pin Configuration.................................................................................20
4.2.1 ISD91300 Pin Diagram ...............................................................................20
4.3 Pin Description....................................................................................21
4.3.1 ISD91300 Pin Description............................................................................21
5BLOCK DIAGRAM...............................................................................................26
5.1 ISD91300 Block Diagram .......................................................................26
6FUNCTIONAL DESCRIPTION.............................................................................27
6.1 ARM® Cortex™-M0 Core.......................................................................27
6.2 System Manager .................................................................................29
6.2.1 Overview ................................................................................................29
6.2.2 System Reset ..........................................................................................29
6.2.3 System Power Distribution ...........................................................................30
6.2.4 System Memory Map .................................................................................31
6.2.5 Register Map ...........................................................................................33
6.2.6 Register Description...................................................................................34
6.2.7 System Timer (SYST).................................................................................51
6.2.8 Nested Vectored Interrupt Controller (NVIC)......................................................56
6.2.9 System Control.........................................................................................81
6.3 Clock Controller and Power Management Unit (PMU).....................................88
6.3.1 Overview ................................................................................................88
6.3.2 System Clock &SYST Clock .........................................................................89
6.3.3 Peripheral Clocks......................................................................................90
6.3.4 Power Management...................................................................................91
6.3.5 Register Map ...........................................................................................96
6.3.6 Register Description...................................................................................97
6.4 General Purpose I/O (GPIO) .................................................................113
6.4.1 Overview ..............................................................................................113

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6.4.2 Features...............................................................................................113
6.4.3 Basic Configuration..................................................................................113
6.4.4 Functional Description ..............................................................................114
6.4.5 Register Map .........................................................................................117
6.4.6 Register Description.................................................................................118
6.5 Brownout Detection and Temperature Alarm..............................................129
6.5.1 Overview ..............................................................................................129
6.5.2 Register Map .........................................................................................129
6.5.3 Register Description.................................................................................130
6.6 I2C Serial Interface Controller (I2C)..........................................................135
6.6.1 Overview ..............................................................................................135
6.6.2 Features...............................................................................................135
6.6.3 Functional Description ..............................................................................135
6.6.4 Register Map .........................................................................................149
6.6.5 Register Description.................................................................................150
6.7 PWM Generator and Capture Timer (PWM)...............................................157
6.7.1 Overview ..............................................................................................157
6.7.2 Features...............................................................................................158
6.7.3 Block Diagram........................................................................................159
6.7.4 Functional Description ..............................................................................160
6.7.5 PWM0 Register Map ................................................................................167
6.7.6 Register Description.................................................................................169
6.7.7 PWM1 Register Map ................................................................................186
6.7.8Register Description.................................................................................187
6.8 Real Time Clock (RTC)........................................................................202
6.8.1 Overview ..............................................................................................202
6.8.2 Features...............................................................................................202
6.8.3 Block Diagram........................................................................................203
6.8.4 Functional Description ..............................................................................204
6.8.5 Register Map .........................................................................................207
6.8.6 Register Description.................................................................................208
6.9 Serial Peripheral Interface (SPI) .............................................................221
6.9.1 Overview ..............................................................................................221
6.9.2 Features...............................................................................................221
6.9.3 Block Diagram........................................................................................221
6.9.4 FunctionalDescription...............................................................................222

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6.9.5 Timing Diagram ......................................................................................233
6.9.6 Programming Examples ............................................................................235
6.9.7 Register Map .........................................................................................237
6.9.8 Register Description.................................................................................238
6.10Timer Controller (TIMER) .....................................................................253
6.10.1Overview ..............................................................................................253
6.10.2Features...............................................................................................253
6.10.3Block Diagram........................................................................................254
6.10.4Functional Description ..............................................................................255
6.10.5Register Map .........................................................................................257
6.10.6Register Description.................................................................................258
6.11Watchdog Timer (WDT).......................................................................263
6.11.1Overview ..............................................................................................263
6.11.2Features...............................................................................................263
6.11.3Block Diagram........................................................................................264
6.11.4Functional Description ..............................................................................265
6.11.5Register Map .........................................................................................266
6.11.6Register Description.................................................................................267
6.12UART Interface Controller (UART) ..........................................................269
6.12.1Overview ..............................................................................................269
6.12.2Features...............................................................................................269
6.12.3Block Diagram........................................................................................269
6.12.4Basic Configuration..................................................................................271
6.12.5Functional Description ..............................................................................271
6.12.6Register Map .........................................................................................279
6.12.7Register Description.................................................................................280
6.13I2S Controller (I2S)Audio PCM Controller...................................................297
6.13.1Overview ..............................................................................................297
6.13.2Features...............................................................................................297
6.13.3Block Diagram........................................................................................298
6.13.4Functional Description ..............................................................................299
6.13.5Register Map .........................................................................................304
6.13.6Register Description.................................................................................305
6.14PDMA Controller (PDMA).....................................................................316
6.14.1Overview ..............................................................................................316
6.14.2Features...............................................................................................317

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6.14.3Block Diagram........................................................................................318
6.14.4Functional Description ..............................................................................320
6.14.5Register Map .........................................................................................322
6.14.6Register Description.................................................................................325
7FLASH MEMORY CONTROLLER (FMC)..........................................................353
7.1 Overview.........................................................................................353
7.2 Features .........................................................................................353
7.3 Block Diagram ..................................................................................354
7.4 FunctionalDescription..........................................................................355
7.4.1 Flash Memory Organization........................................................................355
7.4.2 Boot Selection........................................................................................357
7.4.3 Data Flash (DATAF).................................................................................358
7.4.4 User Configuration...................................................................................359
7.4.5 In-System-Programming (ISP) ....................................................................362
7.4.6 Register Map .........................................................................................364
7.4.7 Register Description.................................................................................365
8ANALOG SIGNAL PATH BLOCKS...................................................................372
8.1 Audio Analog-to-Digital Converter (ADC) ..................................................372
8.1.1 Overview ..............................................................................................372
8.1.2 Features...............................................................................................372
8.1.3 Block Diagram........................................................................................372
8.1.4 Functional Description ..............................................................................372
8.1.5 Register Map .........................................................................................376
8.1.6 Register Description.................................................................................377
8.2 Audio Class D Speaker Driver (DPWM)....................................................384
8.2.1 Overview ..............................................................................................384
8.2.2 Features...............................................................................................384
8.2.3 Block Diagram........................................................................................384
8.2.4 Functional Description ..............................................................................384
8.2.5 Register Map .........................................................................................386
8.2.6 Register Description.................................................................................387
8.3 Analog Comparator (ACMP)..................................................................392
8.3.1 Overview ..............................................................................................392
8.3.2 Features...............................................................................................392
8.3.3 Block Diagram........................................................................................392

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8.3.4 Functional Description ..............................................................................393
8.3.5 Register Map .........................................................................................394
8.3.6 Register Description.................................................................................395
8.4 Analog Functional Blocks .....................................................................399
8.4.1 Overview ..............................................................................................399
8.4.2 Features...............................................................................................399
8.4.3 VMID Reference Voltage Generation ............................................................399
8.4.4 GPIO Current Source Generation.................................................................400
8.4.5 LDO Power Domain Control .......................................................................401
8.4.6 Microphone Bias Generator........................................................................402
8.4.7 Analog Multiplexer...................................................................................403
8.4.8 Temperature Sensor Measurement ..............................................................404
8.4.9 Programmable Gain Amplifier .....................................................................405
8.4.10CapSense Relaxation Oscillator/Counter........................................................407
8.4.11Oscillator Frequency Measurement and Control ...............................................409
8.4.12Register Map .........................................................................................411
8.4.13Register Description.................................................................................412
8.5 Automatic Level Control (ALC)...............................................................430
8.5.1 Overview ..............................................................................................430
8.5.2 Block Diagram........................................................................................430
8.5.3 Basic Configuration..................................................................................431
8.5.4 Functional Description ..............................................................................431
8.5.5 Register Map .........................................................................................436
8.5.6 Register Description.................................................................................437
8.6 Biquad Filter (BIQ) .............................................................................442
8.6.1 Overview ..............................................................................................442
8.6.2 Basic Configuration..................................................................................442
8.6.3 Functional Description ..............................................................................442
8.6.4 Register Map .........................................................................................444
8.6.5 Register Description.................................................................................445
9APPLICATION DIAGRAM .................................................................................449
10ELECTRICAL CHARACTERISTICS..................................................................450
10.1Absolute Maximum Ratings...................................................................450
10.2DC Electrical Characteristics .................................................................451
10.2.1Operating Current Curve (Test condition: run NOP) ...........................................454

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10.3AC Electrical Characteristics .................................................................455
10.3.1External 32kHz XTAL Oscillator...................................................................455
10.3.2Internal 49.152MHz Oscillator .....................................................................455
10.3.3Internal 16kHz Oscillator ...........................................................................455
10.4Analog Characteristics.........................................................................456
10.4.1Specification of ADC and Speaker Driver........................................................456
10.4.2ADC Filter Characteristics..........................................................................457
10.4.3Specification of PGA and BOOST ................................................................459
10.4.4Specification of ALC an MICBIAS.................................................................460
10.4.5Specification of LDO & Power management ....................................................461
10.4.6Specification of Brownout Detector ...............................................................461
10.4.7Specification of Power-On Reset (VCCD) .......................................................462
10.4.8Specification of Temperature Sensor.............................................................462
10.4.9Specification of Comparator .......................................................................462
11PACKAGE DIMENSIONS ..................................................................................464
11.164L LQFP (7x7x1.4mm footprint 2.0mm)...................................................464
12............................................................................................... REVISION HISTORY....465

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LIST OF FIGURES
Figure 4-1 ISD91300 Series Selection Code................................................................................. 19
Figure 4-2 ISD91300 LQFP 64-pin Diagram.................................................................................. 20
Figure 5-1 ISD91300 Block Diagram ............................................................................................. 26
Figure 6-1 Functional Controller Diagram...................................................................................... 27
Figure 6-2 ISD91300 Power Distribution Diagram......................................................................... 30
Figure 6-3 Clock Generator Block Diagram................................................................................... 88
Figure 6-4 System Clock Block Diagram ....................................................................................... 89
Figure 6-5 SysTick Clock Control Block Diagram.......................................................................... 89
Figure 6-6 Push-Pull Output......................................................................................................... 114
Figure 6-7 Open-Drain Output ..................................................................................................... 115
Figure 6-8 Quasi-bidirectional I/O Mode...................................................................................... 115
Figure 6-9 I2C Bus Timing............................................................................................................ 136
Figure 6-10 I2C Protocol............................................................................................................... 136
Figure 6-11 START and STOP Conditions.................................................................................. 137
Figure 6-12 Bit Transfer on the I2C Bus....................................................................................... 137
Figure 6-13 Acknowledge on the I2C Bus.................................................................................... 138
Figure 6-14 Master Transmits Data to Slave............................................................................... 138
Figure 6-15 Master Reads Data from Slave ................................................................................ 138
Figure 6-16 Control I2C Bus according to Current I2C Status...................................................... 139
Figure 6-17 Master Transmitter Mode Control Flow.................................................................... 140
Figure 6-18 Master Receiver Mode Control Flow........................................................................ 141
Figure 6-19 Save Mode Control Flow .......................................................................................... 142
Figure 6-20 GC Mode .................................................................................................................. 143
Figure 6-21 Arbitration Lost.......................................................................................................... 144
Figure 6-22 I2C Data Shifting Direction........................................................................................ 145
Figure 6-23 I2C Time-out Count Block Diagram........................................................................... 148
Figure 6-24 PWM Generator Clock Source Control..................................................................... 159
Figure 6-25 PWM Generator Architecture Diagram..................................................................... 159
Figure 6-26 Legend of Internal Comparator Output of PWM-Timer ............................................ 160
Figure 6-27 PWM-Timer Operation Timing.................................................................................. 161
Figure 6-28 PWM Double Buffering Illustration............................................................................ 162
Figure 6-29 PWM Controller Output Duty Ratio........................................................................... 163
Figure 6-30 Paired-PWM Output with Dead-zone Generation Operation ................................... 163
Figure 6-31 Capture Operation Timing ........................................................................................ 164
Figure 6-32 PWM-Timer Interrupt Architecture Diagram............................................................. 165
Figure 6-33 RTC Block Diagram.................................................................................................. 203

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Figure 6-34 SPI Block Diagram.................................................................................................... 221
Figure 6-35 SPI Master Mode Application Block Diagram........................................................... 222
Figure 6-36 SPI Slave Mode Application Block Diagram............................................................. 222
Figure 6-37 32-Bit in One Transaction......................................................................................... 223
Figure 6-38 Word Sleep Suspend Mode...................................................................................... 224
Figure 6-39 Byte Reorder Function.............................................................................................. 225
Figure 6-40 Byte OrderIn Memory ............................................................................................... 225
Figure 6-41 Byte Reorder In Memory........................................................................................... 226
Figure 6-42 2-bit System Architecture.......................................................................................... 228
Figure 6-43 2-bit Transfer Mode (Slave Mode)............................................................................ 228
Figure 6-44 Bit Sequence of Dual Output Mode.......................................................................... 229
Figure 6-45 Bit Sequence of Dual Input Mode............................................................................. 229
Figure 6-46 Quad ModeSystem Architecture............................................................................... 230
Figure 6-47 Bit Sequence of Quad Output Mode......................................................................... 230
Figure 6-48 FIFO Mode Block Diagram....................................................................................... 231
Figure 6-49 SPI Timing in Master Mode ...................................................................................... 233
Figure 6-50 SPI Timing in Master Mode (Alternate Phase of SPI Bus Clock)............................. 233
Figure 6-51 SPI Timing in Slave Mode ........................................................................................ 234
Figure 6-52 SPI Timing in Slave Mode (Alternate Phase of SPI Bus Clock)............................... 234
Figure 6-53 Timer Controller Block Diagram ............................................................................... 254
Figure 6-54 Clock Source of Timer Controller ............................................................................. 254
Figure 6-55 Continuous Counting Mode...................................................................................... 256
Figure 6-56 Watchdog Timer Clock Control................................................................................. 264
Figure 6-57 Watchdog Timer Block Diagram............................................................................... 264
Figure 6-58 UART Clock Control Diagram................................................................................... 269
Figure 6-59 UART Block Diagram................................................................................................ 270
Figure 6-60 Auto Flow Control Block Diagram............................................................................. 273
Figure 6-61 UART CTS Auto Flow Control Enabled.................................................................... 274
Figure 6-62 UART RTS Auto Flow Control Enabled.................................................................... 274
Figure 6-63 UART RTS Flow with Software Control.................................................................... 275
Figure 6-64 IrDA Control Block Diagram ..................................................................................... 275
Figure 6-65 IrDA TX/RX Timing Diagram .................................................................................... 276
Figure 6-66 Structure of LIN Frame............................................................................................. 277
Figure 6-67 Structure of LIN Byte ................................................................................................ 277
Figure 6-68 I2S Controller Block Diagram.................................................................................... 298
Figure 6-69 I2S Clock Control Diagram........................................................................................ 299
Figure 6-70 I2S Data Format Timing Diagram.............................................................................. 300

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Figure 6-71 MSB Justified Data Format Timing Diagram............................................................ 300
Figure 6-72 FIFO Contents for Various I2S Modes...................................................................... 302
Figure 6-73 Master Mode Interface.............................................................................................. 303
Figure 6-74 Slave Mode Interface................................................................................................ 303
Figure 6-75 DMA Controller Block Diagram................................................................................. 318
Figure 6-76 CRC Generator Block Diagram ................................................................................ 319
Figure 7-1 Flash Memory Control Block Diagram........................................................................ 354
Figure 7-2 Flash Memory Organization ....................................................................................... 356
Figure 7-3 Program Executing Range for Booting from APROM and LDROM ........................... 357
Figure 7-4 Flash Memory Structure ............................................................................................. 358
Figure 7-5 Example Flow of Boot Selection by BS Bit................................................................. 362
Figure 8-1 ADC Signal Path Block Diagram ................................................................................ 372
Figure 8-2 ADC Clock Control...................................................................................................... 373
Figure 8-3 SDADC Controller Interrupt........................................................................................ 374
Figure 8-4 DPWM Block Diagram................................................................................................ 384
Figure 8-5 Analog Comparator Block Diagram............................................................................ 392
Figure 8-6 Comparator Controller Interrupt Sources ................................................................... 393
Figure 8-7 Comparator Hysteresis Function................................................................................ 393
Figure 8-8 VMID Reference Generation ...................................................................................... 399
Figure 8-9 GPIO Current Source Generation .............................................................................. 400
Figure 8-10 LDO Power Domain.................................................................................................. 401
Figure 8-11 MICBIAS Block Diagram........................................................................................... 402
Figure 8-12 MICBIAS Application Diagram.................................................................................. 402
Figure 8-13 Analog Multiplexer Control Signals........................................................................... 403
Figure 8-14 PGA Signal Path Block Diagram .............................................................................. 405
Figure 8-15 PGA Structure........................................................................................................... 405
Figure 8-16 CapSense Function Block Diagram.......................................................................... 407
Figure 8-17 Oscillator Frequency Measurement Block Diagram................................................. 409
Figure 8-18 Example SUPERFINE Trim Frequency Adjustment................................................. 410
Figure 8-19 Typical Oscillator Frequency versus SYS_IRCTCTL Setting................................... 410
Figure 8-20 ALC Block Diagram .................................................................................................. 430
Figure 8-21 ALC Response Graph............................................................................................... 431
Figure 8-22 ALC Normal Mode Operation ................................................................................... 432
Figure 8-23 ALC Hold Time ......................................................................................................... 432
Figure 8-24 ALC Limit Mode Operation ....................................................................................... 433
Figure 8-25 ALC Operation with Noise Gate disabled................................................................. 434
Figure 8-26 ALC Operation with Noise Gate Enabled................................................................. 434

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Figure 9-1 Application Diagram.................................................................................................... 449
Figure 10-1 Operating Current Curve .......................................................................................... 454
Figure 10-2 ADC Filter Characteristics ........................................................................................ 457
Figure 10-3 ADC Filter Characteristics Zoom In.......................................................................... 458

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LIST OF TABLES
Table 3-1 List of Abbreviations....................................................................................................... 18
Table 6-1 Address Space Assignments for On-Chip Controllers................................................... 32
Table 6-2 Exception Model ............................................................................................................ 57
Table 6-3 System Interrupt Map..................................................................................................... 58
Table 6-4 Vector Table Format...................................................................................................... 59
Table 6-5 I2C Status Code Description........................................................................................ 147
Table 6-6 Watchdog Timer Time-out Interval Period Selection................................................... 265
Table 6-7 UART Interface Controller Pin ..................................................................................... 271
Table 6-8 UART Baud Rate Equation.......................................................................................... 271
Table 6-9 UART Controller Interrupt Source and Flag List in DMA Mode................................... 272
Table 6-10 Controller Interrupt Source and Flag in Software ModeList....................................... 273
Table 7-1 Memory Address Map.................................................................................................. 355
Table 7-2 ISP Command List....................................................................................................... 363
Table 7-3 Device ID Memory Size ............................................................................................... 363
Table 8-1 Sample Rates for HCLK=49.152MHz.......................................................................... 373
Table 8-2 Sample Rates for HCLK=32.768MHz.......................................................................... 373
Table 8-3 Sample Rates for HCLK=24.576MHz.......................................................................... 374
Table 8-4 Sample Rates for HCLK=16.384MHz.......................................................................... 374
Table 8-5 DPWM Sample Rates for Various HCLK..................................................................... 385
Table 8-6 Temperature Sensor Measurement............................................................................. 404
Table 8-7 PGA Input Impedance Variation with Gain Setting...................................................... 406
Table 10-1 Absolute Maximum Ratings....................................................................................... 450
Table 10-2 DC Electrical Characteristics ..................................................................................... 453
Table 10-3 External 32kHz XTAL Oscillator ................................................................................ 455
Table 10-4 Internal 49.152MHz Oscillator ................................................................................... 455
Table 10-5 Internal 16 KHz Oscillator.......................................................................................... 455
Table 10-6 Specification of ADC and Speaker Driver.................................................................. 456
Table 10-7 Specification of PGA and BOOST ............................................................................. 459
Table 10-8 Specification of ALC an MICBIAS.............................................................................. 460
Table 10-9 Specification of LDO & Power management ............................................................. 461
Table 10-10 Specification of Brownout Detector.......................................................................... 462
Table 10-11 Specification of Power-On Reset (VCCD)............................................................... 462
Table 10-12 Specification of Temperature Sensor ...................................................................... 462
Table 10-13 Specification of Comparator .................................................................................... 463

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1 GENERAL DESCRIPTION
The ISD91300 series are system-on-chip products optimized for low power, audio record and
playback with an embedded ARM® Cortex™-M0 32-bit microcontroller core.
The series embeds a Cortex™-M0 core running up to 98MHz with 68K/145K-byte of non-volatile
flash memory and 16K-byte of embedded SRAM. It also comes equipped with a variety of
peripheral devices, such as Timers, Watchdog Timer (WDT), Real-time Clock (RTC), Peripheral
Direct Memory Access (PDMA), a variety of serial interfaces (UART, SPI/SSP, I2C, I2S), PWM
modulators, GPIO, Analog Comparator, Low Voltage Detector and Brown-out detector.
The ISD91300 series comes equipped with a rich set of power saving modes including a Deep
Power Down (DPD) mode drawing less than 1µA. A micro-power 16KHz oscillator can periodically
wake up the device from deep power down to check for other events. A Standby Power Down
(SPD) mode can maintain a real time clock function at less than 10µA.
For audio functionality the ISD91300 series includes a Sigma-Delta ADC with 90dB SNR
performance coupled with a Programmable Gain Amplifier (PGA) capable of a maximum gain of
61dB to enable direct connection of a microphone. Audio output is provided by a Differential Class
D amplifier (DPWM) that can deliver 1W of power to an 8Ω speaker.
The ISD91300 series provides in total 32 general purpose IO pins (GPIO), including 16 pins which
are analog enabled. These pins can be configured to connect to an analog comparator, can be
configured as analog current sources or can be routed to the SDADC for analog conversion. They
can also be used as a relaxation oscillator to perform capacitive sensing.

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2 FEATURES
The equipped features are dependent on the product line and their sub products.
Core
– ARM® Cortex™-M0 core running up to 98.304MHz.
– One 24-bit System tick timer for operating system support.
– Supports a variety of low power sleep and power down modes.
– Single-cycle 32-bit hardware multiplier.
– NVIC (Nested Vector Interrupt Controller) for 32 interrupt inputs, each with 4-levels of priority.
– Serial Wire Debug (SWD) support with 2 watchpoints/4 breakpoints.
Power Management
– Wide operating voltage range from 2.4V to 5.5V.
– Power management Unit (PMU) providing four levels of power control.
– Deep Power Down (DPD) mode with sub micro-amp leakage (<1µA).
– Wakeup from Deep Power Down via dedicated WAKEUP pin or timed operation from internal
low power16kHz oscillator.
– Standby mode with limited RAM retention and RTC operation (<10µA).
– Wakeup from Standby can be from any GPIO interrupt, RTC or BOD.
– Sleep mode with minimal dynamic power consumption.
– 3V LDO for operation of external 3V devices such as serial flash.
Flash EPROM Memory
– 68/145K bytes Flash EPROM for program code and data storage.
– Mini-cache to maintain near zero-wait state memory access.
– 4KB of flash can be configured as boot sector for ISP loader.
– Support In-system program(ISP) and In-circuit program (ICP) application code update.
– 1K byte page erase for flash.
– Configurable boundary to delineate code and data flash.
– Support 2 wire In-circuit Programming (ICP) update from SWD ICE interface.
SRAM Memory
– 16K bytes embedded SRAM.
Clock Control
– One high speed and two low speed oscillators providing flexible selection for different
applications. No external components necessary.
– Built-in trimmable oscillator with range of 16-49.152MHz. Factory trimmed within 1% to
settings of 49.152MHz 36.864MHz and 32.768MHz. User trimmable with in-built frequency
measurement block (OSCFM) using reference clock of 32kHz crystal or external reference
source.
– Ultra-low power (<1uA) 16kHz oscillator for watchdog and wakeup from power-down or
sleep operation.
– External 32kHz crystal input for RTC function and low power system operation.
GPIO
– 32 general purpose IO pins, including 16 analog enabled.
– Four I/O modes:
Quasi-bidirectional
Push-pull output
Open-drain output
Input only with high impendence
– TTL/Schmitt trigger input selectable

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– I/O pin can be configured as interrupt source with edge/level setting.
– Switchable pull-up.
Audio Analog to Digital converter
– Sigma Delta ADC with configurable decimation filter and 16 bit output.
– 90dB Signal-to-Noise (SNR) performance.
– Programmable gain amplifier with 32 steps from -12 to 35.25dB in 0.75dB steps.
– Boost gain stage of 26dB, giving maximum total gain of 61dB.
– Input selectable from dedicated MIC pins or analog enabled GPIO.
– Programmable biquad filter to support multiple sample rates from 8-32kHz.
– DMA support for minimal CPU intervention.
Differential Audio PWM Output (DPWM)
– Direct connection of speaker.
– 1W drive capability into 8Ω load.
– High efficiency 88%
– Configurable up-sampling to support sample rates from 8-32kHz.
– DMA support for minimal CPU intervention.
Timer
– Two timers with 8-bit pre-scaler and 24-bit resolution.
– Counter auto reload.
Watchdog Timer
– Default ON/OFF by configuration setting.
– Multiple clock sources.
– 8 selectable time out period from micro seconds to seconds (depending on clock source).
– WDT can wake up power down/sleep.
– Interrupt or reset selectable on watchdog time-out.
RTC
– Real Time Clock.
– Counter (second, minute, hour) and calendar counter (day, month, year).
– Alarm registers (second, minute, hour, day, month, year).
– Selectable 12-hour or 24-hour mode.
– Automatic leap year recognition.
– Time tick and alarm interrupts.
– Device wake up function.
– Supports software compensation of crystal frequency by compensation register (FCR).
PWM/Capture
– Six 16-bit PWM generators provide sixsingle ended PWM outputs or three complementary
paired PWM outputs.
– The PWM generator equipped with a clock source selector, a clock divider, an 8-bit pre-
scaler and Dead-Zone generator for complementary paired PWM.
– PWM interrupt synchronous to PWM period.
– 16-bit digital Capture timers (shared with PWM timers) provide rising/falling capture inputs.
– Support Capture interrupt.
UART
– UART ports with flow control (TX, RX, CTS and RTS).
– 8-byte FIFO.
– Support IrDA (SIR) and LIN function.

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– Programmable baud-rate generator up to 1/16 of system clock.
SPI
– SPI Clock up to 24MHz.
– SPI data rate in Quad mode of 98 Mbps.
– Support MICROWIRE/SPI master/slave mode (SSP).
– Full duplex synchronous serial data transfer.
– Variable length of transfer data from 1 to 4 bytes.
– MSB or LSB first data transfer.
– 2 slave/device select lines when used in master mode.
– Hardware CRC calculation module available for CRC calculation of data stream.
– DMA support.
– Quad/Dual SPI support.
I2C
– Master/Slave up to 1Mbit/s.
– Bidirectional data transfer between masters and slaves.
– Multi-master bus (no central master).
– Arbitration between simultaneously transmitting masters without corruption of serial data on
the bus.
– Serial clock synchronization allows devices with different bit rates to communicate via one
serial bus.
– Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
– Programmable clock allowing versatile rate control.
– I2C-bus controller supports multiple address recognition.
I2S
– Interface with external audio CODEC.
– Operate as either master or slave.
– Capable of handling 8, 16, 24 and 32 bit word sizes.
– Mono and stereo audio data supported.
– I2S and MSB justified data format supported.
– Two 8 word FIFO data buffers are provided, one for transmit and one for receive.
– Generates interrupt requests when buffer levels cross a programmable boundary.
– Supports DMA requests, for transmit and receive.
Brown-out detector
– With 16 levels: 2.1V, 2,2V, 2.4V, 2.5V, 2.65V, 2.8V, 3.0V, 3.1V, 3.2V, 3.4V, 3.6V, 3.7V, 3.8V,
3.9V, 4.2V, 4.6V.
– Supports time-multiplex operation to minimize power consumption.
– Supports Brownout Interrupt and Reset option.
Built in Low Dropout Voltage Regulator (LDO)
– Capable of delivering 30mA load current.
– Configurable for output voltage of 1.8V, 2.4V, 3.0V and 3.3V.
– Ten GPIO (GPIOA<7:0>& GPIOB<13:12>) operate from LDO voltage domain allowing direct
interface to, for example, 3V SPI Flash.
– Can be bypassed and voltage domain supplied directly from system power.
Additional Features
– Over temperature alarm. Can generate interrupt if device exceeds safe operating

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temperature.
– Temperature proportional voltage source which can be routed to ADC for temperature
measurements.
– Digital Microphone interface.
Operating Temperature: -40℃~85℃
Packages:
– All Green package (RoHS).
– LQFP 64-pin.

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3 ABBREVIATIONS
Acronym Description
ACMP Analog Comparator Controller
ADC Analog-to-Digital Converter
APB Advanced Peripheral Bus
AHB Advanced High-Performance Bus
BOD Brown-out Detection
FIFO First In, First Out
FMC Flash Memory Controller
GPIO General-Purpose Input/Output
HCLK The Clock of Advanced High-Performance Bus
ICP In Circuit Programming
ISP In System Programming
LDO Low Dropout Regulator
MPU Memory Protection Unit
NVIC Nested Vectored Interrupt Controller
PDMA Peripheral Direct Memory Access
PLL Phase-Locked Loop
PWM Pulse Width Modulation
SPI Serial Peripheral Interface
TMR Timer Controller
UART Universal Asynchronous Receiver/Transmitter
WDT Watchdog Timer
Table 3-1 List of Abbreviations

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4 PARTS INFORMATION LIST AND PIN CONFIGURATION
4.1 ISD91300 Product Selection Guide
Part number Flash SRAM Max. CPU
Freq I/O Package
I91331RI 68 KB 16 KB 98.304 MHz up to 32 LQFP64
I91331VRI 68 KB 16 KB 98.304 MHz up to 32 LQFP64
I91361RI 145 KB 16 KB 98.304 MHz up to 32 LQFP64
I91361VRI 145 KB 16 KB 98.304 MHz up to 32 LQFP64
I9
ISD Audio Product Family
Product Series
1: Cortex-M0
Flash ROM
1: 16KB
3: 64+4KB
6: 145KB
SRAM
SW Feature
Blank: Standard
C: Voice Recognition
Temperature
I: -40°C ~ +85°C
Package
R: LQFP-64
1 3 x x x x x
Family ID
3: Family Series ID
Figure 4-1 ISD91300 Series Selection Code

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4.2 Pin Configuration
4.2.1 ISD91300 Pin Diagram
4.2.1.1 ISD91300 LQFP 64 pin
LQFP 64-pin
54 53 56 55 58 57 60 59 62 61 63 64
36
40
34
33
48
47
46
45
38
39
35
37
20 21 18
19
32
17
30 31 29
22 23
24
1
2
3
4
6
7
8
9
10
5
11
12
PA.0/SPI_MOSI0/MCLK
VCCLDO
PA.5/I2S_BCLK/SPI_SSB1
PA.3/SPI_MISO0/I2C_SDA
PA.7/I2S_SDO
PA.4/I2S_FS
PA.6/I2S_SDI/UART_TX
PB.12/SPI_MISO1/PWM1CH0/PWM1CH1_INV
PA.2/SPI_SSB0
PA.1/SPI_SCLK/I2C_SCL
VDD33
SPI_SCLK/CMP2/I2C_SCL/PB.2
VCCD
NC
VREG
SPI_SSB0/CMP0/SPI_SSB1/PB.0
SPI_SSB1/CMP1/MCLK/PB.1
SPI_MISO0/CMP3/I2C_SDA/PB.3
SPI_MOSI0/CMP4/PWM0CH0_INV/PB.4
SPI_MOSI1/CMP6/I2S_SDI/PB.6
SPI_MISO1/CMP5/PWM0CH1_INV/PB.5
WAKEUP
CMP7/I2S_SDO/PB.7
PWM0CH2/CMP12/UART_TX/PA.8
SPK+
VCCSPK
NC
SPK-
VSSSPK
NC
PWM0CH3/CMP13/UART_RX/PA.9
PWM1CH1/SDIN/TM1/PA.15
NC
NC
VCCSPK
MICBIAS PA.11/I2C_SCL/I2S_SDO/UART_CTSn
VSSA VMID MIC+ MIC- PA.10/I2C_SDA/I2S_SDI/UART_RTSn
XI32K NC VCCA NC XO32K
13
14
15
16
25 26 27 28
ICE_DAT
RESETN
ICE_CLK
NC
44
43
42
41
PB.15/PWM0CH3/PWM0CH2_INV
VSSD
PB.14/PWM0CH2/UART_TX/PWM0CH3_INV
NC
50 49 52 51
PA.12/PWM0CH0/SPKP/I2S_FS
NC PA.13/PWM0CH1/SPKM/I2S_BCLK
PA.14/TM0/SDCLK/SDCLKn
CMP8/I2S_FS/PB.8
CMP10/PB.10
CMP9/I2S_BCLK/PB.9
CMP11/I2S_SDO/PB.11
PB.13/SPI_MOSI1/PWM1CH1/PWM1CH0_INV
Figure 4-2 ISD91300 LQFP 64-pin Diagram