NXP Semiconductors LX2160ARDBGSG User manual

1 Introduction
The Layerscape® LX2160A reference design board (RDB) provides a
comprehensive platform that enables design and evaluation of the Layerscape
LX2160A processor.
The LX2160ARDB functions with an integrated development environment
(IDE), such as CodeWarrior Development Studio. For instructions on how
to work with the CodeWarrior Development Studio IDE, see CodeWarrior
Development Studio for LS series - ARM V8 ISA, Targeting Manual.
This document provides details of different board interfaces and explains how
to set up and boot the board.
2 Related documentation
The table below lists and explains the additional documents and resources that you can refer to for more information on the
LX2160ARDB. Some of the documents listed below may be available only under a non-disclosure agreement (NDA). To request
access to these documents, contact your local NXP field applications engineer (FAE) or sales representative.
Table 1. Related documentation
Document Description Link / how to access
LX2160A Reference Design Board
Reference Manual
Provides detailed description of the LX2160ARDB LX2160ARDBRM.pdf
LX2160A Reference Design Board
Errata
Describes known errata and workarounds for the
LX2160ARDB
LX2160ARDBE.pdf
LX2160A Product Brief Provides a brief overview of the LX2160A processor LX2160APB.pdf
LX2160A Data Sheet Provides information about electrical characteristics,
hardware design considerations, and ordering information
LX2160A.pdf
LX2160A Reference Manual Provides a detailed description about the LX2160A multicore
processor and its features, such as memory map, serial
interfaces, power supply, chip features, and clock information
LX2160ARM.pdf
LX2160A Chip Errata Lists the details of all known silicon errata for the LX2160A Contact NXP FAE /
sales representative
LX2160A Design Checklist, AN5407 This document provides recommendations for new designs
based on the LX2160A. This document can also be used to
debug newly designed systems by highlighting those aspects
of a design that merit special attention during initial system
start-up.
AN5407.pdf
Table continues on the next page...
Contents
1 Introduction......................................1
2 Related documentation................... 1
3 Hardware kit contents......................2
4 Chassis and board pictures.............3
5 Power and reset buttons................. 6
6 Connectors......................................6
7 Jumpers...........................................8
8 DIP switches..................................10
9 LEDs..............................................13
10 Getting started with LX2160ARDB
...................................................... 16
11 Troubleshooting............................ 22
12 Revision history.............................22
LX2160ARDBGSG
LX2160A Reference Design Board Getting Started Guide
Supports LX2160ARDB, Board Revisions B and C
Rev. 5 — 28 September 2021 User Guide

Table 1. Related documentation (continued)
Document Description Link / how to access
Layerscape Software Development
Kit User Guide
Describes how to work with LSDK, which is a complete Linux
kit for NXP Layerscape Arm-based SoCs and the reference
and evaluation boards available for them.
LSDKUG.pdf
CodeWarrior Development Studio
for LS series - ARM V8 ISA,
Targeting Manual
Explains how to use the CodeWarrior Development Studio for
LS series - ARM V8 ISA product.
CWARMv8TM.pdf
CodeWarrior TAP Probe User
Guide
Provides details of CodeWarrior® TAP, which enables target
system debugging through a standard debug port (usually
JTAG) while connected to a developer workstation through
Ethernet or USB
CWTAPUG.pdf
3 Hardware kit contents
The table below lists the items included in the LX2160ARDB hardware kit.
Table 2. Hardware kit contents
Item description Quantity
LX2160ARDB hardware assembly with enclosure 1
3-conductor power cord 1
DB9 shielded serial cable 1
1.8 meter Cat-6 Ethernet cable 1
32 GB SD card, Samsung MB-ME32GA/AM (UHS-I) 1
Zip lock bag containing 1U chassis bracket (2 pieces) + screw (8 pieces) 1
LX2160ARDB insert card 1
Apart from the main LX2160ARDB kit, two optional kits are also available for purchase at nxp.com:
•LX2RDBKIT1-10-40: Contains transceivers and cables recommended to be used for testing 10/40 Gigabit Ethernet
performance on the LX2160ARDB
• LX2RDBKIT2-25G: Contains transceivers and cables recommended to be used for testing 25 Gigabit Ethernet
performance on the LX2160ARDB
The table below describes the items included in the LX2RDBKIT1-10-40 kit.
Table 3. LX2RDBKIT1-10-40 kit contents
Item description Manufacturer Manufacturing part
number
For port/slot Quantity
Cat-6 Ethernet cable, 6
ft length, orange
10X8-03106 10G MAC3/4 2
40G-BASE-SR4
QSFP+ optical
transceiver module, 40
Gbit/s multi-mode, 850
Mellanox Technologies MC2210411-SR4 40G MAC2 1
Table continues on the next page...
NXP Semiconductors
Hardware kit contents
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Table 3. LX2RDBKIT1-10-40 kit contents (continued)
Item description Manufacturer Manufacturing part
number
For port/slot Quantity
nm wavelength, 150 m
maximum reach
QSFP+ LAN optical
cable, multi-mode,
OM3 50/125, MPO
connector, 3 m length
12FMPOOM3 - 66239 40G MAC2 1
Samsung 32 GB (U1)
EVO select micro-SD
card with adapter
Samsung MB-ME32GA/AM SD card 1
The table below describes the items included in the LX2RDBKIT2-25G kit.
Table 4. LX2RDBKIT2-25G kit contents
Item description Manufacturer Manufacturing part
number
For port/slot Quantity
SFP-25G-SR optical
transceiver module, 25
Gbit/s multi-mode, 850
nm wavelength, 100 m
maximum reach
Mellanox Technologies MMA2P00-AS 25G MAC5/6 1
LAN optical cable,
multi-mode, OM3
50/125, LC duplex
connector, 3 m length
OM3-LC-LC-DX-
FS-3M-PVC - 41728
25G MAC5/6 1
4 Chassis and board pictures
This section provides labelled images of the LX2160ARDB chassis and board for easy identification of different board
components. The board components marked with labels are described in the subsequent sections.
The figure below shows the front side view of the LX2160ARDB chassis.
Power button
Reset button
Ethernet ports
Figure 1. LX2160ARDB chassis
The figure below shows the back panel of the LX2160ARDB chassis.
NXP Semiconductors
Chassis and board pictures
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Power jack
Figure 2. Chassis back panel
The figure below shows the onboard connectors of the LX2160ARDB.
P3
J4 J32
J30
J42
P1
J1
J2
J13
J28
J14
J48
BT1
J29
J26 J27
J25 J24
J46
J40
J43
J37
J21
J19 J18
P2
J23
J53
J11
J47
J22
J44 J54 J34
J36
J55
J35 J10
J5
J15
J17
J16
J41 J38J39
J3
Figure 3. Connectors
The figure below shows the jumpers, LEDs, and DIP switches available on the LX2160ARDB.
NXP Semiconductors
Chassis and board pictures
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J33
J6
J7
J31
J8
J9
D1
D11 D10
D9
D5
D39-D28
D44-D45
D43-D42
D27-D24
D41
D23-D18
SW4-SW1
D13
Figure 4. Jumpers, LEDs, and DIP switches
The figure below shows a closer look of the DIP switches.
SW1 SW2 SW3 SW4
Figure 5. DIP switches
NXP Semiconductors
Chassis and board pictures
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5 Power and reset buttons
The power and reset buttons are present on the front panel of the LX2160ARDB chassis (see Figure 1). Both power and reset
buttons are push buttons. The table below describes the power and reset buttons.
Table 5. Power and reset buttons
Identifier Label Function Description
SW5 PWR Power cycle Pressing SW5 turns the power ON or OFF
SW7 RST System reset Pressing SW7 resets the system, including the device and all the
attached peripherals
You cannot switch off the board completely when the SW_AUTO_ON switch (SW4[2]) is set to ON/1. In this mode, pressing the
power switch turns the power off briefly, then it immediately turns back on. To turn off power, set the SW_AUTO_ON switch to
OFF/0 or disconnect the AC power.
To avoid any damage to SDHC1 port pins due to a silicon erratum, follow these recommendations:
•Always use the power button on the front panel to power down the system. Do not power down the system by unplugging
the power adapter.
• Before removing AC power to power cycle the system:
— Insert an SDHC card in the SDHC card slot
— Allow Linux to boot and configure EVDD to 1.8 V
6 Connectors
The LX2160ARDB has numerous onboard connectors (see Figure 3). The table below describes the LX2160ARDB connectors.
Table 6. LX2160ARDB connectors
Connector Connector type Description Typical connection
BT1 3-pin battery holder RTC battery Connects to 3 V standby CR2032 lithium coin
cell battery
J1 2x4-pin ATX 12 V
connector
12 V ATX power supply Connects to the ATX power supply; both
connections are required
J2 2x12-pin ATX connector Main ATX power supply
J3 1x2-pin header Remote power Connects to remote power switch
J4 1x2-pin header Remote reset Connects to remote reset switch
J5 2x6-pin header VDD_DEBUG Connects to Analog Devices PMBus
monitoring tool (not included in the hardware
kit)
J47 1x2-pin connector VDD measurement Allows remote measurement of VDD
J48 1x2-pin connector GVDD measurement Allows remote measurement of GVDD
J11 2x5-pin Arm JTAG header Arm JTAG Connects to CodeWarrior TAP using a 10-pin
cable
J53 2x5-pin header CPLD JTAG Connects to JTAG interface for CPLD
programming
Table continues on the next page...
NXP Semiconductors
Power and reset buttons
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Table 6. LX2160ARDB connectors (continued)
Connector Connector type Description Typical connection
J18 QSFP+ cage 40G MAC2: 40 Gbit
Ethernet
Accepts one zQSFP+ transceiver (optical or
copper) (not included in the hardware kit)
J19 SFP cage (2) 25G MAC5/6: 25 Gbit
Ethernet
Accepts two SFP+ transceivers (optical or
copper) (not included in the hardware kit)
J21 RJ45-19 connector 10G MAC3: 10 Gbit
USXGMII
Connects to external RJ45 Ethernet cable
J22 RJ45-19 connector 10G MAC4: 10 Gbit
USXGMII
Connects to external RJ45 Ethernet cable
P1 RJ45 connector (2) 1G MAC17/18: 1
Gbit RGMII
•1G MAC17 (bottom)
• 1G MAC18 (top)
Connects to external RJ45 Ethernet cable
J45 (board revision
B)
1x3-pin connector 40G interface
programming
Provides direct access to CS4223 data
EEPROM for programming purposes
P2 DB9 connector (2) UART1 (bottom)
UART2 (top)
Connects to external RS-232 cable
P3 DB9 connector (2) CAN1 (bottom)
CAN2 (top)
Connects to external CAN adapter cable
J23 PCIe Gen 3 x4 connector PCI Express slot #1 Connector for Gen 1/2/3 PCIe cards, or right-
angle/low-profile chassis adapter accepting
Gen 1/2 cards
J28 PCIe Gen 3 x8 connector PCI Express slot #2 Connector for Gen 1/2/3 PCIe cards
J24 SATA-3 header SATA1 Connector for user-supplied SATA disk
J25 SATA-3 header SATA2 Connector for user-supplied SATA disk
J26 SATA-3 header SATA3 Connector for user-supplied SATA disk
J27 SATA-3 header SATA4 Connector for user-supplied SATA disk
J30 USB 3.0 Type-A
connector
USB1 (Host mode by
default)
Connects to USB-compatible device
J32 USB 3.0 Micro-AB
connector
USB2 (OTG mode by
default)
Connects to USB-compatible device
J42 SD card receptacle SD card slot Provides access to an SDHC/SDXC card
J13 2x10-pin connector QSPI emulator Connects to DediProg EM100Pro QSPI
emulator using a sideband cable (ISP-ADP-
intel-B)
J46 1x2-pin connector QSPI emulator reset Allows system reset to be triggered by
DediProg EM100Pro emulator using the ISP-
ADP-intel-B cable
Table continues on the next page...
NXP Semiconductors
Connectors
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Table 6. LX2160ARDB connectors (continued)
Connector Connector type Description Typical connection
J34 1x3-pin header I2C1 Provides remote access to I2C1 bus
J36 1x3-pin header I2C1_CH0 Provides remote access to I2C1 channel 0
segment
J55 1x3-pin header I2C1_CH1 Provides remote access to I2C1 channel 1
segment
J37 1x3-pin header I2C1_CH3 Provides remote access to I2C1 channel 3
segment
J35 1x3-pin header I2C5 Provides remote access to I2C5 bus
J43 1x3-pin header I2C6 Provides remote access to I2C6 bus
J10 1x5-pin header GPIO/event access Provides access to GPIO/event pins
J38 1x4 connector Fan #1 (placed near
bottom of PCB)
Provides PWM-controlled 12 V power for
cooling fans
J39 1x4 connector Fan #2 (placed near
bottom of PCB)
J41 1x4 connector Fan #4 (placed near
bottom of PCB)
J40 1x4 connector Fan #3 (placed near
bottom of PCB)
J44 1x4 connector Fan #5 (placed near top of
PCB)
J54 1x3 connector Heatsink fan (placed near
Fan #5)
J29 2x6-pin header 1588 test Provides access to IEEE 1588 pins
J50 (board revision
B)
Subminiature version A
(SMA) coaxial connector
SMA #1 Provides access to recovered IEEE-1588
clock. J50 is not installed, by default.
J52 (board revision
B)
SMA coaxial connector SMA #2 J52 is not installed, by default
J14 288-pin DDR4 UDIMM
socket
DDR4#1 DIMM#1 Single/dual rank UDIMM inserted
J15 288-pin DDR4 UDIMM
socket
DDR4#1 DIMM#2 Single/dual rank UDIMM (optional)
J17 288-pin DDR4 UDIMM
socket
DDR4#2 DIMM#1 Single/dual rank UDIMM inserted
J16 288-pin DDR4 UDIMM
socket
DDR4#2 DIMM#2 Single/dual rank UDIMM (optional)
7 Jumpers
Jumpers (or shorting headers) are used to select some options that either do not change often or involve power conduction. The
LX2160ARDB jumpers are shown in Figure 4 and are described in the table below.
NXP Semiconductors
Jumpers
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Table 7. LX2160ARDB jumpers
Jumper Type Name/function Description
J6 1x2-pin connector TA_BB_TMP_DETECT_B enable Open: TA_BB_TMP_DETECT_B pin
is grounded
Shorted: TA_BB_TMP_DETECT_B pin is
powered (default setting)
J7 1x2-pin connector VBAT power for TA_BB_VDD
enable
Not supported. Do not install J7. See
LX2160A
Reference Design Board Errata for more
details.
J8 1x2-pin connector PROG_MTR voltage control (for
NXP use only)
Open: PROG_MTR pin is powered off
(default setting)
Shorted: PROG_MTR pin is powered by OVDD
(1.8 V)
J9 1x2-pin connector TA_PROG_SFP voltage control
(for NXP use only)
Open: TA_PROG_SFP pin is powered off
(default setting)
Shorted: TA_PROG_SFP pin is powered by
OVDD (1.8 V)
J31 1x2-pin connector USB1 mode setting Open: USB1 works in Endpoint mode
Shorted: USB1 works in Host mode
(default setting)
J33 1x2-pin connector USB2 mode setting Open: USB2 works in On-The-Go (OTG) mode
(default setting)
Shorted: USB2 works in Host mode
J56 (board
revision B)
2x3-pin connector Inphi CS4223 GUI access Normal mode (default setting):
• J56, pins 1-2: Shorted
• J56, pins 5-6: Shorted
• J57: Open
GUI mode:
• J56, pins 1-2: Open
• J56, pins 5-6: Open
• J57: Shorted
After switching to GUI mode, connect a
BeagleBone and a 3.3 V - 1.8 V level shifter
to J56 at pins 1-3-5.
J57 (board
revision B)
1x2-pin connector
J58 (board
revision B)
1x2-pin connector PWM fan speed control Open: 100% speed
Shorted: 50% speed (default setting)
Most of these jumpers are installed during assembly, and they do not require any change.
NOTE
NXP Semiconductors
Jumpers
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8 DIP switches
The LX2160ARDB provides dual inline package (DIP) switches to allow easy configuration of the system for the most popular
board options. These switches are stored in BRDCFG and DUTCFG registers by CPLD before being used, allowing software
(either local or remote) to reconfigure the system as needed.
The table below explains the DIP switches available in the LX2160ARDB. For each DIP switch:
•If the switch is up (on), the value is 1
• If the switch is down (off), the value is 0
Table 8. Switch settings
Switch Supported function Description
SW1[1:4] RCW fetch location
CFG_RCW_SRC[3:0]
SW_RCW_SRC[3:0]
•0000: Hard-coded RCW
• 1000: SDHC1: SD card
• 1001: SDHC2: eMMC
• 1010: I2C boot EEPROM
• 1100: XSPI sNAND, 2 KB pages
• 1101: XSPI sNAND, 4 KB pages
• 1111: XSPI serial NOR, 24-bit address (default setting)
SW1[5] Reset mode
RESET_REQ_B
SW_RST_MODE
• 0: Ignore RESET_REQ_B
• 1: Trigger system reset on assertion of RESET_REQ_B (default setting)
SW1[6:8] XSPI_A device mapping
CFG_XSPI_MAP[3:0]
SW_XMAP[2:0]: Controls how XSPI_A chip-selects are connected to
devices/peripherals.
Bit value XSPI_A_CS0 XSPI_A_CS1 Description
000 (default
setting)
DEV#0 DEV#1 Boot from default
flash memory
001 DEV#1 DEV#0 Boot from
alternative flash
memory
010 QSPI emulator DEV#0 Boot from QSPI
emulator
011 QSPI emulator DEV#1 Boot from QSPI
emulator
100 DEV#0 QSPI emulator User defined
SW2[1] PCIe Spread-Spectrum
enable
CFG_SPREAD
SW_SPREAD
•0: 100 MHz clocks for PCIe slots are fixed (default setting)
• 1: 100 MHz clocks for PCIe slots are spread-spectrum modulated
Table continues on the next page...
NXP Semiconductors
DIP switches
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Table 8. Switch settings (continued)
Switch Supported function Description
SW2[2] (board
revision B)
CS4223 configuration
CFG_40GE_ROM
SW_INIT40GE
•0: CS4223 40 GbE PHY is not self-configured (default setting)
• 1: CS4223 40 GbE PHY is self-configured on reset
SW2[2] (board
revision C)
Unused Reserved with 0 as the default setting
SW2[3] PCIe slot clock enable
CFG_CLKEN_SLOT[1:2]_B
SW_SLOTCLK
• 0: PCIe slots are clocked only when a card is installed (default setting)
• 1: PCIe slots are clocked always
SW2[4] SDHC voltage control
SDHC1_VSEL
SW_SDHC_VCTL
• 0: Normal mode (LX2160A input/output at risk) (default setting)
• 1: Lock EVDD at 1.8 V (SDHC may not work)
SW2[5] Unused Reserved with 0 as the default setting
SW2[6] Extended DDR PHY Reset
Timing mode
CFG_ENG_USE0
SW_RSTDLY / SW_ENGUSE0
• For LX2160A silicon revision 1.0:
— Reserved with 1 as the default setting
• For LX2160A silicon revision 2.0 or later:
— 0: Extended (delayed) reset timing for DDR PHY (default setting)
— 1: Standard reset timing for DDR PHY
SW2[7] Unused
CFG_ENG_USE1
SW_ENGUSE1
Reserved with 1 as the default setting
SW2[8] DDR clock source selection
CFG_ENG_USE2
SW_DDRSRC / SW_ENGUSE2
• 0: DDR clocked from DDRCLK pin (default setting)
• 1: DDR clocked from differential SYSCLK
SW3[1:3] Device type selection
TEST_SEL_B,
CFG_SVR[0:1]
SW_TESTSEL_B + SW_SVR[0:1]
• 011: LX2120A/E
• 110: LX2080A/E
• 111: LX2160A/E (default setting)
• All other values are reserved
SW3[4] SoC use
CFG_SOC_USE
SW_SOCUSE
• 1: Normal mode (default setting)
Do not change the default setting of this switch.
NOTE
SW3[5:7] Unused SW_MODE_SEL[2:0]
Table continues on the next page...
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DIP switches
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Table 8. Switch settings (continued)
Switch Supported function Description
Reserved with 000 as the default settings
Do not change the default settings of this switch.
NOTE
SW3[8] Unused Reserved with 0 as the default setting
SW4[1] Bypass mode SW_BYPASS_B
•0: Disable thermal monitors and other alarms
• 1: Normal operation (default setting)
SW4[2] Automatic power on SW_AUTO_ON
• 0: Normal power on/off (default setting)
• 1: Always power up
SW4[3] System configuration write
protect
CFG_MEM_WP
SW_CFG_WP
• 0: Allow writes to SYSID and I2C flash
• 1: Write-protect SYSID and I2C flash (default setting)
SW4[4] JTAG Scan mode
TBSCAN_EN_B
SW_TBSCAN
• 0: Boundary Scan mode
• 1: Debugging mode (default setting)
SW4[5] Boot Box mode SW_BOOTBOX_B
• 0: Enable Boot Box mode
• 1: Normal operating mode (default setting)
SW4[6] VDD power enable SW_VDD_DIS
• 0: Enable VDD power supply (default setting)
• 1: Disable VDD power supply (for manufacturing setup only)
SW4[7:8] General purpose
CFG_GPIN[7:6]
SW_GPIN[7:6]
• 00: Software or end-user defined (default setting)
The table below summarizes the default switch settings of the LX2160ARDB DIP switches.
Table 9. Default switch settings
DIP switch [1] [2] [3] [4] [5] [6] [7] [8]
SW1[1:8] 1 1 1 1 1 0 0 0
SW2[1:8] 0 0 0 0 0 0 1 0
SW3[1:8] 1 1 1 1 0 0 0 0
SW4[1:8] 1 0 1 1 1 0 0 0
NXP Semiconductors
DIP switches
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9 LEDs
The LX2160ARDB has numerous onboard light-emitting diodes (LEDs), which can be used to monitor various system functions,
such as power on, reset, board faults, and so on. The information collected from LEDs can be used for debugging purposes. The
table below lists all the LEDs present on the LX2160ARDB.
Table 10. LX2160ARDB LEDs
Reference
designator
LED color LED name Description (when LED is ON)
D1 Yellow PRELOAD The PSU-loading FET is active; it may be hot during
power-up or shortly afterward. Avoid touching this area.
D18 Blue PASS The CPLD has completed power and reset sequencing
and no errors are detected
D19 Yellow ASLEEP The processor has not exited Sleep mode, which generally
indicates:
•Improper RCW source selection
• Boot memory does not contain a valid RCW/PBL
• PLL multipliers in the RCW data are not compatible
with the fixed SYSCLK, DDRCLK, or SDCLK values
D20 Red FAIL One of the following has happened:
• A thermal over-temperature fault has occurred
• One or more power supplies have not started
• Software has set the register CTL[0] (FAIL) to indicate
a software fault
D21 Red PORST The CPLD is asserting PORESET_B to the processor and
is in the process of restarting the system
D22 Red RST REQ The processor is asserting RESET_REQ_B. This is
typically due to the reasons described for the ASLEEP
LED.
D23 Red THERM Thermal monitors have detected a thermal fault and have
shut down the system
Unless reprogrammed by user
software, the thermal trip point is
85 °C.
NOTE
D41 Red ROTERR The processor has been installed in the socket rotated
90, 180, or 270 degrees from the pin 1 orientation. The
system and device power supplies have been shut down
to protect the device.
D24 Green M7 General status. See Multi-status LEDs for details.
D25 Green M6
D26 Green M5
Table continues on the next page...
NXP Semiconductors
LEDs
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Table 10. LX2160ARDB LEDs (continued)
Reference
designator
LED color LED name Description (when LED is ON)
D27 Green M4
D42 Green M3
D43 Green M2
D45 Green M1
D44 Green M0
D28 Green 3VSB The ATX power supply is supplying 3.3 V “standby power”
to the system. The system cannot power up unless this
supply is provided.
D29 Green 3V3 3V3 ATX power supply is operating correctly
D30 Green VDD VDD (processor core) power supply is operating correctly
D31 Green GVDD GVDD (DDR4) power supply is operating correctly
D32 Green SDAV SD_AVDD power supply is operating correctly
D33 Green USBV USB_SVDD power supply is operating correctly
D34 Green OVDD OVDD power supply is operating correctly
D35 Green 0V85 0V85 power supply is operating correctly
D36 Green VTT1 VTT1 power supply is operating correctly
D37 Green SDV SD_VDD power supply is operating correctly
D38 Green 2Vx 2V1 and 2V5 power supplies are operating correctly
D39 Green LVX 0V9 and 1V2 power supplies are operating correctly
D5 Green QSFP A QSFP module is installed in the QSFP port
D9 Green 25GMAC5 An SFP module is installed in 25G MAC5 SFP port
D10 Green 25GMAC6 An SFP module is installed in 25G MAC6 SFP port
D11 Green USB1_5V 5 V power is supplied to the USB #1 connector for external
devices
D13 Green USB2_5V 5 V power is supplied to the USB #2 connector for external
devices
9.1 Multi-status LEDs
The board includes eight multi-status LEDs that indicate hardware activity; however, software can override these LEDs to use
them for debugging purposes. The table below describes the functions of the multi-status LED arrays.
NXP Semiconductors
LEDs
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Table 11. LED array functions
LED If FAIL LED is OFF If FAIL LED is ON
Startup (power on to
power-up complete)
Normal behavior Fault code
M7 Power Sequencer state
(see Table 12)
"Idle" pattern, a pattern shown
to indicate that the FPGA has
completed all startup activities
If FAIL LED is ON and M[7:0] are not blinking,
then the fault code is the same as the ALARM
register. Otherwise, it shows the failing tier
number alternately, as follows:
XXXX 0000
0000 XXXX
where XXXX indicates tier number + 1. Fault
code is made to blink in this way to differentiate
power failures from regular alarm codes. Fault
codes are explained in table below.
Fault code Tier number
0001 0000
0000 0001
Tier 0 => ATX,
USB_HVDD (3V3)
0010 0000
0000 0010
Tier 1 => 0V85, 0V9, 1V2
0011 0000
0000 0011
Tier 2 => VDD,
OVDD, 2V1, 2V5,
SD_AVDD, USB_SVDD
0100 0000
0000 0100
Tier 3 =>
SD_SVDD, SD_OVDD
0101 0000
0000 0101
Tier 4 => GVDD, VTT1,
VTT2, EVDD
M6
M5
M4 Off always
M3 Reset Sequencer state
(see Table 13)
Live I2C1_SCL activity
M2 Live I2C remote activity
M1 Same as M[3:2], except that short
pulses are stretched to 500 ms for
easier detection
M0
The LX2160ARDB power up voltage sequence diagram (LX2160ARDB Reference Manual) lists the power
supplies assigned to each tier.
NOTE
Table 12. Power Sequencer state
State LED: M[7:4] Description
IDLE 1110 = 0xE Waiting for power-on events (for example, switch)
WAIT_ATX 0000 = 0x0 Waiting for ATX PSU to report stable
EN_TIER1 0001 = 0x1 Enable tier 1 PSUs, wait for tier 1 power-good reports
EN_TIER2 0010 = 0x2 Enable tier 2 PSUs, wait for tier 2 power-good reports
Table continues on the next page...
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Table 12. Power Sequencer state (continued)
State LED: M[7:4] Description
EN_TIER3 0011 = 0x3 Enable tier 3 PSUs, wait for tier 3 power-good reports
EN_TIER4 0100 = 0x4 Enable tier 4 PSUs, wait for tier 4 power-good reports
WAIT_ALL 0110 = 0x6 Wait for all unmanaged PSUs to report power-good
PG_FAIL 0111 = 0x7 All power supplies were not stable within 1800*30 ns after the last
power was enabled
STABLE 1000 = 0x8 Power sequencing complete. Wait for power-off events.
DISABLE 1101 = 0xD Disable tiers 4..1 PSUs, in that order, with 1 ms delay
FAULT 1111 = 0xF Fault occurred. Power supplies were shut down due to thermal
faults or die rotation errors.
Table 13. Reset Sequencer state
State LED: M[3:0] Description
IDLE 0000 = 0x0 Waiting for initial reset events
RECONFIG 0010 = 0x2 Update configuration from registers
CLOCK_LOCK 0101 = 0x5 Wait for clock PLLs to stabilize
RELEASE_ALL 0110 = 0x6 Release all hardware resets except DUT
RELEASE_DUT 0111 = 0x7 Release DUT from reset
STABLE 1000 = 0x8 Reset sequencing complete. Wait for reset events.
RESET_REQ 1001 = 0x9 Start reset due to DUT RESET_REQ_B
PORESET 1010 = 0xA Start reset due to JTAG_RST_B
RST_WATCH 1011 = 0xB Start reset due to watchdog timeout
RST_BY_REG 1100 = 0xC Start reset due to setting register bit RST_CTL[RST] = 1
RST_BY_SW 1101 = 0xD Start reset due to pushbutton switch
RECONFIG 1110 = 0xE Start reset due to reconfig request via RCFG[GO] = 1
POST_RST 1111 = 0xF Wait for reset requests to clear
10 Getting started with LX2160ARDB
This section explains:
•Prerequisites
•Booting LX2160ARDB
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10.1 Prerequisites
To set up your LX2160ARDB, you need the items listed in the table below.
Table 14. Prerequisites
Item Available in
board kit?
Purpose / required action
Hardware
Host computer system capable of
running a terminal emulator
No Host computer (for example, Windows PC, Linux system, or Mac) to
control and monitor the LX2160ARDB from the serial console via a serial
terminal emulator, such as Tera Term.
You can also use a Linux machine to connect to the
board console via a Linux utility, such as Minicom.
NOTE
AC power cord Yes To connect the board to AC power supply
DB9 female to DB9 female
serial cable
Yes To make a console connection from UART1 port of the board
USB-to-serial adapter No To connect the serial port of DB9 cable to the USB port of the
host computer
Cat-6 Ethernet cable Yes To connect the board to network to get updated board software
UHS-1 SD card Yes A USH-1 SD card should always be plugged into the SD card slot
when the board is powered on, even if the SD card is not used.
Otherwise, the LX2160A SoC could be damaged. For more details, see
the "eSDHC interface" section of LX2160A Reference Design Board
Reference Manual .
CodeWarrior TAP (optional) No To debug and control the board using the CodeWarrior IDE
Software
USB to serial/UART/RS-232 driver No Download and install on the host computer from Internet
Tera Term (serial
terminal emulator)
No Download and install on the host computer from Internet
TFTP server No Download and install on the host computer from Internet
10.2 Booting LX2160ARDB
If the board is configured with the default switch settings and power is supplied to the board, then the boot loader (U-Boot) image
located in FlexSPI NOR flash DEV#0 runs.
To boot the board, follow these steps:
1. Ensure that you have met the prerequisites described in Table 14.
2. Open the chassis top cover and ensure that the board is configured with the default switch settings, as mentioned in
Table 9.
3. Verify that the board has default jumper settings (see Jumpers).
4. Connect one end of the AC power cord to the wall mount power switch and the other end of the cable to the power jack
available on the chassis back panel, as shown in the figure below.
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Figure 6. Power supply connection
As a precautionary step, the power switch mounted on the wall (if available) must be turned off before connecting
the power cord.
NOTE
5. Turn on the wall mount power switch. The D28 LED (3VSB) turns ON when the standby power is available (see figure
below).
D28 LED
Figure 7. Standby power indicator
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6. Connect one end of the DB9 female to DB9 female cable to the UART1 port available on chassis front panel (see figure
below) and the other end of the cable to the USB-to-serial adapter. Connect the other end of the USB-to-serial adapter
to the USB port of the host machine. This connection allows you to make a console connection between the board and
host computer to see the console output.
Figure 8. Console connection
7. Optionally, connect the CodeWarrior TAP to the board by performing the following steps:
Follow the instructions included with the CodeWarrior package to set up the environment and host attachment,
such as USB and Ethernet.
NOTE
a. Connect the 10-pin micro adapter (CWH-CTP-CTX10-YE), provided with the CodeWarrior TAP, to the
CodeWarrior TAP.
b. Connect one end of the 10-wire cable (gray ribbon cable) to the 10-pin micro adapter (both ends of the wire are
keyed and can be connected on either side).
c. Connect the other end of the 10-wire cable to the 10-pin Arm JTAG header (J11) on the board, as shown in the
figure below.
Figure 9. CodeWarrior TAP connection
Pin 1 of the gray ribbon cable connector should align with pin 1 of the debug port header on the board.
NOTE
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8. Optionally, connect the Ethernet cable if you want to connect your board to the network, for example, for obtaining latest
board software and updating board images.
9. Set up Tera Term on the host computer:
a. Start Tera Term. The Tera Term console appears along with the Tera Term: New connection dialog.
b. On the Tera Term: New connection dialog, select the Serial option, and ensure that COM: USB-to-Serial Comm
Port is selected in the Port menu.
c. Close the Tera Term: New connection dialog by clicking OK.
d. Choose Setup > Serial port from the Tera Term console menu bar. The Tera Term: Serial port setup dialog
appears.
e. On the Tera Term: Serial port setup dialog, configure the serial port of the host computer with the following
settings:
• Baud rate: 115200
• Data: 8 bit
• Parity: none
• Stop: 1 bit
• Flow control: none
f. Close the Tera Term: Serial port setup dialog by clicking OK, and complete setting up Tera Term. This
configuration sets a console connection between the board and the host computer.
10. Press the power button available on the chassis front panel. The status LEDs on the PCB run through various patterns
while powering up the board. The board boots up and the console shows the U-Boot messages as given below:
NOTICE: BL2: v2.3():v2.3-LSDK-20.12
NOTICE: BL2: Built : 22:20:18, Apr 19 2021
NOTICE: UDIMM 18ADF2G72AZ-3G2E1
NOTICE: DDR4 UDIMM with 2-rank 64-bit bus (x8)
NOTICE: 32 GB DDR4, 64-bit, CL=22, ECC on, 256B, CS0+CS1
NOTICE: BL2: Booting BL31
NOTICE: BL31: v2.3():v2.3-LSDK-20.12
NOTICE: BL31: Built : 22:20:18, Apr 19 2021
NOTICE: Welcome to LX2160ARDB BL31 Phase
U-Boot 2020.04-00006-g0f2cfcb048 (Apr 19 2021 - 22:20:08 +0530)
SoC: LX2160ACE Rev2.0 (0x87360020)
Clock Configuration:
CPU0(A72):2200 MHz CPU1(A72):2200 MHz CPU2(A72):2200 MHz
CPU3(A72):2200 MHz CPU4(A72):2200 MHz CPU5(A72):2200 MHz
CPU6(A72):2200 MHz CPU7(A72):2200 MHz CPU8(A72):2200 MHz
CPU9(A72):2200 MHz CPU10(A72):2200 MHz CPU11(A72):2200 MHz
CPU12(A72):2200 MHz CPU13(A72):2200 MHz CPU14(A72):2200 MHz
CPU15(A72):2200 MHz
Bus: 750 MHz DDR: 3200 MT/s
Reset Configuration Word (RCW):
00000000: 5883833c 24580058 00000000 00000000
00000010: 00000000 0c010000 00000000 00000000
00000020: 036001a0 00002580 00000000 00000096
00000030: 00000000 00000000 00000000 00000000
00000040: 00000000 00000000 00000000 00000000
00000050: 00000000 00000000 00000000 00000000
00000060: 00000000 00000000 00027000 00000000
00000070: 08b30010 00150020
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