NXP Semiconductors i.MX 8MDQLQ User manual

© 2019 NXP B.V.
i.MX 8MDQLQ Hardware Developer’s Guide
1. Overview
This document aims to help hardware engineers design
and test the i.MX 8MDQLQ series processor. It gives
examples on board layout, design checklists to ensure
first-pass success, and solutions to avoid board bring-up
problems.
Engineers should understand board layouts and board
hardware terminology.
This guide is released with relevant device-specific
hardware documentation such as datasheets, reference
manuals, and application notes. All these documents are
available on www.nxp.com/i.MX8M.
NXP Semiconductors
User's Guide
Document Number: IMX8MDQLQHDG
Rev. 2 , 06/2019
Contents
1. Overview............................................................................ 1
1.1. Device supported .................................................... 2
1.2. Essential references................................................. 2
1.3. Supplementary references ....................................... 2
1.4. Related documentation............................................ 3
1.5. Conventions ............................................................ 3
1.6. Acronyms and abbreviations................................... 4
2. i.MX 8MDQLQ design checklist ....................................... 5
2.1. Design checklist table ............................................. 5
2.2. JTAG signal termination....................................... 10
3. i.MX 8MDQLQ layout/routing recommendations........... 11
3.1. Introduction........................................................... 11
3.2. Basic design recommendations............................. 11
3.3. Stack-up recommendations................................... 12
3.4. DDR design recommendations ............................. 12
3.5. Trace impedance recommendations...................... 33
3.6. Power connectivity/routing................................... 35
3.7. USB connectivity.................................................. 37
3.8. HDMI port connectivity (i.MX 8MDQLQ) .......... 38
3.9. PCIE connectivity................................................. 40
3.10. Unused input/output terminations......................... 42
4. Avoiding board bring-up problems.................................. 43
4.1. Introduction........................................................... 43
4.2. Avoiding power pitfalls -Current .......................... 43
4.3. Avoiding power pitfall -Voltage ........................... 43
4.4. Checking for clock pitfalls.................................... 44
4.5. Avoiding reset pitfalls........................................... 45
4.6. Sample board bring-up checklist........................... 45
5. Using BSDL for board-level test...................................... 47
5.1. BSDL overview .................................................... 47
5.2. How BSDL functions............................................ 47
5.3. Downloading BSDL files...................................... 47
5.4. Pin coverage of BSDL .......................................... 47
5.5. Boundary scan operation....................................... 48
5.6. I/O pin power considerations ................................ 48
6. Revision history ............................................................... 49

Overview
i.MX 8MDQLQ Hardware Developer’s Guide, User's Guide, Rev. 2, 06/2019
2 NXP Semiconductors
1.1. Device supported
This Hardware Developer’s Guide supports the i.MX 8MDQLQ (17 x 17 mm package).
1.2. Essential references
This guide is supplementary to the i.MX 8MDQLQ series chip reference manuals and data sheets. For
reflow profile and thermal limits during soldering, see General Soldering Temperature Process
Guidelines (document AN3300). These documents are available on www.nxp.com/i.MX8M.
1.3. Supplementary references
1.3.1. General information
The following documents introduces the Arm®processor architecture and computer architecture.
•For information about the Arm Cortex®-A35 processor, see:
www.arm.com/products/processors/cortex-a/cortex-a35-processor.php
•For information about the Arm Cortex-A53 processor, see:
www.arm.com/products/processors/cortex-a/cortex-a53-processor.php
•For information about the Arm Cortex-A72 processor, see:
www.arm.com/products/processors/cortex-a/cortex-a72-processor.php
•For information about the Arm Cortex-M4F processor, see:
www.arm.com/products/processors/cortex-m/cortex-m4-processor.php
•Computer Architecture: A Quantitative Approach (Fourth Edition) - by John L. Hennessy and
David A. Patterson
•Computer Organization and Design: The Hardware/Software Interface (Second Edition), by David
A. Patterson and John L. Hennessy
The following documentation introduces the high-speed board design:
•Right the First Time- A Practical Handbook on High Speed PCB and System Design - Volumes I
& II - Lee W. Ritchey (Speeding Edge) - ISBN 0-9741936- 0-72
•Signal and Power Integrity Simplified (2nd Edition) - Eric Bogatin (Prentice Hall)- ISBN 0-13-
703502-0
•High Speed Digital Design- A Handbook of Black Magic - Howard W. Johnson & Martin Graham
(Prentice Hall) - ISBN 0-13-395724-1
•High Speed Signal Propagation- Advanced Black Magic - Howard W. Johnson & Martin Graham -
(Prentice Hall) - ISBN 0-13-084408-X
•High Speed Digital System Design- A handbook of Interconnect Theory and Practice - Hall, Hall
and McCall (Wiley Interscience 2000) - ISBN 0-36090-2
•Signal Integrity Issues and Printed Circuit Design - Doug Brooks (Prentice Hall) ISBN 0-13-
141884-X

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NXP Semiconductors 3
•PCB Design for Real-World EMI Control - Bruce R. Archambeault (Kluwer Academic Publishers
Group) - ISBN 1-4020-7130-2
•Digital Design for Interference Specifications - A Practical Handbook for EMI Suppression -David
L. Terrell & R. Kenneth Keenan (Newnes Publishing) - ISBN 0-7506-7282-X
•Electromagnetic Compatibility Engineering - Henry Ott (1st Edition - John Wiley and Sons) -
ISBN 0-471-85068-3
•Introduction to Electromagnetic Compatibility - Clayton R. Paul (John Wiley and Sons) - ISBN
978-0-470-18930-6
•Grounding & Shielding Techniques - Ralph Morrison (5th Edition - John Wiley & Sons) - ISBN 0-
471-24518-6
•EMC for Product Engineers - Tim Williams (Newnes Publishing) - ISBN 0-7506- 2466-3
1.4. Related documentation
Additional literature will be published when new NXP products become available.
For the list of current documents, see www.nxp.com/i.MX8M.
1.5. Conventions
Table 1 lists the notational conventions used in this document.
Table 1. Conventions used in the document
Conventions Description
Courier
Used to indicate commands, command parameters, code examples, and file and directory names.
Italics
Used to indicatescommand or function parameters.
Bold
Function names are written in bold.
cleared/set
When a bit takes the value zero, it means to be cleared; when it takes a value of one, it means to be set.
mnemonics
Instruction mnemonics are shown in lowercase bold. Book titles in text are set in italics.
sig_name
Internal signals are written in all lowercase.
nnnn nnnnh
Denotes hexadecimal number
0b
Denotes binary number
rA, rB
Instruction syntax used to identify a source GPR
rD
Instruction syntax used to identify a destination GPR
REG[FIELD]
Abbreviations for registers are shown in uppercase. Specific bits, fields, or ranges appear in brackets.
For example, MSR[LE] refers to the little-endian mode enable bit in the machine state register.
x
An italicized x indicates an alphanumeric variable.
n, m
An italicized n indicates a numeric variable.
In this guide, notation for all logical, bit-wise, arithmetic, comparison, and assignment operations follow C
Language conventions.

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1.6. Acronyms and abbreviations
Table 2 defines the acronyms and abbreviations used in this document.
Table 2. Definitions and acronyms
Acronym Definition
ArmTM
Advanced RISC Machines processor architecture
BGA
Ball Grid Array package
BOM
Bill of Materials
BSDL
Boundary Scan Description Language
CAN
Flexible Controller Area Network peripheral
CCM
Clock Controller Module
CSI
MIPI Camera Serial Interface
DDR
Dual Data Rate DRAM
DDR3L
Low voltage DDR3 DRAM
DDR4
DDR4 DRAM
DDRC
DDR Controller
DFP
Downstream Facing Port (USB Type-C)
DRP
Dual Role Port (USB Type-C)
ECSPI
Enhanced Configurable SPI peripheral
EIM
External Interface Module
ENET
10/100/1000 Mbps Ethernet MAC peripheral
EPIT
Enhanced Periodic Interrupt Timer peripheral
ESR
Equivalent Series Resistance
GND
Ground
GPC
General Power Controller
GPIO
General Purpose Input/Output
HDCP
High-bandwidth Digital Content Protection
I2C
Inter-integrated Circuit interface
IBIS
Input output Buffer Information Specification
IOMUX
i.MX 8MDQLQ chip-level I/O multiplexing
JTAG
Joint Test Action Group
KPP
Keypad Port Peripheral
LDB
LVDS Display Bridge
LDO
Low Drop-Out regulator
LPCG
Low Power Clock Gating
LPDDR4
Low Power DDR4 DRAM
LVDS
Low-Voltage Differential Signaling
MLB
Media Local Bus
ODT
On-Die Termination
OTP
One-Time Programmable
PCB
Printed Circuit Board
PCIe
PCI Express
PCISig
Peripheral Component Interconnect Special Interest Group
PDN
Power Distribution Network
PMIC
Power Management Integrated Circuit
POR
Power-On Reset
PTH
Plated Through Hole PCB (i.e. no microvias)
RGMII
Reduced Gigabit Media Independent Interface (Ethernet)
RMII
Reduced Media Independent Interface (Ethernet)
ROM
Read-Only Memory

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2. i.MX 8MDQLQ design checklist
This document provides a design checklist for the i.MX 8MDQLQ (17 × 17 mm package) processor.
The design checklist tables recommend optimal design and provide explanations to help users
understand better. All supplemental tables referred by the checklist appear in sections following the
design checklist tables.
2.1. Design checklist table
Table 3. LPDDR4 recommendations (i.MX 8MDQLQ)
Check box Recommendations Explanation/Supplemental recommendations
1. Connect the ZQ ball on the processor (ball AA13)
to individual 240 Ω , 1 % resistors to GND.
This is a reference used during DRAM output
buffer driver calibration.
2. The ZQ0 and ZQ1 balls on LPDDR4 device should
be connected through 240 Ω , 1 % resistors to the
LPDDR4 VDDQ rail.
—
3. Place a 10 kΩ , 5 % resistor to ground on the
DRAM reset signal.
This will ensure adherence to the JEDEC
specification until the control is configured and
starts driving the DDR.
4. The VREF ball on the processor (ball AA14) should
be connected to a voltage level of VDDQ/2.
In LPDDR4 mode, the VREF ball serves as ZQ
calibration.
5. The processor balls AC12 and AE11 should be left
unconnected. The ODT_CA balls on the LPDDR4
device should be connected directly or through a
10 kΩ to the LPDDR4 VDD2 rail.
LPDDR4 ODT on the i.MX 8MDQLQ is
command-based, making processor ODT_CA
output balls unnecessary.
6. The architecture for each chip inside the DRAM
package must be x 16.
The processor does not support byte mode
specified in JESD209-4B.
7. The processor ball MTEST (ball AB14), MTEST1
(ball AC13), should be left unconnected.
These are observability ports for manufacturing
and are not used otherwise.
Table 4. DDR4/DDR3L recommendations (i.MX 8MDQLQ)
Check box Recommendations Explanation/Supplemental recommendations
1. Connect the ZQ ball on the processor (ball AA13)
to individual 240 Ω , 1 % resistors to GND.
This is a reference used during DRAM output
buffer driver calibration.
2. The ZQ ball on each DDR4/DDR3L device should
be connected through individual 240 Ω , 1 %
resistors to GND.
—
3. The VREF ball on the processor (ball AA14) should
be connected to a voltage level of VDDQ/2.
In DDR4 mode, the VREF ball serves as ZQ
calibration.
4. The processor ball MTEST (ball AB14), MTEST1
(ball AC13), should be left unconnected.
These are observability ports for manufacturing
and are not used otherwise.

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Table 5. I2C recommendations
Check box Recommendations Explanation/Supplemental recommendations
1. Verify the target I2C interface clock rates
The I2C bus can only be operated as fast as the
slowest peripheral on the bus. If faster operation
is required, move the slow devices to another
I
2
C port.
2. Verify that there are no I2C address conflicts on any
of the I2C buses utilized
There are multiple I2C ports available on chip,
so if a conflict exists, move one of the conflicting
devices to a different I2C bus. If this isn’t
possible, use a I2C bus switch (NXP part
number PCA9646).
3. Do not place more than one set of pull-up resistors
on the I2C lines.
This could result in excessive loading and
potential incorrect operation. Choose the pull-up
value commensurate with the bus speed being
utilized.
4. Ensure that the VCC rail powering the i.MX
8MDQLQ I2C interface balls matches the supply
voltage used for the pull-up resistors and the slave
I
2
C devices.
Prevent device damage or incorrect operation
due to voltage mismatch.
Table 6. JTAG recommendations
Check box Recommendations Explanation/Supplemental recommendations
1. Do not use external pullup or pulldown resistors on
JTAG_TDO.
JTAG_TDO is configured with an on-chip
keeper circuit and the floating condition is
actively eliminated if an external pull resistor is
not present.
2. Follow the recommendations for external pull-up
and pull-down resistors given in Table 14.
—
3. For normal operation, TEST_MODE (ball V7)
should be pulled down using a 100 KOhm resistor.
To enter boundary-scan mode, this pin should be
pulled up to NVCC_JTAG using a 4.7 KOhm
resistor. Please refer to
COMPLIANCE_PATTERNS in the chip BSDL file.
—
4. To enter boundary-scan mode, GPIO1_IO00,
GPIO1_IO01, GPIO1_IO02 should be pulled down
and GPIO1_IO03, JTAG_nTRST should be pulled
up. Recommended pull resistor value is 4.7 KOhm.
Please refer to COMPLIANCE_PATTERNS in the
chip BSDL file.
—

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Table 7. Reset and ON/OFF recommendations
Check box Recommendations Explanation/Supplemental recommendations
1. The POR_B input must be asserted at power-up
and remain asserted until the last power rail for
devices required for system boot are at their
working voltage. This functionality is controlled by
the PMIC (PF4210) on EVK.
POR_B is driven by the PMIC. If a reset button
is used, it should be connected to the enable
pin of the PMIC and/or other power supply chips
instead of directly connected to POR_B pin of
the CPU. When POR_B is asserted (low) on the
i.MX 8MDQLQ, the output PMIC_ON_REQ
remains asserted (high).
2. For portable applications, the ON_OFF_BUTTON
input may be connected to an ON/OFF SPST push-
button switch to ground. If the On-chip debouncing
is provided, this input has an on-chip pullup.
Otherwise, the ON_OFF_BUTTON should not be
connected.
A brief connection to GND in OFF mode causes
the internal power management state machine
to change state to ON. In ON mode, a brief
connection to GND generates an interrupt
(intended to initiate a software-controllable
power-down). The connection to GND for
approximate 5 second or more causes a forced
OFF.
3. If using WDOG_B(GPIO1_IO02) signal as a reset
source, the signal should be AC coupled to reset
input with a 1uF capacitor.
In boundary-scan mode WDOG_B
(GPIO1_IO02) signal will be pulled down, which
will keep the system in the reset state if DC is
coupled to reset input.
Table 8. i.MX 8MDQLQ power/decoupling recommendations
Check box Recommendations Explanation/Supplemental recommendations
1. Comply with the power-up sequence guidelines as
described in the datasheet to guarantee reliable
operations of the device.
Any deviation from these sequences may result
in the following situations:
•Excessive current during power-up phase
•Prevention of the device from booting
•Irreversible damage to the processor
(worst case)
2. Maximum ripple voltage requirements
Common requirement for ripple noise peak-to-
peak value should be less than 5% of the
supply voltage nominal value.
3. Industrial part and commercial part have different
VDD_SOC operation range
Please refer to IMX8MDQLQIEC and
IMX8MDQLQCEC for details.
Table 9. Decoupling capacity recommendations (i.MX 8MDQLQ)
Checkbox Supply 4.7 nF 0.01 µF 0.1 µF 1 µF 2.2 µF 22 µF Notes
VDD_DRAM 11 2 — 4 — 3
Location of these
capacitors is critical for
effective decoupling.
See layout of EVK for
the optimum location of
these decoupling
capacitors.
NVCC_DRAM
—
—
—
18
—
3
—
VDD_ARM
—
—
—
9
—
3
—
VDD_GPU
—
—
—
7
—
3
—
VDD_VPU
—
—
—
4
—
6
—
VDD_SOC
—
—
—
10
—
3
—

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Table 9. Decoupling capacity recommendations (i.MX 8MDQLQ)
Checkbox Supply 4.7 nF 0.01 µF 0.1 µF 1 µF 2.2 µF 22 µF Notes
VDD_SNVS
—
—
1
—
—
—
—
NVCC_SNVS
—
—
—
1
—
—
—
VDDA_0P9 — — — 1 — —
This rail should be
sourced from the
VDD_SOC rail through
a 240 Ω ferrite bead.
VDDA_DRAM,
VDDA_1P8_XXX
— — 6 — — 1 —
NVCC_JTAG,
NVCC_NAND,
NVCC_SAI1,
NVCC_SAI2,
NVCC_SAI3,
NVCC_SAI5,
NVCC_GPIO1,
NVCC_I2C,
NVCC_UART,
NVCC_ECSPI
— — 9 — — — —
NVCC_SD1
—
—
1
—
—
—
—
NVCC_SD2
—
—
1
—
—
—
—
NVCC_ENET
—
—
1
—
—
—
—
USB1_VDD33,
USB1_VPH,
USB2_VDD33,
USB2_VPH
— — 2 — 1 — —
USB1_VPTX,
USB1_VP,
USB1_DVDD,
USB2_VPTX,
USB2_VP,
USB2_DVDD
— — 2 — 1 — —
PCIE_VPH
—
—
1
—
1
—
—
PCIE_VPTX,
PCIE_VP
— — 2 — 1 — —
HDMI_AVDDIO
—
—
1
—
1
—
—
HDMI_AVDDCLK,
HDMI_AVDDCORE
— — 2 — 1 — —
MIPI_VDDHA
—
—
1
—
1
—
—
MIPI_VDDA,
MIPI_VDDPLL
— — 3 — 1 — —
MIPI_VDD — — 2 — — —
MIPI_VDD and
MIPI_VDDA can share
the same source.
MIPI_VDD should be
isolated with a 120 Ω
ferrite bead.

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Table 9. Decoupling capacity recommendations (i.MX 8MDQLQ)
Checkbox Supply 4.7 nF 0.01 µF 0.1 µF 1 µF 2.2 µF 22 µF Notes
Capacitor part number used on EVK:
•4.7 nF --- GRM033R61A472KA01D
•0.01 uF --- GRM033R70J103KA01D
•0.1 uF --- 0201X104K100CT
•1 uF --- 02016D105MAT2A
•2.2 uF --- C1005X5R1A225K
•22 uF --- C1608X5R1A226M080AC
Table 10. PCIe recommendations
Check box Recommendations Explanation/Supplemental recommendations
1. Use an appropriate PCIe
reference clock generator.
The NXP EVK board design uses an IDT 9FGV0241 device.
However, NXP does not recommend one supplier over another,
and does not suggest that this is the only clock generator supplier.
The device used should support all the specs (jitter, accuracy,
etc.).
2. The differential transmitters from
the processor must be AC
coupled. Use a 0.1 µF cap on
both the PCIE_TXP and
PCIE_TXN outputs
PCIe specification compliance requires AC coupling at each
transmitter. The receiver must be DC coupled.
3. The PCIEx_RESREF ball (ball
G25 and C25) should be
connected to the ground through
a 200 Ω , 1 % resistor.
—
Table 11. USB recommendations
Check box Recommendations Explanation/Supplemental recommendations
1. Connect a 200 Ω , 1 % resistor to the ground on the
USBx_RESREF ball (ball A11 and B11).
—
2. Route all USB differential signals with 90 Ω
differential impedance.
—
3. ESD protection should be implemented at the
connector pins. Choose a low capacitance device
recommended for high-speed interfaces.
This will prevent potential damages to board
components from ESD.
Table 12. HDMI recommendations
Check box Recommendations Explanation/Supplemental recommendations
1. Connect a 499 Ω , 1 % resistor to ground on the
HDMI_REXT ball (ball P1).
—
2. Route all HDMI differential pairs with 100 Ω
differential impedance.
—

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Table 13. Oscillator/Crystal recommendations
Check box Recommendations Explanation/Supplemental recommendations
1. Connect a 25 MHz
crystal between
XTALI_25M and
XTALO_25 M (balls U24
and U25).
A 100 Ωtypical ESR and 8 pF CL crystal rated for a maximum drive level
of 200 μW is acceptable. Consult crystal vendor and do matching test for
designing external compensation capacitors is preferred. Use short traces
between the crystal and the processor, with a ground plane under the
crystal, load capacitors, and associated traces.
2. Connect a 27 MHz
crystal between
XTALI_27M and
XTALO_27M (balls V24
and V25).
A 100 Ωtypical ESR and 8 pF CL crystal rated for a maximum drive level
of 200 μW is acceptable. Consult crystal vendor and do matching test for
designing external compensation capacitors is preferred. Use short traces
between the crystal and the processor, with a ground plane under the
crystal, load capacitors, and associated traces.
3. The i.MX 8MDQLQ
32.768 kHz needs to be
driven with an external
clock (oscillator) into the
RTC input (ball V22).
The voltage level of this driving clock should not exceed the voltage of the
NVCC_SNVS rail and the frequency should be less than 100 kHz. Do not
exceed NVCC_SNVS, or the damage/malfunction may occur. The RTC
signal should not be driven if the NVCC_SNVS supply is OFF. It can lead
to damage or malfunction. For RTC VIL and VIH voltage levels, see the
latest i.MX 8MDQLQ datasheet available at www.nxp.com/i.MX8M.
2.2. JTAG signal termination
Table 14 is a JTAG termination chart showing what terminations should be placed on PCB designs.
Table 14. Recommended JTAG board terminations
JTAG signal I/O type External termination Comments
JTAG_TCK
Input
10 kΩ pull-down
—
JTAG_TMS
Input
None
Internal pulled up to NVCC_JTAG, no
external termination required.
JTAG_TDI
Input
None
Internal pulled up to NVCC_JTAG, no
external termination required.
JTAG_TDO
3-state output
None
—
JTAG_TRSTB
Input
4.7 kΩ pull-up
In normal operation, this pin is internally
pulled-up to NVCC_JTAG. But in boundary-
scan mode, this pin is floating. An external
pull-up resistor is required for boundary-
scan mode.

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3. i.MX 8MDQLQ layout/routing recommendations
3.1. Introduction
This chapter introduces how to assist design engineers with the layout of an i.MX 8MDQLQ-based
system.
3.2. Basic design recommendations
When using the Allegro design tool, the schematic symbol & PCB footprint created by NXP is
recommended. When not using the Allegro tool, use the Allegro footprint export feature (supported by
many tools). If the export is not possible, create the footprint per the package dimensions outlined in the
product data sheet.
Native Allegro layout and gerber files are available on www.nxp.com/i.MX8M.
3.2.1. Placing decoupling capacitors
Place small decoupling and larger bulk capacitors on the bottom side of the PCB.
The 0201 or 0402 decoupling and 0603 or larger bulk capacitors should be mounted as close as possible
to the power vias. The distance should be less than 50 mils. Additional bulk capacitors can be placed
near the edge of the BGA via array. Placing the decoupling capacitors close to the power balls is critical
to minimize inductance and ensure high-speed transient current required by the processor. See the i.MX
8MDQLQ EVK layouts for examples of the desired decoupling capacitor placement.
The following list introduces how to choose correct decoupling scheme:
•Place the largest capacitance in the smallest package that budget and manufacturing can support.
•For high speed bypassing, select the required capacitance with the smallest package (for
example, 0.1 μF, 0.22 μF, 1.0 μF, or even 2.2 μF in a 0201 package size).
•Minimize trace length (inductance) to small caps.
•Series inductance cancels out capacitance.
•Tie caps to GND plane directly with a via.
•Place capacitors close to the power ball of the associated package from the schematic.
•A preferred BGA power decoupling design is available on the EVK board design available on
www.nxp.com/i.MX8M. Customers should use the NXP design strategy for power and
decoupling.

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3.3. Stack-up recommendations
3.3.1. Stack-up recommendation (i.MX 8MDQLQ)
Due to the number of balls on the i.MX 8MDQLQ processor in the 17 mm × 17 mm package, a
minimum 8-layer PCB stackup is recommended. Of the 8-layers on the PCB, a sufficient number of
layers need to be dedicated to power on routing to meet the IR drop target of 1 % for the i.MX
8MDQLQ CPU power rails.
The constraints for the trace width will depend on such factors as the board stackup and associated
dielectric and copper thickness, required impedance, and required current (for power traces). The
stackup also determines the constraints for routing and spacing. Consider the following requirements
when designing the stackup and selecting board material:
•Board stack-up is critical for high-speed signal quality.
•Preplanning impedance of critical traces is required.
•High-speed signals must have reference planes on adjacent layers to minimize cross-talk.
•PCB material: the material used on EVK is TU768.
3.4. DDR design recommendations
3.4.1. DDR connection information
The i.MX 8MDQLQ processor can be used with LPDDR4, DDR4 or DDR3L memory. Since these
memory types have different I/O signals, there are 37 generically-named functional balls, depending on
the type of memory used. See Table 15 for the connectivity of these generic balls for DDR3L, LPDDR4
and DDR4. The schematic symbol created by NXP already replaced these generic names with DDR
function.
Table 15. DDR3L/LPDDR4/DDR4 connectivity
Ball name Ball # LPDD4 function DDR4 function DDR3L function
DRAM_AC00
AC16
CKE0_A
CKE0
CKE0
DRAM_AC01
AE17
CKE1_A
CKE1
CKE1
DRAM_AC02
AE18
CS0_A
CS0_n
CS0#
DRAM_AC03
AC18
CS1_A
C0
—
DRAM_AC04
AD14
CK_t_A
BG0
BA2
DRAM_AC05
AE14
CK_c_A
BG1
A14
DRAM_AC06
AE13
—
ACT_n
A15
DRAM_AC07
AB15
—
A9
A9
DRAM_AC08
AD17
CA0_A
A12
A12/BC#
DRAM_AC09
AE16
CA1_A
A11
A11
DRAM_AC10
AD20
CA2_A
A7
A7
DRAM_AC11
AE20
CA3_A
A8
A8
DRAM_AC12
AD19
CA4_A
A6
A6
DRAM_AC13
AE19
CA5_A
A5
A5
DRAM_AC14
AB16
—
A4
A4
DRAM_AC15
AC15
—
A3
A3
DRAM_AC16
AE15
—
CK_t_A
CK_A

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NXP Semiconductors 13
Table 15. DDR3L/LPDDR4/DDR4 connectivity
Ball name Ball # LPDD4 function DDR4 function DDR3L function
DRAM_AC17
AD15
—
CK_c_A
CK#_A
DRAM_AC19
AB14
MTEST
MTEST
MTEST
DRAM_AC20
AD10
CKE0_B
CK_t_B
CK_B
DRAM_AC21
AE10
CKE1_B
CK_c_B
CK#_B
DRAM_AC22
AD8
CS1_B
—
—
DRAM_AC23
AC9
CS0_B
—
—
DRAM_AC24
AD12
CK_t_B
A2
A2
DRAM_AC25
AE12
CK_c_B
A1
A1
DRAM_AC26
AB12
—
BA1
BA1
DRAM_AC27
AA12
—
PARITY
—
DRAM_AC28
AC7
CA2_B
A13
A13
DRAM_AC29
AE7
CA3_B
BA0
BA0
DRAM_AC30
AE6
CA4_B
A10 / AP
A10 / AP
DRAM_AC31
AD6
CA5_B
A0
A0
DRAM_AC32
AE8
CA0_B
C2
—
DRAM_AC33
AE9
CA1_B
CAS_n/A15
CAS#
DRAM_AC34
AC10
—
WE_n A14
WE#
DRAM_AC35
AB10
—
RAS_n/A16
RAS#
DRAM_AC36
AC12
—
ODT0
ODT0
DRAM_AC37
AE11
—
ODT1
ODT1
DRAM_AC38
AC11
—
CS1_n
CS1#
3.4.2. LPDDR4-3200 design recommendations
The following list details some generic guidelines that should be adhered to when implementing an
i.MX 8MDQLQ design using LPDDR4.
1. It is expected that the layout engineer and design team already has experience and training with
DDR designs at speeds of 1.6 GHz/3200 MT/s.
2. Refer to solid GND plane only for all the high-speed signal traces. If referring to both GND and
NVCC_DRAM (VDDQ) plane, make sure the dielectric thickness between trace and NVCC_DRAM
plane is larger than that between trace and GND plane. Do not refer to other power planes.
3. The impedance of DQ and DMI signal traces should be controlled to 42 Ω instead of 50 Ω to
maximize the timing margin at 3200 MT/s.
4. The DQ/DMI/DQS signals must be routed in inner layers as stripline or embedded microstrip and
follow 3W rule(center to center) to minimize trace crosstalk.
5. At a speed of 3200 MT/s, signal vias can be a significant source of crosstalk. If not properly
designed, it can introduce crosstalk larger than that from the trace. To minimize via crosstalk, make
sure the total number of vias to be two or less on each point-to-point single-ended/differential trace.
Place at least one ground stitching via within 40 mils of signal via when switching reference planes
to provide continuous return path and reduce crosstalk. If it is not possible to place enough ground
stitching vias due to space limitation, try to make the length that the signal actually travels on the via
as short as possible, as illustrated in Figure 1.

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14 NXP Semiconductors
Figure 1. Length that the signal actually travels on the Via
6. Route the CLK signal on top layer with no via transition and keep over than 5 W spacing from other
signals.
7. DQS and DMI with the same slice should have the same number of vias/layer changes.
8. Use time delay instead of length when performing the delay matching. The delay matching includes
the PCB trace delay and the IC package delay. Incorporate the package pin delay into the CAD
tool’s constraint manager.
9. Include the delay of vias when performing delay matching. This can be realized in Allegro tool by
enabling the Z Axis Delay in Setup -> Constraints -> Modes.
10. Byte swapping within each 16-bit channel is OK. Bit swapping within each slice/byte lane is OK.
11. Bit swapping of Command/Address (CA[5:0]) signals is NOT allowed.
12. For an i.MX 8MDQLQ design, DRAM_AC14 and DRAM_AC34 on the processor must be left
unconnected if using LPDDR4. The ODT_CA balls on the LPDDR4 devices should be connected
directly or through a resistor to the VDD2 supply.
13. In general, the 200-ball LPDDR4 package should be placed 100 mils from the i.MX 8MDQLQ.
14. Enable the DBI (data bus inversion) feature. It can help reduce both power consumption and power
noise.
3.4.2.1. i.MX 8MDQLQ LPDDR4-3200 routing recommendations
LPDDR4-3200 needs to be routed with signal fly times matched shown in Table 16. The delay of the via
transitions needs to be included in the overall calculation. This can be realized in Allegro tool by
enabling the Z Axis Delay in Setup -> Constraints -> Modes.
An example of the delay match calculation has been shown for the i.MX 8MDQLQ EVK board design
in Table 17 and Table 18. This analysis was done for the LPDDR4-3200 implementation using the i.MX
8MDQLQ. In Table 17, the PCB Delay column was obtained directly from the Allegro PCB file, and
the Pkg Delay column is the package delay obtained from Table 24.

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NXP Semiconductors 15
NXP recommends that users simulate their LPDDR4 implementation before fabricating PCBs.
Table 16.
i.MX 8MDQLQ LPDDR4-3200 routing recommendations
LPDDR4-3200
LPDDR4 signal (each
16-bit channel)
Group PCB + package prop delay
Min Max Considerations
CK_t/CK_c Clock Short as possible 175 ps
Match the
true/complement
signals within 1 ps.
CA[5:0]
Address/Command/Control CK_t - 25 ps CK_t + 25 ps —
CS[1:0]
CKE[1:0]
DQS0_t/DQS0_c
Byte 0 - DQS
CK_t - 85 ps
CK_t + 85 ps
Match the
true/complement
signals of DQS within 1
ps.
DM0
Byte 0 - Data DQS0_t -10 ps DQS0_t +10 ps
DQ[7:0]
DQS1_t/DQS1_c
Byte 1 - DQS
CK_t - 85 ps
CK_t + 85 ps
DM1
Byte 1 - Data DQS1_t -10 ps DQS1_t +10 ps
DQ[15:8]
Table 17. LPDDR4 delay matching example (CA/CTL signals)
Net name PCB delay (ps) Pkg delay (ps) Comments
DRAM_CK_T_A
106.6
42.7
Routed on top layer, no via
149.3
Total Net Delay
DRAM_CK_C_A
107.1
41.5
Routed on top layer, no via
148.6
Total Net Delay
DRAM_CA0_A
105.0
49.8
Vias are L1-> L8->L1
154.8
Total Net Delay
DRAM_CA1_A
85.1
73.5
Vias are L1-> L8->L1
158.6
Total Net Delay
DRAM_CA2_A
106.6
51.2
Vias are L1-> L8->L1
157.8
Total Net Delay
DRAM_CA3_A
106.2
52.6
Vias are L1-> L8->L1
158.8
Total Net Delay
DRAM_CA4_A
111.8
58.6
Vias are L1-> L8->L1
170.4
Total Net Delay
DRAM_CA5_A
105.7
56.2
Vias are L1-> L8->L1
161.9
Total Net Delay
DRAM_nCS0_A
106.6
51.0
Vias are L1-> L8->L1
157.6
Total Net Delay
DRAM_nCS1_A
108.1
47.8
Vias are L1-> L8->L1
155.9
Total Net Delay
DRAM_CKE0_A
121.1
36.5
Vias are L1-> L8->L1
157.6
Total Net Delay
DRAM_CKE1_A
106.1
47.4
Vias are L1-> L8->L1
153.5
Total Net Delay

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Table 18. LPDDR4 length matching example (byte lane 1 signals)
Net name PCB delay (ps) Pkg delay (ps) Comments
DRAM_SDQS1_T_A
180.1
45.2
Vias are L1-> L4->L1
225.3
Total Net Delay
DRAM_SDQS1_C_A
179.5
45.3
Vias are L1-> L4->L1
224.8
Total Net Delay
DRAM_DMI1_A
180.2
43.4
Vias are L1-> L4->L1
223.6
Total Net Delay
DRAM_DATA8_A
179.1
44.2
Vias are L1-> L4->L1
223.3
Total Net Delay
DRAM_DATA9_A
182.7
46.5
Vias are L1-> L4->L1
229.2
Total Net Delay
DRAM_DATA10_A
175.5
53.8
Vias are L1-> L4->L1
229.3
Total Net Delay
DRAM_DATA11_A
185.9
43.5
Vias are L1-> L4->L1
229.4
Total Net Delay
DRAM_DATA12_A
179.1
44.9
Vias are L1-> L4->L1
224.0
Total Net Delay
DRAM_DATA13_A
182.0
45.0
Vias are L1-> L4->L1
227.0
Total Net Delay
DRAM_DATA14_A
188.0
35.3
Vias are L1-> L4->L1
223.3
Total Net Delay
DRAM_DATA15_A
184.3
40.4
Vias are L1-> L4->L1
224.7
Total Net Delay
3.4.2.2. LPDDR4-3200 routing example (i.MX 8MDQLQ)
Figure 2 to Figure 5 show the placement and routing of the LPDDR4 signals on the i.MX 8MDQLQ
EVK board. The CLK signals are routed on top layer with no via to achieve the best signal quality. Data
byte lane 1 signals are routed on layer 4 to make the length that the signal actually travels on the via as
short as possible, as limited number of GND vias can be placed near these signal vias. Data byte lane 0
signals are routed on layer 6. CA/CTL signals are routed on layer 8 as their data rate is only half of the
data signals, and CA/CTL has more tolerance for crosstalk.

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NXP Semiconductors 17
Figure 2. i.MX 8MDQLQ EVK board LPDDR4 routing (top layer)
Figure 3. i.MX 8MDQLQ EVK board LPDDR4 routing (Layer 4)

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Figure 4. i.MX 8MDQLQ EVK board LPDDR4 routing (Layer 6)
Figure 5. i.MX 8MDQLQ EVK board LPDDR4 routing (Layer 8)

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3.4.2.3. LPDDR4-3200 SI simulation guide
The simulation architecture includes the DDR controller (i.e. the i.MX 8MDQLQ processor), the PCB
and the LPDDR4 device. The IBIS model for the i.MX 8MDQLQ processor is available from NXP. The
LPDDR4 device IBIS model must be obtained from the memory vendor.
This section introduces how to check SI performance of the layout for an LPDDR4-3200 design using
the i.MX 8MDQLQ.
•Firstly, perform S-parameter extraction:
—It requires a 2.5D full-wave extraction tool, such as PowerSI from Cadence.
—Set the extraction bandwidth to 20 GHz.
—Port reference impedance: 50 Ω for signal ports, and 0.1 Ω for power ports.
—Coupled mode: Set the rise time to 20 ps and coupling coefficient to 1 %.
•Secondly, perform time domain simulation:
—Stimulus pattern: 500-bit random code and different pattern for each signal within the
same byte.
—Ideal power.
—Probe at the die.
—Simulation at slow corner (worst case).
—Eye waveform triggered by aligning with the timing reference (DQS/CLK).
3.4.2.4. Eye width requirement
The simulated worst eye width should meet following requirements:
•DQ Write: Eye width @VREF ±70 mV should be over 221 ps.
•CA/CTL: Eye width @VREF ±77.5 mV should be over 380 ps.
Figure 6 shows an example of simulated eye width of DQ write.
Figure 6. Example of simulated eye width

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20 NXP Semiconductors
3.4.3. i.MX 8MDQLQ DDR4-2400/DDR3L-1600 design recommendations
The following lists details some generic guidelines that should be adhered to when implementing an
i.MX 8MDQLQ design using DDR4/DDR3L.
1. Use a T PCB routing topology for a 2-rank system. Mount a rank of SDRAM on both top and
bottom of the board, mirroring in a clamshell design for highest performance.
Figure 7. PCB routing topology for a 2-rank system
2. As illustrated in Figure 7, for data bytes, route straight from SOC to the SDRAM devices and via up
and down with minimal stubs. For address/command signals, it is a T structure with branch to the
SDRAM devices and via up and down with minimal stubs. And add a parallel termination (about 65
Ωto VDDQ/2 or VTT) at the branch point of the T.
3. The branch and stubs to the SDRAM pins must be the same length on both sides of the branch point
(A+C=B+D); otherwise, the signal will show significant distortion. Also try to minimize length of
branch as it is un-terminated at the SDRAM devices.
4. The impedance of DQ& DMI & the trunk of address/command signal traces should be controlled to
40 Ω instead of 50 Ω to maximize the timing margin.
5. All data signals within a byte lane should have the same number of vias/layer changes.
6. All the high-speed signal traces must be referred to solid GND or NVCC_DRAM (VDDQ) plane.
Do not refer to other power planes.
7. For DQ nets, bit swapping within each slice/byte lane is OK.
8. For Address nets, use address mirroring to minimize top to bottom stubs. i.MX 8MDQLQ supports
address mirroring but the wiring from i.MX 8MDQLQ to the two DRAM ranks must conform to
Table 19 and Table 20, for DDR4 and DDR3L respectively.