NXP Semiconductors QorIQ T2080 User manual

QorIQ T2080 Reference Design Board
(T2080RDB-PC) User Guide
NXP Semiconductors Document identifier: T2080RDBPCUG
User Guide Rev. 1, 08/2021

Contents
Chapter 1 Overview............................................................................................... 4
1.1 Related documentation..............................................................................................................4
1.2 Acronyms and abbreviations..................................................................................................... 4
1.3 T2080 silicon features............................................................................................................... 5
1.4 T2080RDB-PC board features.................................................................................................. 6
1.5 Block diagram............................................................................................................................8
Chapter 2 Architecture ........................................................................................ 10
2.1 Processor................................................................................................................................ 10
2.2 Power...................................................................................................................................... 10
2.3 Reset....................................................................................................................................... 11
2.4 Clocks......................................................................................................................................12
2.5 DDR.........................................................................................................................................13
2.6 SerDes port............................................................................................................................. 14
2.6.1 PCI Express support................................................................................................................. 15
2.6.2 XFI 10G optics port support...................................................................................................... 15
2.6.3 XFI 10GBase-T port support..................................................................................................... 16
2.6.4 SATA support............................................................................................................................16
2.7 Ethernet controllers ................................................................................................................ 16
2.8 Ethernet Management Interface..............................................................................................17
2.9 I2C...........................................................................................................................................18
2.10 SPI interface .........................................................................................................................19
2.11 Local bus............................................................................................................................... 19
2.12 SDHC interface......................................................................................................................19
2.13 USB interface........................................................................................................................ 20
2.14 RS-232.................................................................................................................................. 21
2.15 JTAG/COP port..................................................................................................................... 22
2.16 Connectors, Headers, Jumper, Push buttons, and LEDs......................................................24
2.16.1 Connectors..............................................................................................................................24
2.16.2 Headers...................................................................................................................................25
2.16.3 Jumper.................................................................................................................................... 25
2.16.4 Push buttons........................................................................................................................... 25
2.16.5 LEDs....................................................................................................................................... 25
2.17 Temperature..........................................................................................................................26
2.18 DIP switch definition.............................................................................................................. 27
Chapter 3 CPLD Specification............................................................................. 30
3.1 Register descriptions...............................................................................................................30
3.1.1 CPLD Memory map...................................................................................................................30
3.1.2 Chip ID1 register (CHIPID1)......................................................................................................30
3.1.3 Chip ID2 register (CHIPID2)......................................................................................................31
3.1.4 Hardware version register (HWVER)........................................................................................ 31
3.1.5 Software version register (SWVER)..........................................................................................32
3.1.6 Reset control register (RSTCON)............................................................................................. 33
3.1.7 Flash control and status register (FLHCSR)............................................................................. 34
3.1.8 Thermal control and status register (THMCSR)........................................................................35
3.1.9 Panel LED control and status register (LEDCSR).....................................................................36
3.1.10 SFP+ control and status register (SFPCSR)...........................................................................37
3.1.11 Miscellanies control and status register (MISCCSR).............................................................. 38
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3.1.12 Boot configuration override register (BOOTOR)..................................................................... 39
3.1.13 Boot configuration register 1 (BOOTCFG1)............................................................................ 39
3.1.14 Boot configuration register 2 (BOOTCFG2)............................................................................ 40
Appendix A Revision history................................................................................ 42
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Contents
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Chapter 1
Overview
The T2080RDB-PC is a high-performance computing evaluation, development, and test platform supporting the T2080 QorIQ®
Power Architecture® processor. The T2080RDB-PC is optimized to support the high-bandwidth DDR3L memory and a full
complement of high-speed SerDes ports. This system has two working modes, the Standalone mode and the PCIe Endpoint
mode. The motherboard, inside the T2080RDB-PC, is a PCIe form factor card and it is installed in a custom 1U chassis. The
system is in standalone mode by default and you can remove the PCIe from its chassis for PCIe Endpoint mode operation.
The T2080RDB boards are using NXP C29x Crypto Coprocessor series silicon.
NOTE
1.1 Related documentation
The table below lists the related documentation:
Table 1. Related documentation
Document name Description
QorIQ T2080
Reference Manual
This document provides a detail description on the T2080 QorIQ multicore processor and on some of its
features such as memory map, serial interfaces, power supply, chip features, and clock information.
T2080
Product Brief
This document provides an overview of the NXP T2080 features and examples of the T2080 usage.
QorIQ T2080
Data Sheet
This document contains the T2080 information on pin assignments, electrical characteristics, hardware
design, considerations, package information, and ordering information.
Some of the documents mentioned above may be available only under a non-disclosure agreement (NDA). To
request access to these documents, contact your local field applications engineer or sales representative.
NOTE
1.2 Acronyms and abbreviations
Table 2. Acronyms and abbreviations
Usage Description
COP Common On-chip Processor
CPC CoreNet Platform Cache
CPLD Complex Programmable Logic Device
DIMM Dual In-Line Memory Module
DIP Dual In-Line Package
DMA Direct Memory Access
DPAA Data Path Acceleration Architecture
DRAM Dynamic Random Access Memory
DUT Device Under Test
Table continues on the next page...
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Table 2. Acronyms and abbreviations (continued)
Usage Description
EC Ethernet Controllers
ECC Error Detection and Correction
EMI Ethernet Management Interfaces
eSDHC enhanced Secure Digital Host Controller
eSPI enhanced Serial Peripheral Interface
FPGA Field-Programmable Gate Array
HW Hardware
I2C Inter - Integrated Circuit
IFC Integrated Flash Controller
JTAG Joint Test Action Group
PCIe/PEX PCIe = PCI Express = PEX
PLD Programmable Logic Device
POR Power-on Reset
QMan Queue Manager
SATA Serial Advanced Technology Attachment
SD Secure Digital
SerDes Serializer/Deserializer
SGMII Serial Gigabit Media Independent Interface
SPI Serial Peripheral Interface
SW Switch
SYSCLK System Clock
UART Universal Asynchronous Receiver/Transmitter
VCC Voltage for Circuit
VTT Voltage for Terminal
1.3 T2080 silicon features
The T2080 silicon features are as follows:
• Four e6500 cores, built on Power Architecture technology, sharing a 2 MB L2 cache
• 512 kB CoreNet Platform cache (CPC)
• Hierarchical interconnect fabric:
— CoreNet fabric supporting coherent and non-coherent transactions with prioritization and bandwidth allocation among
CoreNet endpoints
— Queue Manager (QMan) fabric supporting packet-level queue management and quality of service scheduling
• One 32/64-bit DDR3 SDRAM memory controller:
— DDR3 and DDR3L with ECC and interleaving support
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— Memory pre-fetch engine
• Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions:
— Packet parsing, classification, and distribution (Frame Manager 1.1)
— Queue management for scheduling, packet sequencing, and congestion management (Queue Manager 1.1)
— Hardware buffer management for buffer allocation and de-allocation (Buffer Manager 1.1)
— Cryptography Acceleration (SEC 5.2)
— RegEx Pattern Matching Acceleration (PME 2.1)
— Decompression/Compression Acceleration (DCE 1.0)
— DPAA chip-to-chip interconnect, using RapidIO Message Manager (RMan 1.0)
• 16 SerDes lanes at up to 10 GHz.
• Eight Ethernet interfaces, supporting combinations of:
— Up to four 10 Gbit/s Ethernet MACs
— Up to eight 1 Gbit/s Ethernet MACs
— Up to four 2.5 Gbit/s Ethernet MACs
— IEEE 1588 standard support.
• High-speed peripheral interfaces:
— Four PCI Express controllers (two supporting PCIe 2.0 and two supporting PCIe 3.0)
— Two Serial RapidIO 2.0 controllers running at up to 5 GHz with Type 11 messaging and Type 9 data streaming support
• Additional peripheral interfaces:
— Two Serial ATA (SATA 2.0) controllers
— Two high-speed USB 2.0 controllers with integrated PHY
— Enhanced secure digital host controller (SD/MMC/eMMC)
— Enhanced Serial peripheral interface (eSPI)
— Four I2C controllers
— Four 2-pin UARTs or two 4-pin UARTs
— Integrated flash controller supporting NAND and NOR flash
• Three 8-channel DMA engines
• 896 FC-PBGA package, 25 mm x 25 mm, 0.8 mm pitch
1.4 T2080RDB-PC board features
The T2080RDB-PC board features are as follows:
• SerDes connections
— 16 lanes configuration:
◦ SerDes-1 Lane A-B: to two 10GSFP+ (MAC9 and MAC10)
◦ SerDes-1 Lane C-D: to two 10GBase-T (MAC1 and MAC2)
◦ SerDes-1 Lane E-H: to PCIe slot (PCIe4 x4, Gen3)
◦ SerDes-2 Lane A-D: to PCIe Goldfinger (PCIe1 x4, Gen2)
◦ SerDes-2 Lane E-F: to C293 secure coprocessor (PCIe2 x2)
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◦ SerDes-2 Lane G-H: to SATA1 and SATA2
• DDR controller
— Supports data rates of up to 1600 MHz or 1866 MHz
— Supports one DDR3L DIMM of single, dual-rank types
— DDR power supplies 1.35 V to all devices with automatic tracking of VTT
• IFC/Local Bus
— NAND flash: 8 bit, async, up to 1 GB
— NOR: 16 bit, non-multiplexed, up to 128 MB, NOR devices support 8 virtual banks
• Ethernet
— Two onboard RGMII 10/100/1G Ethernet ports
— Two onboard XFI 10GEDC for 10G SFP+ port
— Two onboard XFI 10GBase-T ports
• CPLD
— PCBA version identify
— Manages system power and reset sequencing
— Configures DUT, board, clock with dynamic
— Reset and interrupt monitor and control
— General fault monitoring and logging
• Clocks
— System and DDR clock (SYSCLK, DDRCLK)
◦ Switch selectable to one of the 16 common settings in the interval 64 MHz-166 MHz
◦ Software programmable in 1 MHz increments from 1-200 MHz
— SerDes clocks
◦ Provides clocks to all SerDes blocks and slots
◦ 100 MHz
◦ 156.25 MHz
• Power supplies
— Dedicated PMBus regulator for core power; adjustable from 0.7 V to 1.3 V at 60 A
• USB
— Supports two USB 2.0 ports with integrated PHYs: Two type A ports with 5 V @ 1.5 A per port
• MicroSD card
— MicroSD port connects directly to MicroSD or TF
• SPI
— Onboard support of SPI flash
• Other I/O
— Two serial ports
— Two I2C ports
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1.5 Block diagram
The T2080RDB-PC supports two modes of operation, the Standalone mode and the Endpoint mode. There is one configuration
in the Standalone mode and second configurations is in the Endpoint mode, the major differences are in the PCIe support. All
configurations have NXP C293, 4x XFI, 2x RGMII, DDR, NOR, NAND, SPI EEPROM, I2C EEPROM, and GPIO. FPGA/CPLD
controls the muxing.
DMAx3
Power architecture
e6500
Power architecture
e6500
Power architecture
e6500
32 KB
D-Cache
2 MB Banked L2
Pre-Fetch
512 KB
Plat cache
64-bit DDR3/3L
with ECC
MPIC
Preboot loader
Security monitor
Internal bootROM
Power mgmt
SDXC/eMMC
eSPI
2 x DUART
4x I2C
2 x USB2.0 w/PHY
Clocks/reset
DCE RMan
PME BMan
SEC QMan
PAMU PAMU
CoreNet
coherency fabric
PAMU (peripheral access management unit)
FMan
Parse, classify,
distribute
Buffer
HiGig DCB
8 lanes up to 10 GHz SerDes
PCle
SATA2.0
Perf
Monitor
Watch point
cross-
trigger
Aurora
Real-time
debug
32 KB
I-Cache
32 KB
D-Cache
32 KB
I-Cache
32 KB
D-Cache
32 KB
I-Cache
32 KB
D-Cache
32 KB
I-Cache
PCle PCle PCle
sRIO
SATA2.0
sRIO
8 lanes up to 8 GHz SerDes
CoreNet
trace
4x 1/2.5/1OG
1GE 1GE
1GE 1GE
GPIO
CCSR
IFC
Power architecture
e6500
Figure 1. T2080 block diagram
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Overview
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Clocks, POR, Reset, and
Power supply circuit
USB Conn *2
USB Type A x 2
SFI
SFI XFI
XFI
CS4315
(XFI>SFI)
MDI
Transformer
RJ45
PCle x4
PCle x4 slot
Golden finger
C293
coprocessor
SATA*2
SATA_conn
X2
Magnetic
(GSTS009LF)
RTL8211E-VB
(RGMII->Copper)
RGMII
RJ45
X2
Magnetic
(GSTS009LF)
RTL8211E-VB
(RGMII->Copper)
RGMII
MAX3232
TXD,RXD,RTS,CTS
TXD,RXD,RTS,CTS
RJ45
RJ45
Local Bus (16bit)
Local Bus (8bit)
SPI Bus
SDHC Bus Micro SD card
SPI FLASH
N25Q512A13GSF40F
(64MB)
NAND FLASH
MT29F8G08ABABAWP-12IT
(1GB)
NOR FLASH
S29GL01GP11TFIV10
(128MB)
CPLD
(EPM570G)
PCA9546
Address:0x77
I2C2_PEX4S
NOT USE
I2C2_SFP2
I2C2_SFP1
RESET
Interrupt
Power-on conf
Other control
Address:0x63
Address:0x6A
Address:0x88
I2C_1
Address:0x40
Address:0x50
Battery Backup
RTC(DS1339U)
Temp Sensor
(ADT7481)
I2C EEPROM
(AT24C256)
Clock generator
(IDT9FGV0641)
Power regulator
1.8 GHz, DDR3L/72bit 4GB
(SODIMM)
SPD Address:0x51
DDR3L 72bit
COP
USB2.0SerDes1
I2C_1 DDR3
I2C_2
SerDes 2
RGMII
IFC
DUART
SPI
SDHC
T2080
SFP+ 10G
Optics module
SFP+ 10G
Optics module
JTAG
XFI
XFI
MDI
Transformer
RJ45
PCle x4
PCle x2
MAX3232
10G Base-T PHY
AQR113C
10G Base-T PHY
AQR113C
(LTC3882)
Figure 2. T2080RDB-PC architecture
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Chapter 2
Architecture
This section explains the architecture of T2080RDB-PC:
•Processor
•Power
•Reset
•Clocks
•DDR
•SerDes port
•Ethernet controllers
•Ethernet Management Interface
•I2C
•SPI interface
•Local bus
•SDHC interface
•USB interface
•RS-232
•JTAG/COP port
•Connectors, Headers, Jumper, Push buttons, and LEDs
•Temperature
•DIP switch definition
2.1 Processor
The T2080RDB-PC supports many features of the T2080 processor, as detailed in the following sections.
2.2 Power
The power supply system of the T2080RDB-PC system uses power from a standard 6-pin EPS, to provide power to the numerous
processors, CPLD, and peripheral devices.
• Monolithic power supply for VCC (powering internal cores and platform logic)
• DUT-specific power rails are instrumented such that current measurement is possible
• Automatic collection of voltage, current, and power is performed for critical supplies
• Mounting holes are provided of sufficient size to allow onboard supplies to be replaced by bench supplies
• All power supplies can be sequenced as per hardware specifications
The power supplies provided are organized into general categories and are described in the individual sections.
The diagram below shows the power supply architecture.
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VDD_LP
AVDD_SD1_PLL1
AVDD_SD1_PLL2
AVDD_SD2_PLL1
AVDD_SD2_PLL2
0.33ohm
1V0_LP
NCP571
1V35
5.1ohm
AVDD_CGA1
AVDD_DDR1
AVDD_PLAT
AVDD_CGA1
USB_SVDD[1:2]
USB_HVDD[1:2]
USB_OVDD(1:2)
T2080
X1VDD[1:7]/X2VDD[1:6]
BEAT
VDD_CORE
3V3
1V8
1V35 XVDD
S1VDD(1:6)/S2VDD[1:6]
SVDD
1V0S
FA_VL
PROG_MTR
PROG_SFP
D1_MVREF
MVREF
J10
J9
J11
1V8
1V8 OVDD[1:11)/
TH_VDD/CVDD[1:2]
LVDD(1:3)/DVDD[1:2]
G1VDD[1:25]
VDD[1:60]
1V35
2V5
1V8 AVDD_PLAT
VDD_CB
VDD_CA
VDDC/VDD_LL/VDD_LP
AVDD_CORE
AVDD_DDR
BVDD/O2VDD
3V3
1V0S2
1V5X
SVDD
XVDD
GND CVDD/GVDD/LVDD/
OVDD/VDD/BVDD_VSEL
C293
1V0
1V8
1V2 V12/VA12
CS4315
V25_SRDS/V25_IO
LVDD
VDD
AQI1202
0V67
2V5
0V87
5V0 IN USB: MIC2506(U24)
1V8
LDT9FGV0641
VCC NAND FLASH(U68)
MT29F4G08ABBDAH4
74LVC373(U2)
SN74LVCIGS6(U7/9/11)
SN74LVC1GS6(U7/9/11)
Y66.66MHz(X3)
T2080 sys refclk
EPM570
NOR FLASH(U4)
828F00AM29EWHA
VCC
VCC
RTL8211E-VH(U35/U38)
VDD
3V3
ADT7481(U34)
AT24C256(U33)
DSI339U(U31)
MAX3232(U27)
MICX11(U67)
ICS843002(U47)
SFPX2(J13/J15)
OSC.32.768KHz(X2)
1.66.66MHz(X5)
C293 Sys_refclk
P13PCIE3212(U23)
Micro SD Card(12)
SPI FLASH(U13)
N25Q512A13G
PCA9516(U22)
12V
3V3
VTT/VREF
PCIEX4 SLOT(J20)
DDR3_SODIM_ECC
1V35
2V5
3V3 (5A)
5V0 (2A)
0V67 (4A)
0V78 (4A)
1V2(2A)
5V0H
For IR3473_VCC
MIC39102
IR3473
IR3475
12V
IR3473
IR3473
1VB (1.5A)
2V5 (2A)
1V35 (5A)
VTT/MVREF
1V0S
T2080_SVDD
1V0S2
C293_SVDD
1V5x
C290_XVDD
MIC47100
TPSS1200
IR3473
IR3475
1V0 (1A)
3V3
CPLD
VCC_DRV_3.3V
VCC_DRV_7V
MIC39102
YM
VDD_CORE / 35A
Standalone_det
12VEPS
6PIN EPS
12V_PEX
Power
selection 12V
CPLD
3V3
BAT
1V35
1V8
2V5
3V3
PM_BUS
VCORE_PG
VCORE_EN
12V
12V
12V
12V
12V
12V
12V
12V
12V
12V
IR3473
IR3473
IR3473
MIC47100
MIC47100
0.33ohm
0.33ohm
0.33ohm
5.1ohm
5.1ohm
5.1ohm
1V8
BEAT
BEAT
BEAT
BEAT
VCORE
VCORE
VCORE
BEAT
BEAT
5.1ohm
5.1ohm
5.1ohm
VCC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
1V8
1V8
1V8
1V8
1V8
1V8
1V8
1V8
1V8
3V3
3V3
3V3
3V3
VIO
VDD
VDD
VDD
VDD
VDD
VDD
VDD
Y133.33MHz(X4)
T2080 ddr refclk
Y24MHz(x1)
Usb_refclk
Golden
finger
VDD
Power
Regulator
LTC3882
FDMF5820DC
FDMF5820DC
VDD_CORE
VDD_CORE
VCORE / 35A
VDD_CORE_PG
VDD_CORE_EN
Figure 3. Power supply
2.3 Reset
CPLD manages the reset signals to and from the T2080 processor and other devices on the T2080RDB-PC. The diagram below
shows an overview of the reset architecture.
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Architecture
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Golden finger PEX4_RST_N
GND Push-Button
MAX811S
(Power-on RST)
PWR_RST_N
COP_SRST_N
T2080
COP_ITF
T2080
HESET_REQ_N
HRSET_N
PORESET_N
C293
COP_ITF C290_COP_HRST_N
C290_COP_SRST_N
C290_HESET_REQ_N
C290_HRSET_N
C293
C290 Reset
Logic
T2080
Reset
Source
select
RST_CTL
DDR_RSTN
NOR
FLASH
NOR_RSTN
PEX4S_RST PEX SLOT
EDC_RST_N CS4315
DVI_RST_N
EC1_RST_N RGMII
GE PHY1
Soft reset register
RSTCON1 & RSTCON2
SW_RST
7
CPLD
COP_HRST_N
6543210
EC2_RST_N RGMII
GE PHY2
DDR3/
DDR3L
10GBASET
PHY
AQR113C
10GBASET
PHY
AQR113C
DVI_RST_N
Figure 4. Reset architecture
2.4 Clocks
The clock circuitry provides clocks for the processor, for:
• SYSCLK
• DDRCLK (single-ended and differential)
• SerDes clocks
• Ethernet clocks
• USB clock
The architecture of the clock section is shown in the diagram below.
NXP Semiconductors
Architecture
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OSC-66.66MHz
OSC-133.33MHz
OSC-24MHz
25MHz
ICS843002
Golden finger
EDC_REFCLK_P/N(156.25MHz)
SD1_REFCLK1_P/N(156.25MHz)
PEX4_REFCLK_P/N(100MHz)
PI3PCIE3212
CS4315
USB_REFCLK(24MHz)
DDRCLK(133.33MHz)
SYSCLK(66.66MHz)
T2080
SD1_REFCLK1_P/N
SD1_REFCLK2_P/N
SD2_REFCLK1_P/N
SD2_REFCLK2_P/N
P E X S L O T
C293
SD1_REFCLK2_P/N(100MHz)
PEX_CLK_P/N(100MHz)
IDT9FGV0641
SD2_REFCLK1_P/N(100MHz)
C290_SYSCLK (66.66MHz)
OSC-66.66MHz
SD2_REFCLK2_P/N(100M)
PEX4S_REFCLK_P/N(100M)
C290_SD_REFCLK_P/N(100M)
25MHz
Figure 5. Clock architecture
2.5 DDR
The T2080RDB-PC supports high-speed DRAM, with an SODIM socket, featuring single, dual, and quad-rank support. The
memory interface includes the necessary termination and I/O power and is routed to achieve maximum performance of the
memory bus, as shown in the diagram below.
NXP Semiconductors
Architecture
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IV35
187Ohm
187Ohm
DDR_DQ[0:63]
DDR_ECC[0:7]
DDR_MA[0:15]
DDR_MDQS[0:8]
DDR_MDM[0:8]
DDR_MBA[0:2]
DDR_MDOT[0:1],DDR_MAPAR_OUT,DDR_MPAR_ERR
DDR_MCS[0:3]
DDR_MCK_P[0:1]_P/N
DDR_CAS,DDR_RAS,DDR_WE
DDR_MCKE[0:1]
IV35
DDR_RST_N
(CPLD)
I2C1_SCL,I2C1_SDA
MV_REF
VTT
IV35
(SPD_ADDR=0X51)
DDR3 SODIMM SOCKET
DIMM
T2080
DI_MDICI
DI_MDICO
IR3475 TPS
51200
Figure 6. Memory interface
2.6 SerDes port
The T2080 SerDes block provides 16 high-speed serial communication lanes, supporting various protocols, including:
• SGMII 1.25 / 3.125 Gbit/s
• PCI Express (PEX) Gen 1 1X / 2X / 4X 2.5 Gbit/s
• PCI Express (PEX) Gen 2 1X / 2X / 4X 5 Gbit/s
• SATA 1X 1.5 / 3 Gbit/s
The T2080 additionally supports these protocols:
• PCI Express (PEX) Gen 3 1X 8 Gbit/s
• XFI 1X 10.3125 Gbit/s
An overview of the SerDes protocols, which are supported on the T2080RDB, is shown in the table below.
NXP Semiconductors
Architecture
QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 1, 08/2021
User Guide 14 / 44

Table 3. SerDes protocols
SERDES1
SRDS_PRTCL_S1 A B C D E F G H Per lane PLL mapping
66 XFI9 XFI10 XFI1 XFI2 PCIe4 1111
2222
SERDES2
SRDS_PRTCL_S2 A B C D E F G H Per lane PLL mapping
15 PCIe1 PCIe
2
PCI
e2
SAT
A1
SAT
A2
1111
1122
The image below shows the SerDes distribution of T2080RDB-PC.
10G
10G
1G
1G
10G
10G
10GBaseT
XFI.
9-
10G
RGMII
RGMII SERDES 1 66
XFI.1-
10G XFI.2-10G
T2080
SERDES 2 15
PCle2 SATA
FSL
C293
SATA
Conn
PCle x 4 Gen3 support
XFI.
10-
10G PCle SATA
SATA
Conn
10GBaseT
PCle1 x 4 Gen2
PCle4 x 4 Gen3
X4 PCle
Gen3 slot
Figure 7. SerDes distribution of T2080RDB-PC
2.6.1 PCI Express support
The T2080RDB-PC supports PCIe x4 Gen 3 for golden finger and PCIe x4 Gen 2 for slot.
2.6.2 XFI 10G optics port support
The T2080 supports evaluation of the XFI protocol using Cortina CS4315 dual port 10G CDR. 10G data is carried over the XFI
interface. The image below shows the connectivity of XFI interface.
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QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 1, 08/2021
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T2080
XFI
XFI
EMI2
XFI
XFI
EMI2
CS4315
Dual 10G EDC
SFP+
SFP+
SFI
SFI
Figure 8. XFI interface
2.6.3 XFI 10GBase-T port support
The T2080 only supports evaluation of the XFI protocol using dual Aquantia AQR113C 10GBase-T PHYs. 10G data is carried over
the XFI interface. The image below shows the connectivity of XFI interface.
T2080
XFI
XFI
EMI2
XFI
XFI MDI
Magnetics RJ46
MDI
Magnetics RJ46
EMI2
AQR113C
10G Base-T PHY
AQR113C
10G Base-T PHY
Figure 9. XFI interface
2.6.4 SATA support
SATA is evaluated using the two onboard SATA headers, by selecting a SATA-supporting SerDes protocol.
2.7 Ethernet controllers
The T2080 supports two Ethernet Controllers (EC), which can connect to Ethernet PHYs using MII or RGMII protocols. On the
T2080RDB-PC, the EC1 and EC2 ports only operate in RGMII mode. Both ports connect to Realtek RTL8211 PHYs.
The image below shows the connectivity of EC1/EC2 interface.
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QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 1, 08/2021
User Guide 16 / 44

RGMII
MDIO/MDC
ETH. Cntr. 1
T2080
EMII
RGMII
RGMII
MDIO/MDC
RTL8211E_VB
Transformer
Transformer
RJ-45 Port
RJ-45 Port
ETH. Cntr. 2
EMII
RGMII
RTL8211E_VB
Figure 10. EC1/EC2 interface connectivity
2.8 Ethernet Management Interface
The T2080 has two Ethernet Management Interfaces (EMI), both powered by LVDD. However, EMI2 is only used with XFI-based
PHYs, which uses 1.2 V pull-up. EMI1 is used with all other non-XFI-based PHYs, including the onboard RGMII PHYs. The image
below shows the EMI hardware block.
1V2
2V5
EMI1_MDC
EMI1_MDIO
RTL8211E-VB
(RGMII PHY)
RTL8211E-VB
(RGMII PHY)
CS4315
10G CDR
AQR113C
10G-BASET
PHY_ADDR=0x01
PHY_ADDR=0x02
PHY1_ADDR=0x0C
PHY2_ADDR=0x0D
PHY1_ADDR=0x00
PHY2_ADDR=0x08
EMI1_MDC
EMI1_MDIO
T2080
EMI2_MDC
EMI2_MDIO
AQR113C
10G-BASET
Figure 11. EMI hardware block
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QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 1, 08/2021
User Guide 17 / 44

2.9 I2C
The T2080 device supports up to four I2C buses, in order to make the I2C resources equally available to both local and remote
systems. The T2080RDB-PC uses I2C1 port to access onboard devices, such as DDR3 DIMM, RTC, I2C EEPROM, clock
generator, thermal sensor (ADT7481), and core power regulator (LTC3882). The I2C2 bus uses multiplexers to partition the I2C
bus into several subbuses, called channels. Two SFP+ optics use channel 0-1 and the PCIe SLOT use channel 3.
The image below shows the I2C subsystem.
FET Isolation
(TRLML6346)
I2C1
I2C1_SCL
3V3
2V5
DDR3 DIMM
ADT7481
(Thermal Sensor)
AT24C256
DSI339U
IDT9FGV0641
LTC3882
I2C_ADDR=0x51
SFP+ optics
NOT USE
SFP+ optics
PCle SLOT
I2C2_SFP1SCL
I2C2_SDA
I2C2_SCL
I2C2
Channel 3
Channel 2
PCA9546
Channel 1
Channel 0
I2C_ADDR-0X77
T2080
I2C1_SDA
I2C2_SFP1_SDA
I2C2_SFP2_SCL
I2C2_SFP2_SDA
I2C2_CHAN2_SCL
I2C2_CHAN2_SDA
I2C2_PEX4S_SCL
I2C2_PEX4S_SDA
I2C_ADDR=0x4C
I2C_ADDR=0x50
I2C_ADDR=0x68
I2C_ADDR=0x6A
I2C_ADDR=0x63
I2C_ADDR=
0x50
I2C_ADDR=
0x50
2V5
Figure 12. I2C subsystem
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QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 1, 08/2021
User Guide 18 / 44

2.10 SPI interface
The T2080RDB-PC Serial Peripheral Interface (SPI) pins are only used for onboard SPI device accessing various SPI
memory devices.
2.11 Local bus
The T2080 Integrated Flash Controller (IFC), also known as the local bus, supports 32-bit addressing and 8 or 16-bit data widths
for various devices to effectively manage all these resources with the maximum amount of performance and flexibility.
The image below shows an overview of the IFC bus.
T2080
ADDR,DATA,Control
TXBN0304
(1.8V->3.3V)
CPLD
Cfg_vbank[0:2]
IFC_A5-A7
XORs
IFC_VA5-7
NOR_CS
NOR FLASH
(JS28F00AM29EWHA)
NAND_CS
NAND FLASH
(MT29F8G08ABABA WP)
(3.3V)
Figure 13. IFC bus
2.12 SDHC interface
The enhanced SD Host Controller (eSDHC) provides an interface between host system and SD cards. The Secure Digital (SD)
card is designed to meet the security, capacity, performance, and environmental requirements, inherent in emerging audio and
video consumer electronic devices. Booting from eSDHC interface is supported using the on-chip ROM of the processor.
On T2080RDB-PC, a single connector is used for MicroSD memory cards, as shown in the image below.
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QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 1, 08/2021
User Guide 19 / 44

T2080
SD_WP
SD_CD
SDHC_CLK
CMD
DAT[0:3]
TXBN0304
Clamping
diodes
3V33V3
WP
CD
CLK
CMD
DAT[0:3]
Micro
SD Card
Figure 14. SDHC interface
2.13 USB interface
The T2080RDB-PC systems have two integrated USB 2.0 controllers, that allow direct connection to USB ports with appropriate
protection circuitry and power supplies.
The board features are:
• High speed (480 Mbit/s), full-speed (12 Mbit/s), and low-speed (1.5 Mbit/s) operation
• Host mode
• Dual stacked Type A connection
The USB ports connect to a standard Type A connector (USB1 and USB2) for compatibility with most USB peripherals.
Power for the ports is provided by a MIC2506YM, which supplies 5 V at up to 1 A per port. The power enable and power-fault-detect
pins are connected directly to the T2080 for individual port management.
The image below shows how the USB connectivity is implemented on the T2080RDB-PC.
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QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 1, 08/2021
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