NXP Semiconductors I2C Bus AN11022 User manual

AN11022
CLRC663 Quickstart Guide
Rev. 1.1 —
12 July 2012
205911
Application note
COMPANY PUBLIC
Document information
Info
Content
Keywords
RC663, Reader IC, Power Supply, Interfacing RC663, RC663 Quick start
up, Functional description, Register settings
Abstract This document describes the required basic circuitry to operate the
RC663 and it also describes how to set up first communication using the
RC663 Design-In Board (Demo Board V 3_0)

NXP Semiconductors
AN11022
CLRC663 Quickstart Guide
AN11022
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Application note
COMPANY PUBLIC
Rev. 1.1 — 12 July 2012
205911
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Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [e-mail]
Revision history
Rev
Date
Description
1.1
20120712
Some Figures updated because of quality reasons, Section Licenses updated
1.0
20120216
Initial release

NXP Semiconductors
AN11022
CLRC663 Quickstart Guide
AN11022
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Application note
COMPANY PUBLIC
Rev. 1.1 — 12 July 2012
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1. Introduction
This document describes the basic requirements to power up the reader IC. This
application note does not replace the CLRC663 datasheet. Please refer to the datasheet
to read more information on each chapter. This document also gives an overview of the
RC663 evaluation reader board and describes the function and first steps of using the
board and the RC663. For this Application Note Version 3.0 of the 663 reader board is
used.
2. General description of the RC663
The RC663’s overall functionality can be separated into three functions:
1. Generate the RF field: The generated magnetic field has to be maximized within the
limits of the transmitter supply current, general emission limits and requirements to
protocol standards.
2. Transmit data: The coded and modulated data signal has to be transmitted in a way,
that all supported card standards are able to receive it. The signal shape and timing
according to relevant standards has to be considered.
3. Receive data: The response of a card or NFC passive device has to be transferred
to the differential or single sided receive input of the RC663 considering various
limits, e.g. maximum voltage and receiver sensitivity.
In the following chapters the general wiring just like the power supply concept, interface
selection and so on is described.

NXP Semiconductors
AN11022
CLRC663 Quickstart Guide
AN11022
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© NXP B.V. 2012. All rights reserved.
Application note
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2.1 Basic wiring
The basic wiring diagram can be found in Fig 1.
The matching procedure of the antenna
can be found in the application note AN11019 (Ref. 2).
Fig 1. Basic wiring diagram
It is recommended that Input pins which are not used be tied to a defined electrical
potential.
Output pins can be floating.
2.2 Power supply concept
The CLRC663 is supplied by VDD - Supply voltage, PVDD- pad supply and TVDD- Tx
power supply. These three voltages are independent and can have different as well as
the same supply voltage values. e.g. to operate with a 3.3 V supplied Microcontroller,
PVDD and VDD shall be 3.3 V, to guarantee maximum field strength TVDD shall be 5V.
Voltages between 3 V to 5.5 V can be applied to VDD, PVDD and TVDD.
Independent of the voltage it is recommended to buffer these supplies with blocking
capacitors. VDD and PVDD min 100 nF; TVDD min 100 nF parallel to 1 uF
NOTE: AVDD and DVDD are not Voltage inputs! Buffer them with blocking
capacitances of 470 nF each.
470 nF
470 nF

NXP Semiconductors
AN11022
CLRC663 Quickstart Guide
AN11022
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© NXP B.V. 2012. All rights reserved.
Application note
COMPANY PUBLIC
Rev. 1.1 — 12 July 2012
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PMU
TX
TX1
TX2
TVSS
PD V-Regulators 1.8V
HPD
Control
VDD
DVDD
TVDD
AVDD
Fig 2. Power supply diagram
2.3 Interface selection
The CLRC663 supports direct interfacing of various hosts as the SPI, I2C, I2CL and serial
UART interface type. The CLRC663 resets its interface and checks the current host
interface type automatically having performed a Power-On or Hard Reset. The CLRC663
identifies the host interface by the means of the logic levels on the control pins after the
Reset Phase. This is done by a combination of fixed pin connections IF1SEL0 and
IF1SEL1. The following table shows the different configurations:
Table 1. Connection Scheme for detecting the different Interface Types
UART
SPI
I2C
I2C-L
IF0
I/O
Rx
MOSI
ADR1
ADR1
IF1(SCL) I/O SCK SCL SCL
IF2 I/O Tx MISO ADR2 SDA
IF3-SDA SDA Trigger NSS SDA ADR2
IFSEL0
I
0
0
1
1
IFSEL1
I
0
1
0
1
PDOWN

NXP Semiconductors
AN11022
CLRC663 Quickstart Guide
AN11022
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© NXP B.V. 2012. All rights reserved.
Application note
COMPANY PUBLIC
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2.4 Crystal oscillator
The clock applied to the CLRC663 acts as a time basis for generation of the carrier sent
out at TX, for the quadrature mixer I and Q clock generation, and for the coder and
decoder of the synchronous system. Therefore, stability of the clock frequency is an
important factor for proper performance. To obtain highest performance, clock jitter has
to be as small as possible. This is best achieved by using the internal oscillator buffer
with the recommended circuitry.
Fig 3. Crystal connection
Table 2. Crystal requirements recommendations
Symbol Parameter min Typ max Unit
fxtal Crystal frequency 27.12 MHz
∆fxtal
Crystal frequency accuracy
-250
+250
ppm
ESR Equivalent series resistant 50 100 Ω
CL Load capacitance 10 pF
Pxtal Crystal power dissipation 50 100 uW
2.5 Receiver circuit
The Receiver is a fully differential circuit and can be used double ended or single
ended:
For single ended

use (Quasi- Differential) of the receiver circuit it is strongly
recommended to connect RxN and RxP to each other or to connect them by
using the Rcv_Reg register (address 38h).But if the Rcv_Rx_single bit in the
Rcv_Reg register is set to 1 -> Quasi-Differential, the unused Rx pin has to
be open and not connected to Ground.
For double ended
use connect RxN and RxP, as recommended, to the
transmitter circuit, directly after the EMC filter.

NXP Semiconductors
AN11022
CLRC663 Quickstart Guide
AN11022
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Application note
COMPANY PUBLIC
Rev. 1.1 — 12 July 2012
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3. Hardware design of the RC663 evaluation board (“red board”)
3.1 Scope
This part describes the functionality of the evaluation reader based on the RC663. It
includes the functional and electrical specifications and gives the needed details to use
this reader as a reference design.
This reader implementation is based on the HVQFN33 package (body 5 x 5 x 0.85 mm).
The RC663 itself is described in the corresponding data sheet (see reference [1]).
3.2 Features
•Single 7.5 V external power supply
•RS232 DSUB9 connector for easy connection to a host PC
•RS232 Serial UART up to 1228.8 kBd, with voltage levels dependent on pin voltage
supply
•Supports transfer speed communication up to 848 kbit/s with credentials
•I/O pins (GPIO0/SIGIN; SIGOUT)
•Hard Power Down
•Standby mode
•Programmable and cascadable timers
•FiFo buffer handles 512 byte send and receive
•IntegerN PLL providing clock for standard microcontroller used frequencies
•Low power card detection
•Integrated Free-Running Low Power Oscillator
•Digital test signal pins CLKOUT,SIGOUT,TCK,TDI,TDO,TMS
•versatile quadrature receiver architecture with fully differential receiver
•Antenna size: 113 mm x 77 mm

NXP Semiconductors
AN11022
CLRC663 Quickstart Guide
AN11022
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© NXP B.V. 2012. All rights reserved.
Application note
COMPANY PUBLIC
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3.3 Functional description
The RC663 evaluation reader is a contactless smartcard reader based on the RC663
reader IC.
The Reader PCB is divided into 2 Parts, the general reader part and The Antenna and
matching part:
Table 3. PCB sections
PCB Section Description
General reader part
(Fig 5 lower figure) Includes Power supply, Rs232 Interface and RC663 related part also EMC filter for TX circuit
Antenna and matching part
(Fig 5 lower figure) Antenna matching (without EMC filter) with fully differential receiver circuit and PCB antenna coil
The reader has one drawn cutline between EMC filter and matching circuit. This is to cut
the antenna and the antenna related matching from the reader (Fig 4). Seven vias have
been added to connect another Antenna with matching to the evaluation reader.
Fig 4. RC663 board version 3.0

NXP Semiconductors
AN11022
CLRC663 Quickstart Guide
AN11022
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Application note
COMPANY PUBLIC
Rev. 1.1 — 12 July 2012
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3.4 PCB Marking and major improvements to older version
There are two versions of the RC663 board version 2.0 and version 3.0
The latest version is:
NXP
RC663 Board V3.0
The difference is shown below (
Fig 5)
Improvements form V 2.0 to V 3.0:
Adding a Cutline to separate the general reader part from the Antenna and
matching part
Analog debug pins are outlined
Adding pins for current measurement on TVDD
Prepared for adding another antenna with matching

NXP Semiconductors
AN11022
CLRC663 Quickstart Guide
AN11022
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Application note
COMPANY PUBLIC
Rev. 1.1 — 12 July 2012
205911
10 of 48
NXP RC663 Board V2.0
NXP RC663 Board V3.0
Fig 5. NXP RC663 Board V2.0 and 3.0