NXP Semiconductors LPC1311 User manual

UM10375
LPC1311/13/42/43 User manual
Rev. 3 — 14 June 2011 User manual
Document information
Info Content
Keywords ARM Cortex-M3, microcontroller, USB, LPC1311, LPC1313, LPC1342,
LPC1343, LPC1311/01, LPC1313/01
Abstract LPC1311/13/42/43 user manual

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Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
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LPC13xx User manual
Revision history
Rev Date Description
3 20110614 LPC1311/13/42/43 user manual
Modifications:
•Parts LPC1311/01 and LPC1313/01 added.
•Modifications to the user manual applicable to parts LPC1311/01 and LPC1313/01 only:
–SSP1 added for part LPC1313FBD48/01 in Chapter 3 “LPC13xx System
configuration” and Chapter 14 “LPC13xx SSP0/1”.
–UART functions for part LPC1313FBD48/01 added in Table 128, Table 129,
Table 134, and Table 138.
–Use of IRC for entering deep power-down updated in Section 3.9.4.2.
–Enable sequence for UART clock updated in Section 12.1.
–Chapter 5 “LPC13xx Power profiles” added.
–Register IOCON_DSR_LOC (Table 140), IOCON_DCD_LOC (Table 141),
IOCON_RI_LOC (Table 142) added.
–Programmable bit OD for pseudo open-drain mode added to IOCON registers in
Chapter 7.
–Chapter 19 “LPC13xx Windowed WatchDog Timer (WWDT)” added.
•Editorial and formatting updates throughout the user manual.
•Pull-up level for internal pull-ups specified in Section 7.3.2 and Section 8.4.1 and
Section 8.4.2.
•Description WDEN bit updated in Table 290 and Table 296 (WDMOD registers).
•Section 3.7 “Start-up behavior” added.
•NVIC priority register bit description updated in Section 6.6.
•Description of GPIO data register updated in Section 9.4.1.
•LPC1342FBD48 package added.
2 20100707 LPC1311/13/42/43 user manual
1 20091106 LPC1311/13/42/43 user manual

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1.1 Introduction
The LPC13xx are ARM Cortex-M3 based microcontrollers for embedded applications
featuring a high level of integration and low power consumption. The ARM Cortex-M3 is a
next generation core that offers system enhancements such as enhanced debug features
and a higher level of support block integration.
The LPC13xx operate at CPU frequencies of up to 72 MHz. The ARM Cortex-M3 CPU
incorporates a 3-stage pipeline and uses a Harvard architecture with separate local
instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3
CPU also includes an internal prefetch unit that supports speculative branching.
The peripheral complement of the LPC13xx series includes up to 32 kB of flash memory,
up to 8 kB of data memory, USB Device, one Fast-mode Plus (FM+) I2C interface, one
UART, four general purpose timers, and up to 42 general purpose I/O pins.
1.2 How to read this manual
This user manual describes parts LPC1311, LPC1313, LPC1342, LPC1343. Part-specific
features and registers are listed at the beginning of each chapter.
Remark: The LPC13xx series consists of the LPC1300 series (parts LPC1311/13/42/43)
and the LPC1300L series (parts LPC1311/01 and LPC1313/01). The LPC1300L series
features the following enhancements over the LPC1300 series:
•Power profiles with lower power consumption in Active and Sleep modes.
•Four levels for BOD forced reset.
•Second SSP controller (LPC1313FBD48/01 only).
•Windowed Watchdog Timer (WWDT).
•Internal pull-up resistors pull up pins to full VDD level.
•Programmable pseudo open-drain mode for GPIO pins.
1.3 Features
•ARM Cortex-M3 processor, running at frequencies of up to 72 MHz.
•ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
•32 kB (LPC1343/13)/16 kB (LPC1342)/8 kB (LPC1311) on-chip flash programming
memory.
•8 kB (LPC1343/13)/4 kB (LPC1342/11) SRAM.
•In-System Programming (ISP) and In-Application Programming (IAP) via on-chip
bootloader software.
•Selectable boot-up: UART or USB (USB on LPC134x only).
•On LPC134x: USB MSC and HID on-chip drivers.
•Serial interfaces:
UM10375
Chapter 1: LPC13xx Introductory information
Rev. 3 — 14 June 2011 User manual

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Chapter 1: LPC13xx Introductory information
–USB 2.0 full-speed device controller with on-chip PHY for device (LPC1342/43
only).
–UART with fractional baud rate generation, modem, internal FIFO, and
RS-485/EIA-485 support.
–SSP controller with FIFO and multi-protocol capabilities.
–Additional SSP controller on LPC1313FBD48/01.
–I2C-bus interface supporting full I2C-bus specification and Fast-mode Plus with a
data rate of 1 Mbit/s with multiple address recognition and monitor mode.
•Other peripherals:
–Up to 42 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down
resistors.
–Four general purpose counter/timers with a total of four capture inputs and 13
match outputs.
–Programmable WatchDog Timer (WDT).
–Programmable Windowed Watchdog Timer (WWDT) on LPC1311/01 and
LPC1313/01.
–System tick timer.
•Serial Wire Debug and Serial Wire Trace port.
•High-current output driver (20 mA) on one pin.
•High-current sink drivers (20 mA) on two I2C-bus pins in Fast-mode Plus.
•Integrated PMU (Power Management Unit) to minimize power consumption during
Sleep, Deep-sleep, and Deep power-down modes.
•Power profiles residing in boot ROM allowing to optimize performance and minimize
power consumption for any given application through one simple function call.
(LPC1300L series, on LPC1311/01 and LPC1313/01 only.)
•Three reduced power modes: Sleep, Deep-sleep, and Deep power-down.
•Single power supply (2.0 V to 3.6 V).
•10-bit ADC with input multiplexing among 8 pins.
•GPIO pins can be used as edge and level sensitive interrupt sources.
•Clock output function with divider that can reflect the system oscillator clock, IRC
clock, CPU clock, or the watchdog clock.
•Processor wake-up from Deep-sleep mode via a dedicated start logic using up to 40
of the functional pins.
•Brownout detect with four separate thresholds for interrupt and one threshold for
forced reset (four thresholds for forced reset on the LPC1311/01 and LPC1313/01
parts).
•Power-On Reset (POR).
•Integrated oscillator with an operating range of 1 MHz to 25 MHz.
•12 MHz internal RC oscillator trimmed to 1 % accuracy over the entire temperature
and voltage range that can optionally be used as a system clock.
•Programmable watchdog oscillator with a frequency range of 7.8 kHz to 1.8 MHz.

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Chapter 1: LPC13xx Introductory information
•System PLL allows CPU operation up to the maximum CPU rate without the need for
a high-frequency crystal. May be run from the system oscillator or the internal RC
oscillator.
•For USB (LPC1342/43), a second, dedicated PLL is provided.
•Code Read Protection (CRP) with different security levels.
•Unique device serial number for identification.
•Available as 48-pin LQFP package and 33-pin HVQFN package.
1.4 Ordering options
Table 1. Ordering information
Type number Package
Name Description Version
LPC1311FHN33 HVQFN33 HVQFN33: plastic thermal enhanced very thin quad flat package; no
leads; 33 terminals; body 7 7 0.85 mm n/a
LPC1311FHN33/01 HVQFN33 HVQFN33: plastic thermal enhanced very thin quad flat package; no
leads; 33 terminals; body 7 7 0.85 mm n/a
LPC1313FHN33 HVQFN33 HVQFN33: plastic thermal enhanced very thin quad flat package; no
leads; 33 terminals; body 7 7 0.85 mm n/a
LPC1313FHN33/01 HVQFN33 HVQFN33: plastic thermal enhanced very thin quad flat package; no
leads; 33 terminals; body 7 7 0.85 mm n/a
LPC1313FBD48 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7 7 
1.4 mm SOT313-2
LPC1313FBD48/01 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7 7 
1.4 mm SOT313-2
LPC1342FHN33 HVQFN33 HVQFN33: plastic thermal enhanced very thin quad flat package; no
leads; 33 terminals; body 7 7 0.85 mm n/a
LPC1342FBD48 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7 7 
1.4 mm SOT313-2
LPC1343FHN33 HVQFN33 HVQFN33: plastic thermal enhanced very thin quad flat package; no
leads; 33 terminals; body 7 7 0.85 mm n/a
LPC1343FBD48 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7 7 
1.4 mm SOT313-2
Table 2. Ordering options for LPC13xx
Type number Flash Total
SRAM USB Power profiles UART RS-485 I2C/ Fast+ SSP ADC channels Pins Package
LPC1311FHN33 8 kB 4 kB - no 1 1 1 8 33 HVQFN33
LPC1311FHN33/01 8 kB 4 kB - yes 1 1 1 8 33 HVQFN33
LPC1313FHN33 32 kB 8 kB - no 1 1 1 8 33 HVQFN33
LPC1313FHN33/01 32 kB 8 kB - yes 1 1 1 8 33 HVQFN33
LPC1313FBD48 32 kB 8 kB - no 1 1 1 8 48 LQFP48
LPC1313FBD48/01 32 kB 8 kB - yes 1 1 2 8 48 LQFP48
LPC1342FHN33 16 kB 4 kB Device no 1 1 1 8 33 HVQFN33

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Chapter 1: LPC13xx Introductory information
LPC1342FBD48 16 kB 4 kB Device no 1 1 1 8 48 LQFP48
LPC1343FHN33 32 kB 8 kB Device no 1 1 1 8 33 HVQFN33
LPC1343FBD48 32 kB 8 kB Device no 1 1 1 8 48 LQFP48
Table 2. Ordering options for LPC13xx
Type number Flash Total
SRAM USB Power profiles UART RS-485 I2C/ Fast+ SSP ADC channels Pins Package

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Chapter 1: LPC13xx Introductory information
1.5 Block diagram
(1) LPC1342/43 only.
(2) LQFP48 package only.
(3) On LPC1313FBD48/01 only.
(4) Windowed WatchDog Timer (WWDT) on LPC1311/01 and LPC1313/01 only.
Fig 1. LPC13xx block diagram
SRAM
4/8 kB
ARM
CORTEX-M3
TEST/DEBUG
INTERFACE
FLASH
8/16/32 kB
USB DEVICE
CONTROLLER(1)
I-code
bus
D-code
bus
system
bus
AHB TO
APB
BRIDGE
HIGH-SPEED
GPIO
CLOCK
GENERATION,
POWER CONTROL,
SYSTEM
FUNCTIONS
XTALIN
XTALOUT
RESET
clocks and
controls
SWD
USB PHY(1)
SSP0
10-bit ADC
UART
32-bit COUNTER/TIMER 0
I2C-BUS
WDT/WWDT(4)
IOCONFIG
LPC1311/13/42/43
slave
002aae722
slaveslave slave
slave
ROM
slave
AHB-LITE BUS
GPIO ports
PIO0/1/2/3
CT32B0_MAT[3:0]
AD[7:0]
CT32B0_CAP0
SDA
SCL
RXD
TXD
DTR, DSR(2), CTS,
DCD(2), RI(2), RTS
SYSTEM CONTROL
32-bit COUNTER/TIMER 1
CT32B1_MAT[3:0]
CT32B1_CAP0
16-bit COUNTER/TIMER 1
CT16B1_MAT[1:0]
CT16B1_CAP0
16-bit COUNTER/TIMER 0
CT16B0_MAT[2:0]
CT16B0_CAP0
USB pins
SCK0,SSEL0
MISO0, MOSI0
SSP1(3) SCK1,SSEL1
MISO1, MOSI0
CLKOUT
IRC
WDO
POR

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2.1 How to read this chapter
See Table 3 for LPC13xx memory configurations:
2.2 Memory map
Figure 2 shows the memory and peripheral address space of the LPC13xx.
The AHB peripheral area is 2 MB in size and is divided to allow for up to 128 peripherals.
On the LPC13xx, the GPIO ports are the only AHB peripherals. The APB peripheral area
is 512 kB in size and is divided to allow for up to 32 peripherals. Each peripheral of either
type is allocated 16 kB of space. This allows simplifying the address decoding for each
peripheral.
All peripheral register addresses are 32-bit word aligned regardless of their size. An
implication of this is that word and half-word registers must be accessed all at once. For
example, it is not possible to read or write the upper byte of a word register separately.
UM10375
Chapter 2: LPC13xx Memory mapping
Rev. 3 — 14 June 2011 User manual
Table 3. LPC13xx memory configuration
Part Flash Address range SRAM Address range
LPC1311 8 kB 0x0000 0000 - 0x0000 1FFF 4 kB 0x1000 0000 - 0x1000 0FFF
LPC1311/01 8 kB 0x0000 0000 - 0x0000 1FFF 4 kB 0x1000 0000 - 0x1000 0FFF
LPC1313 32 kB 0x0000 0000 - 0x0000 7FFF 8 kB 0x1000 0000 - 0x1000 1FFF
LPC1313/01 32 kB 0x0000 0000 - 0x0000 7FFF 8 kB 0x1000 0000 - 0x1000 1FFF
LPC1342 16 kB 0x0000 0000 - 0x0000 3FFF 4 kB 0x1000 0000 - 0x1000 0FFF
LPC1343 32 kB 0x0000 0000 - 0x0000 7FFF 8 kB 0x1000 0000 - 0x1000 1FFF

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Chapter 2: LPC13xx Memory mapping
2.3 Memory remapping
For details, see Table 8.
Fig 2. LPC13xx memory map
0x5000 0000
0x5001 0000
0x5002 0000
0x5020 0000
AHB peripherals
16 - 127 reserved
GPIO PIO1
4-7
0x5003 0000
0x5004 0000
GPIO PIO2
GPIO PIO3
8-11
12-15
GPIO PIO0
0-3
APB peripherals
0x4000 4000
0x4000 8000
0x4000 C000
0x4001 0000
0x4001 8000
0x4002 0000
0x4002 8000
0x4003 8000
0x4003 C000
0x4004 0000
0x4004 4000
0x4004 8000
0x4004 C000
0x4008 0000
0x4002 4000
0x4001 C000
0x4001 4000
0x4000 0000
WDT/WWDT
32-bit counter/timer 0
32-bit counter/timer 1
ADC
UART
PMU
I
2
C-bus
10 - 13 reserved
reserved
19 - 21 reserved
23 - 31 reserved
0
1
2
3
4
5
6
7
8
9
16
15
14
17
18
reserved
reserved
0x0000 0000
0 GB
0.5 GB
4 GB
1 GB
0x0000 4000
0x0000 2000
0x1000 2000
0x1000 1000
0x1FFF 0000
0x1FFF 4000
0x2000 0000
0x4000 0000
0x4008 0000
0x5000 0000
0x5020 0000
0xFFFF FFFF
reserved
reserved
reserved
APB peripherals
AHB peripherals
8 kB SRAM (LPC1313/1343)
0x1000 0000
4 kB SRAM (LPC1311/1342)
LPC1311/13/42/43
16 kB on-chip flash (LPC1342)
8 kB on-chip flash (LPC1311)
0x0000 8000
32 kB on-chip flash (LPC1313/43)
16 kB boot ROM
0x0000 0000
0x0000 0400
active interrupt vectors
+ 256 words
I-code/D-code
memory space
002aae723
reserved
reserved
SSP0
0x4005 8000
0x4005 C000
22 SSP1 (LPC1313FBD48/01)
16-bit counter/timer 1
16-bit counter/timer 0
USB (LPC1342/43 only)
IOCONFIG
system control
flash controller
0xE000 0000
0xE010 0000
private peripheral bus

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3.1 How to read this chapter
The system configuration registers apply to all LPC13xx parts with the following
exceptions:
USB clocking and power control
Since the USB block is available on the LPC1342 and LPC1343 only, the registers and
register bits listed in Table 4 are reserved for parts LPC1311 and LPC1313:
SSP1
The SSP1 block is available on the LPC1313FBD48/01 only. SSP1 related registers and
register bits are reserved for the following parts: LPC1311/13/42/43 and
LPC1311FHN33/01 and LPC1313FHN33/01.
BOD control
The number of programmable BOD levels for forced reset is different for the LPC1300 and
the LPC1300L series. See Table 5. The BOD trip levels for the LPC1300 and LPC1300L
series are listed in the LPC1311/13/42/43 data sheet.
UM10375
Chapter 3: LPC13xx System configuration
Rev. 3 — 14 June 2011 User manual
Table 4. USB related registers and register bits reserved for LPC1311/13
Name Access Address
offset Description Register bits reserved for
LPC1311/13
USBPLLCTRL R/W 0x010 USB PLL control all
USBPLLSTAT R 0x014 USB PLL status all
USBPLLCLKSEL R/W 0x048 USB PLL clock source select all
USBPLLCLKUEN R/W 0x04C USB PLL clock source update enable all
SYSAHBCLKCTRL R/W 0x080 System AHB clock control bit 14
USBCLKSEL R/W 0x0C0 USB clock source select all
USBCLKUEN R/W 0x0C4 USB clock source update enable all
USBCLKDIV R/W 0x0C8 USB clock source divider all
PDSLEEPCFG R/W 0x230 Power-down states in Deep-sleep
mode bits 8 and 10
PDAWAKECFG R/W 0x234 Power-down states after wake-up from
Deep-sleep mode bits 8 and 10
PDRUNCFG R/W 0x238 Power-down configuration register bits 8 and 10
Table 5. BOD interrupt and reset levels
Series Type number Interrupt levels Reset levels
LPC1300 LPC1311FHN33 4 (programmable) 1 (fixed)
LPC1300 LPC1313FBD48 4 (programmable) 1 (fixed)
LPC1300 LPC1313FHN33 4 (programmable) 1 (fixed)
LPC1300 LPC1342FHN33 4 (programmable) 1 (fixed)
LPC1300 LPC1343FBD48 4 (programmable) 1 (fixed)

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Chapter 3: LPC13xx System configuration
Input pins to the start logic
For HVQFN packages, the start logic control bits (see Table 44 to Table 51) are reserved
for port pins PIO2_1 to PIO2_11 and PIO3_0, PIO3_1, and PIO3_3.
PIO reset status registers
For HVQFN packages, the reset status bits (see Table 40 and Table 41) are reserved for
port pins PIO2_1 to PIO2_11 and PIO3_0 and PIO3_1, and PIO3_3.
Entering Deep power-down mode
Status of the IRC before entering Deep power-down mode (see Section 3.9.4.2):
•IRC must be enabled for parts LPC1311/13/42/43.
•IRC status has no effect for parts LPC1311/01 and LPC1313/01.
Enabling sequence for UART clock
Requirements for enabling the UART peripheral clock:
•The UART pins must be configured in the IOCON block before the UART clock can be enabled
in the in the SYSAHBCLKCTRL register (Table 25) for parts LPC1311/13/42/43.
•The sequence of configuring the UART pins and the UART clock has no effect for
parts LPC1311/01 and LPC1313/01.
3.2 Introduction
The system configuration block controls oscillators, the power management unit, and
clock generation of the LPC13xx. Also included in this block are registers for setting the
priority for AHB access and a register for remapping flash, SRAM, and ROM memory
areas.
LPC1300 LPC1343FHN33 4 (programmable) 1 (fixed)
LPC1300L LPC1311FHN33/01 4 (programmable) 4 (programmable)
LPC1300L LPC1313FHN33/01 4 (programmable) 4 (programmable)
LPC1300L LPC1313FBD48/01 4 (programmable) 4 (programmable)
Table 5. BOD interrupt and reset levels
Series Type number Interrupt levels Reset levels

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Chapter 3: LPC13xx System configuration
3.3 Pin description
Table 6 shows pins that are associated with system control block functions.
[1] For HVQFN packages, applies to P2_0, P3_2, and P3_3 only.
Table 6. Pin summary
Pin name Pin
direction Pin description
CLKOUT O Clockout pin
PIO0_0 to PIO0_11 I Wake-up pins port 0
PIO1_0 to PIO1_11 I Wake-up pins port 1
PIO2_0 to PIO2_11[1] I Wake-up pins port 2
PIO3_0 to PIO3_3[1] I Wake-up pins port 3

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Chapter 3: LPC13xx System configuration
3.4 Clocking and power control
See Figure 3 for an overview of the LPC13xx Clock Generation Unit (CGU).
The LPC131x include three independent oscillators. These are the system oscillator, the
Internal RC oscillator (IRC), and the Watchdog oscillator. Each oscillator can be used for
more than one purpose as required in a particular application.
Following reset, the LPC131x will operate from the Internal RC oscillator until switched by
software. This allows systems to operate without any external crystal and the bootloader
code to operate at a known frequency.
The SYSAHBCLKCTRL register gates the system clock to the various peripherals and
memories. UART, SSP0/1, the SysTick timer, and the ARM trace clock have individual
clock dividers to derive peripheral clocks from the main clock.
The USB clock, if available, and the watchdog clock, can be derived from the oscillator
output or the main clock.
The main clock, and the clock outputs from the IRC, the system oscillator, and the
watchdog oscillator can be observed directly on the CLKOUT pin.

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Chapter 3: LPC13xx System configuration
3.5 Register description
All registers, regardless of size, are on word address boundaries. Details of the registers
appear in the description of each function.
See Section 3.12 for the flash access timing register, which can be re-configured as part
the system setup. This register is not part of the system configuration block.
USB is available in parts LPC134x only.
SSP1 is available on part LPC1313FBD48 only.
Fig 3. LPC13xx CGU block diagram
SYS PLL
irc_osc_clk
sys_osc_clk
sys_osc_clk
wdt_osc_clk
irc_osc_clk
irc_osc_clk
wdt_osc_clk
USB PLL
MAINCLKSEL
SYSPLLCLKSEL
USBPLLCLKSEL
CLOCK
DIVIDER
SYSAHBCLKCTRL
(ROM enable)
SYSAHBCLKCTRL
(SSP1 enable)
CLOCK
DIVIDER SSP0/1_PCLK
CLOCK
DIVIDER UART_PCLK
CLOCK
DIVIDER
CLOCK
DIVIDER
SYSTICK
timer
CLOCK
DIVIDER ARM trace clock
WDCLK
WDTUEN
CLOCK
DIVIDER usb_clk
USBUEN
wdt_osc_clk
irc_osc_clk
sys_osc_clk CLOCK
DIVIDER CLKOUT
CLKOUTUEN
main clock system clock
sys_pllclkin
usb_pllclkin
sys_pllclkout
usb_pllclkout
2
ARM
CORTEX-M3
ROM
SSP1
SYSAHBCLKDIV

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Chapter 3: LPC13xx System configuration
Table 7. Register overview: system control block (base address 0x4004 8000)
Name Access Address offset Description Reset value Reference
SYSMEMREMAP R/W 0x000 System memory remap 0x0000 0002 Table 8
PRESETCTRL R/W 0x004 Peripheral reset control 0x0000 0000 Table 9
SYSPLLCTRL R/W 0x008 System PLL control 0x0000 0000 Table 10
SYSPLLSTAT R 0x00C System PLL status 0x0000 0000 Table 11
USBPLLCTRL R/W 0x010 USB PLL control 0x0000 0000 Table 12
USBPLLSTAT R 0x014 USB PLL status 0x0000 0000 Table 13
- - 0x018 - 0x01C Reserved - -
SYSOSCCTRL R/W 0x020 System oscillator control 0x0000 0000 Table 14
WDTOSCCTRL R/W 0x024 Watchdog oscillator control 0x0000 0000 Table 15
IRCCTRL R/W 0x028 IRC control 0x0000 0080 Table 16
- - 0x02C Reserved - -
SYSRESSTAT R 0x030 System reset status register 0x0000 0000 Table 17
- - 0x034 - 0x03C Reserved - -
SYSPLLCLKSEL R/W 0x040 System PLL clock source select 0x0000 0000 Table 18
SYSPLLCLKUEN R/W 0x044 System PLL clock source update enable 0x0000 0000 Table 19
USBPLLCLKSEL R/W 0x048 USB PLL clock source select 0x0000 0000 Table 20
USBPLLCLKUEN R/W 0x04C USB PLL clock source update enable 0x0000 0000 Table 21
- - 0x050 - 0x06C Reserved - -
MAINCLKSEL R/W 0x070 Main clock source select 0x0000 0000 Table 22
MAINCLKUEN R/W 0x074 Main clock source update enable 0x0000 0000 Table 23
SYSAHBCLKDIV R/W 0x078 System AHB clock divider 0x0000 0001 Table 24
- - 0x07C Reserved - -
SYSAHBCLKCTRL R/W 0x080 System AHB clock control 0x0000 485F Table 25
- - 0x084 - 0x090 Reserved - -
SSP0CLKDIV R/W 0x094 SSP0 clock divider 0x0000 0000 Table 26
UARTCLKDIV R/W 0x098 UART clock divder 0x0000 0000 Table 27
SSP1CLKDIV R/W 0x09C SSP1 clock divider 0x000 Table 28
- - 0x0A0 - 0x0A8 Reserved - -
TRACECLKDIV R/W 0x0AC ARM trace clock divider 0x0000 0000 Table 29
SYSTICKCLKDIV R/W 0x0B0 SYSTICK clock divder 0x0000 0000 Table 30
- - 0x0B4 - 0x0BC Reserved - -
USBCLKSEL R/W 0x0C0 USB clock source select 0x0000 0000 Table 31
USBCLKUEN R/W 0x0C4 USB clock source update enable 0x0000 0000 Table 32
USBCLKDIV R/W 0x0C8 USB clock source divider 0x0000 0000 Table 33
- - 0x0CC Reserved - -
WDTCLKSEL R/W 0x0D0 WDT clock source select 0x0000 0000 Table 34
WDTCLKUEN R/W 0x0D4 WDT clock source update enable 0x0000 0000 Table 35
WDTCLKDIV R/W 0x0D8 WDT clock divider 0x0000 0000 Table 36
- - 0x0DC Reserved - -
CLKOUTCLKSEL R/W 0x0E0 CLKOUT clock source select 0x0000 0000 Table 37
CLKOUTUEN R/W 0x0E4 CLKOUT clock source update enable 0x0000 0000 Table 38

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Chapter 3: LPC13xx System configuration
3.5.1 System memory remap register
The system memory remap register selects whether the ARM interrupt vectors are read
from the boot ROM, the flash, or the SRAM.
CLKOUTDIV R/W 0x0E8 CLKOUT clock divider 0x0000 0000 Table 39
- - 0x0EC - 0x0FC Reserved - -
PIOPORCAP0 R 0x100 POR captured PIO status 0 - Table 40
PIOPORCAP1 R 0x104 POR captured PIO status 1 - Table 40
- - 0x108 - 0x14C Reserved 0x0000 0000 -
BODCTRL R/W 0x150 BOD control 0x0000 0000 Table 42
SYSTCKCAL R/W 0x154 System tick counter calibration 0x0000 0004 Table 43
- - 0x158 - 0x1FC Reserved - -
STARTAPRP0 R/W 0x200 Start logic edge control register 0; bottom
32 interrupts -Table 44
STARTERP0 R/W 0x204 Start logic signal enable register 0;
bottom 32 interrupts -Table 45
STARTRSRP0CLR W 0x208 Start logic reset register 0; bottom 32
interrupts -Table 46
STARTSRP0 R 0x20C Start logic status register 0; bottom 32
interrupts -Table 47
STARTAPRP1 R/W 0x210 Start logic edge control register 1; top 8
interrupts -Table 48
STARTERP1 R/W 0x214 Start logic signal enable register 1; top 8
interrupts -Table 49
STARTRSRP1CLR W 0x218 Start logic reset register 1; top 8
interrupts -Table 50
STARTSRP1 R 0x21C Start logic status register 1; top 8
interrupts -Table 51
- - 0x220 - 0x22C Reserved - -
PDSLEEPCFG R/W 0x230 Power-down states in Deep-sleep mode 0x0000 0000 Table 53
PDAWAKECFG R/W 0x234 Power-down states after wake-up from
Deep-sleep mode 0x0000 FDF0 Table 54
PDRUNCFG R/W 0x238 Power-down configuration register 0x0000 FDF0 Table 55
- - 0x23C - 0x3F0 Reserved - -
DEVICE_ID R 0x3F4 Device ID part
dependent Table 56
Table 7. Register overview: system control block (base address 0x4004 8000) …continued
Name Access Address offset Description Reset value Reference

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Chapter 3: LPC13xx System configuration
3.5.2 Peripheral reset control register
This register allows software to reset the SSP0/1 and I2C peripherals. Writing a 0 to the
SSP0/1_RST_N or I2C_RST_N bits resets the SSP0/1 or I2C peripherals. Writing a 1
de-asserts the reset.
Remark: Before accessing the SSP0/1 and I2C peripherals, write a 1 to this register to
ensure that the reset signals to the SSP0/1 and I2C are de-asserted.
3.5.3 System PLL control register
This register connects and enables the system PLL and configures the PLL multiplier and
divider values. The PLL accepts an input frequency from 10 MHz to 25 MHz from various
clock sources. The input frequency is multiplied up to a high frequency, then divided down
to provide the actual clock used by the CPU, peripherals, and optionally the USB
subsystem. Note that the USB subsystem has its own dedicated PLL. The PLL can
produce a clock up to the maximum allowed for the CPU, which is 72 MHz.
Table 8. System memory remap register (SYSMEMREMAP, address 0x4004 8000) bit
description
Bit Symbol Value Description Reset
value
1:0 MAP System memory remap 10
0x0 Boot Loader Mode. Interrupt vectors are re-mapped to Boot
ROM.
0x1 User RAM Mode. Interrupt vectors are re-mapped to Static
RAM.
0x2 User Flash Mode. Interrupt vectors are not re-mapped and
reside in Flash.
31:2 - - Reserved 0x00
Table 9. Peripheral reset control register (PRESETCTRL, address 0x4004 8004) bit
description
Bit Symbol Value Description Reset
value
0 SSP0_RST_N SSP0 reset control 0
0 Reset SSP0.
1 De-assert SSP0 reset.
1 I2C_RST_N I2C reset control 0
0 Reset I2C.
1 De-asset I2C reset.
2 SSP1_RST_N SSP1 reset control 0
0 Reset the SSP1.
1 De-assert SSP1 reset.
31:3 - - Reserved 0x00

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Chapter 3: LPC13xx System configuration
3.5.4 System PLL status register
This register is a Read-only register and supplies the PLL lock status (see Section 3.11.1).
3.5.5 USB PLL control register
The USB PLL is identical to the system PLL and is used to provide a dedicated clock to
the USB block if available (see Section 3.1).
This register connects and enables the USB PLL and configures the PLL multiplier and
divider values. The PLL accepts an input frequency from 10 MHz to 25 MHz from various
clock sources. The input frequency is multiplied up to a high frequency, then divided down
to provide the actual clock 48 MHz clock used by the USB subsystem.
Remark: The USB PLL must be connected to the system oscillator for correct USB
operation (see Table 20).
Table 10. System PLL control register (SYSPLLCTRL, address 0x4004 8008) bit description
Bit Symbol Value Description Reset
value
4:0 MSEL Feedback divider value. The division value M is the
programmed MSEL value + 1.
00000: Division ratio M = 1
to
11111: Division ratio M = 32.
0x000
6:5 PSEL Post divider ratio P. The division ratio is 2 P. 0x00
0x0 P = 1
0x1 P = 2
0x2 P = 4
0x3 P = 8
31:7 - - Reserved. Do not write ones to reserved bits. 0x00
Table 11. System PLL status register (SYSPLLSTAT, address 0x4004 800C) bit description
Bit Symbol Value Description Reset
value
0 LOCK PLL lock status 0x0
0 PLL not locked
1 PLL locked
31:1 - - Reserved 0x00
Table 12. USB PLL control register (USBPLLCTRL, address 0x4004 8010) bit description
Bit Symbol Value Description Reset
value
4:0 MSEL Feedback divider value. The division value M is the
programmed MSEL value + 1.
00000: Division ratio M = 1
to
11111: Division ratio M = 32.
0x000

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Chapter 3: LPC13xx System configuration
3.5.6 USB PLL status register
This register is a Read-only register and supplies the PLL lock status (see Section 3.11.1).
6:5 PSEL Post divider ratio P. The division ratio is 2 P. 0x00
0x0 P = 1
0x1 P = 2
0x2 P = 4
0x3 P = 8
31:7 - - Reserved. Do not write ones to reserved bits. 0x00
Table 12. USB PLL control register (USBPLLCTRL, address 0x4004 8010) bit description
Bit Symbol Value Description Reset
value
Table 13. USB PLL status register (USBPLLSTAT, address 0x4004 8014) bit description
Bit Symbol Value Description Reset
value
0 LOCK PLL lock status 0x0
0 PLL not locked
1 PLL locked
31:1 - - Reserved 0x00

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Chapter 3: LPC13xx System configuration
3.5.7 System oscillator control register
This register configures the frequency range for the system oscillator.
3.5.8 Watchdog oscillator control register
This register configures the watchdog oscillator. The oscillator consists of an analog and a
digital part. The analog part contains the oscillator function and generates an analog clock
(Fclkana). With the digital part, the analog output clock (Fclkana) can be divided to the
required output clock frequency wdt_osc_clk. The analog output frequency (Fclkana) can
be adjusted with the FREQSEL bits between 500 kHz and 3.4 MHz. With the digital part
Fclkana will be divided (divider ratios = 2, 4,...,64) to wdt_osc_clk using the DIVSEL bits.
The output clock frequency of the watchdog oscillator can be calculated as
wdt_osc_clk = Fclkana/(2 (1 + DIVSEL)) = 7.8 kHz to 1.7 MHz (nominal values).
Remark: Any setting of the FREQSEL bits will yield a Fclkana value within 40% of the
listed frequency value. The watchdog oscillator is the clock source with the lowest power
consumption. If accurate timing is required, use the IRC or system clock.
Remark: The frequency of the watchdog oscillator is undefined after reset. The watchdog
oscillator frequency must be programmed by writing to the WDTOSCCTRL register before
using the watchdog oscillator.
Table 14. System oscillator control register (SYSOSCCTRL, address 0x4004 8020) bit
description
Bit Symbol Value Description Reset
value
0 BYPASS Bypass system oscillator 0x0
0 Oscillator is not bypassed.
1 Bypass enabled. PLL input (sys_osc_clk) is fed
directly from the XTALIN and XTALOUT pins.
1 FREQRANGE Determines frequency range for Low-power
oscillator. 0x0
0 1 - 20 MHz frequency range.
1 15 - 25 MHz frequency range
31:2 - - Reserved 0x00
Table 15. Watchdog oscillator control register (WDTOSCCTRL, address 0x4004 8024) bit
description
Bit Symbol Value Description Reset
value
4:0 DIVSEL Select divider for Fclkana.
wdt_osc_clk = Fclkana/(2 (1 + DIVSEL)).
00000: 2 (1 + DIVSEL) = 2
00001: 2 (1 + DIVSEL) = 4
to
11111: 2 (1 + DIVSEL) = 64
0x0