NXP Semiconductors MK30DX64VMC7 User manual

K30 Sub-Family Reference Manual
Supports: MK30DX128VLL7, MK30DX256VLL7, MK30DX64VMC7,
MK30DX128VMC7, MK30DX256VMC7
Document Number: K30P100M72SF1RM
Rev. 1.1, Dec 2012

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Contents
Section number Title Page
Chapter 1
About This Document
1.1 Overview.......................................................................................................................................................................49
1.1.1 Purpose.........................................................................................................................................................49
1.1.2 Audience......................................................................................................................................................49
1.2 Conventions..................................................................................................................................................................49
1.2.1 Numbering systems......................................................................................................................................49
1.2.2 Typographic notation...................................................................................................................................50
1.2.3 Special terms................................................................................................................................................50
Chapter 2
Introduction
2.1 Overview.......................................................................................................................................................................51
2.2 Module Functional Categories......................................................................................................................................51
2.2.1 ARM Cortex-M4 Core Modules..................................................................................................................52
2.2.2 System Modules...........................................................................................................................................53
2.2.3 Memories and Memory Interfaces...............................................................................................................54
2.2.4 Clocks...........................................................................................................................................................54
2.2.5 Security and Integrity modules....................................................................................................................55
2.2.6 Analog modules...........................................................................................................................................55
2.2.7 Timer modules.............................................................................................................................................56
2.2.8 Communication interfaces...........................................................................................................................57
2.2.9 Human-machine interfaces..........................................................................................................................57
2.3 Orderable part numbers.................................................................................................................................................58
Chapter 3
Chip Configuration
3.1 Introduction...................................................................................................................................................................59
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3.2 Core modules................................................................................................................................................................59
3.2.1 ARM Cortex-M4 Core Configuration..........................................................................................................59
3.2.2 Nested Vectored Interrupt Controller (NVIC) Configuration......................................................................61
3.2.3 Asynchronous Wake-up Interrupt Controller (AWIC) Configuration.........................................................67
3.2.4 JTAG Controller Configuration...................................................................................................................69
3.3 System modules............................................................................................................................................................69
3.3.1 SIM Configuration.......................................................................................................................................69
3.3.2 System Mode Controller (SMC) Configuration...........................................................................................70
3.3.3 PMC Configuration......................................................................................................................................71
3.3.4 Low-Leakage Wake-up Unit (LLWU) Configuration.................................................................................71
3.3.5 MCM Configuration....................................................................................................................................73
3.3.6 Crossbar Switch Configuration....................................................................................................................74
3.3.7 Peripheral Bridge Configuration..................................................................................................................75
3.3.8 DMA request multiplexer configuration......................................................................................................76
3.3.9 DMA Controller Configuration...................................................................................................................79
3.3.10 External Watchdog Monitor (EWM) Configuration....................................................................................80
3.3.11 Watchdog Configuration..............................................................................................................................82
3.4 Clock modules..............................................................................................................................................................83
3.4.1 MCG Configuration.....................................................................................................................................83
3.4.2 OSC Configuration......................................................................................................................................84
3.4.3 RTC OSC configuration...............................................................................................................................85
3.5 Memories and memory interfaces.................................................................................................................................85
3.5.1 Flash Memory Configuration.......................................................................................................................85
3.5.2 Flash Memory Controller Configuration.....................................................................................................88
3.5.3 SRAM Configuration...................................................................................................................................89
3.5.4 SRAM Controller Configuration.................................................................................................................92
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3.5.5 System Register File Configuration.............................................................................................................93
3.5.6 VBAT Register File Configuration..............................................................................................................94
3.5.7 EzPort Configuration...................................................................................................................................94
3.6 Security.........................................................................................................................................................................96
3.6.1 CRC Configuration......................................................................................................................................96
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3.7 Analog...........................................................................................................................................................................96
3.7.1 16-bit SAR ADC with PGA Configuration.................................................................................................96
3.7.2 CMP Configuration......................................................................................................................................106
3.7.3 12-bit DAC Configuration...........................................................................................................................108
3.7.4 VREF Configuration....................................................................................................................................109
3.8 Timers...........................................................................................................................................................................110
3.8.1 PDB Configuration......................................................................................................................................110
3.8.2 FlexTimer Configuration.............................................................................................................................113
3.8.3 PIT Configuration........................................................................................................................................117
3.8.4 Low-power timer configuration...................................................................................................................118
3.8.5 CMT Configuration......................................................................................................................................120
3.8.6 RTC configuration.......................................................................................................................................121
3.9 Communication interfaces............................................................................................................................................122
3.9.1 CAN Configuration......................................................................................................................................122
3.9.2 SPI configuration.........................................................................................................................................124
3.9.3 I2C Configuration........................................................................................................................................128
3.9.4 UART Configuration...................................................................................................................................128
3.9.5 I2S configuration..........................................................................................................................................131
3.10 Human-machine interfaces...........................................................................................................................................134
3.10.1 GPIO configuration......................................................................................................................................134
3.10.2 TSI Configuration........................................................................................................................................135
3.10.3 Segment LCD Configuration.......................................................................................................................138
Chapter 4
Memory Map
4.1 Introduction...................................................................................................................................................................141
4.2 System memory map.....................................................................................................................................................141
4.2.1 Aliased bit-band regions..............................................................................................................................142
4.3 Flash Memory Map.......................................................................................................................................................143
4.3.1 Alternate Non-Volatile IRC User Trim Description....................................................................................144
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4.4 SRAM memory map.....................................................................................................................................................144
4.5 Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory maps...................................................................................145
4.5.1 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map........................................................................................145
4.5.2 Peripheral Bridge 1 (AIPS-Lite 1) Memory Map........................................................................................149
4.6 Private Peripheral Bus (PPB) memory map..................................................................................................................152
Chapter 5
Clock Distribution
5.1 Introduction...................................................................................................................................................................155
5.2 Programming model......................................................................................................................................................155
5.3 High-Level device clocking diagram............................................................................................................................155
5.4 Clock definitions...........................................................................................................................................................156
5.4.1 Device clock summary.................................................................................................................................157
5.5 Internal clocking requirements.....................................................................................................................................158
5.5.1 Clock divider values after reset....................................................................................................................159
5.5.2 VLPR mode clocking...................................................................................................................................159
5.6 Clock Gating.................................................................................................................................................................160
5.7 Module clocks...............................................................................................................................................................160
5.7.1 PMC 1-kHz LPO clock................................................................................................................................161
5.7.2 WDOG clocking..........................................................................................................................................162
5.7.3 Debug trace clock.........................................................................................................................................162
5.7.4 PORT digital filter clocking.........................................................................................................................162
5.7.5 LPTMR clocking..........................................................................................................................................163
5.7.6 FlexCAN clocking.......................................................................................................................................164
5.7.7 UART clocking............................................................................................................................................164
5.7.8 I2S/SAI clocking..........................................................................................................................................164
5.7.9 TSI clocking.................................................................................................................................................165
Chapter 6
Reset and Boot
6.1 Introduction...................................................................................................................................................................167
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6.2 Reset..............................................................................................................................................................................168
6.2.1 Power-on reset (POR)..................................................................................................................................168
6.2.2 System reset sources....................................................................................................................................168
6.2.3 MCU Resets.................................................................................................................................................172
6.2.4 Reset Pin .....................................................................................................................................................174
6.2.5 Debug resets.................................................................................................................................................174
6.3 Boot...............................................................................................................................................................................175
6.3.1 Boot sources.................................................................................................................................................175
6.3.2 Boot options.................................................................................................................................................175
6.3.3 FOPT boot options.......................................................................................................................................176
6.3.4 Boot sequence..............................................................................................................................................177
Chapter 7
Power Management
7.1 Introduction...................................................................................................................................................................179
7.2 Power modes.................................................................................................................................................................179
7.3 Entering and exiting power modes...............................................................................................................................181
7.4 Power mode transitions.................................................................................................................................................182
7.5 Power modes shutdown sequencing.............................................................................................................................183
7.6 Module Operation in Low Power Modes......................................................................................................................183
7.7 Clock Gating.................................................................................................................................................................186
Chapter 8
Security
8.1 Introduction...................................................................................................................................................................187
8.2 Flash Security...............................................................................................................................................................187
8.3 Security Interactions with other Modules.....................................................................................................................188
8.3.1 Security Interactions with EzPort................................................................................................................188
8.3.2 Security Interactions with Debug.................................................................................................................188
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Section number Title Page
Chapter 9
Debug
9.1 Introduction...................................................................................................................................................................189
9.1.1 References....................................................................................................................................................191
9.2 The Debug Port.............................................................................................................................................................191
9.2.1 JTAG-to-SWD change sequence.................................................................................................................192
9.2.2 JTAG-to-cJTAG change sequence...............................................................................................................192
9.3 Debug Port Pin Descriptions.........................................................................................................................................193
9.4 System TAP connection................................................................................................................................................193
9.4.1 IR Codes.......................................................................................................................................................193
9.5 JTAG status and control registers.................................................................................................................................194
9.5.1 MDM-AP Control Register..........................................................................................................................195
9.5.2 MDM-AP Status Register............................................................................................................................197
9.6 Debug Resets................................................................................................................................................................198
9.7 AHB-AP........................................................................................................................................................................199
9.8 ITM...............................................................................................................................................................................200
9.9 Core Trace Connectivity...............................................................................................................................................200
9.10 TPIU..............................................................................................................................................................................200
9.11 DWT.............................................................................................................................................................................200
9.12 Debug in Low Power Modes........................................................................................................................................201
9.12.1 Debug Module State in Low Power Modes.................................................................................................202
9.13 Debug & Security.........................................................................................................................................................202
Chapter 10
Signal Multiplexing and Signal Descriptions
10.1 Introduction...................................................................................................................................................................203
10.2 Signal Multiplexing Integration....................................................................................................................................203
10.2.1 Port control and interrupt module features..................................................................................................204
10.2.2 PCRn reset values for port A.......................................................................................................................204
10.2.3 Clock gating.................................................................................................................................................204
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10.2.4 Signal multiplexing constraints....................................................................................................................204
10.3 Pinout............................................................................................................................................................................205
10.3.1 K30 Signal Multiplexing and Pin Assignments...........................................................................................205
10.3.2 K30 Pinouts..................................................................................................................................................210
10.4 Module Signal Description Tables................................................................................................................................212
10.4.1 Core Modules...............................................................................................................................................212
10.4.2 System Modules...........................................................................................................................................213
10.4.3 Clock Modules.............................................................................................................................................214
10.4.4 Memories and Memory Interfaces...............................................................................................................214
10.4.5 Analog..........................................................................................................................................................215
10.4.6 Timer Modules.............................................................................................................................................216
10.4.7 Communication Interfaces...........................................................................................................................218
10.4.8 Human-Machine Interfaces (HMI)..............................................................................................................220
Chapter 11
Port control and interrupts (PORT)
11.1 Introduction...................................................................................................................................................................223
11.1.1 Overview......................................................................................................................................................223
11.1.2 External signal description...........................................................................................................................224
11.1.3 Detailed signal description...........................................................................................................................225
11.1.4 Memory map and register definition............................................................................................................225
11.1.5 Functional description..................................................................................................................................235
Chapter 12
System Integration Module (SIM)
12.1 Introduction...................................................................................................................................................................239
12.1.1 Features........................................................................................................................................................239
12.2 Memory map and register definition.............................................................................................................................240
12.2.1 System Options Register 1 (SIM_SOPT1)..................................................................................................241
12.2.2 System Options Register 2 (SIM_SOPT2)..................................................................................................242
12.2.3 System Options Register 4 (SIM_SOPT4)..................................................................................................244
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12.2.4 System Options Register 5 (SIM_SOPT5)..................................................................................................247
12.2.5 System Options Register 7 (SIM_SOPT7)..................................................................................................248
12.2.6 System Device Identification Register (SIM_SDID)...................................................................................250
12.2.7 System Clock Gating Control Register 1 (SIM_SCGC1)............................................................................251
12.2.8 System Clock Gating Control Register 2 (SIM_SCGC2)............................................................................252
12.2.9 System Clock Gating Control Register 3 (SIM_SCGC3)............................................................................253
12.2.10 System Clock Gating Control Register 4 (SIM_SCGC4)............................................................................255
12.2.11 System Clock Gating Control Register 5 (SIM_SCGC5)............................................................................257
12.2.12 System Clock Gating Control Register 6 (SIM_SCGC6)............................................................................259
12.2.13 System Clock Gating Control Register 7 (SIM_SCGC7)............................................................................261
12.2.14 System Clock Divider Register 1 (SIM_CLKDIV1)...................................................................................262
12.2.15 System Clock Divider Register 2 (SIM_CLKDIV2)...................................................................................264
12.2.16 Flash Configuration Register 1 (SIM_FCFG1)...........................................................................................265
12.2.17 Flash Configuration Register 2 (SIM_FCFG2)...........................................................................................267
12.2.18 Unique Identification Register High (SIM_UIDH).....................................................................................268
12.2.19 Unique Identification Register Mid-High (SIM_UIDMH)..........................................................................268
12.2.20 Unique Identification Register Mid Low (SIM_UIDML)...........................................................................269
12.2.21 Unique Identification Register Low (SIM_UIDL)......................................................................................269
12.3 Functional description...................................................................................................................................................269
Chapter 13
Reset Control Module (RCM)
13.1 Introduction...................................................................................................................................................................271
13.2 Reset memory map and register descriptions...............................................................................................................271
13.2.1 System Reset Status Register 0 (RCM_SRS0)............................................................................................271
13.2.2 System Reset Status Register 1 (RCM_SRS1)............................................................................................273
13.2.3 Reset Pin Filter Control register (RCM_RPFC)..........................................................................................274
13.2.4 Reset Pin Filter Width register (RCM_RPFW)...........................................................................................275
13.2.5 Mode Register (RCM_MR).........................................................................................................................277
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Chapter 14
System Mode Controller
14.1 Introduction...................................................................................................................................................................279
14.2 Modes of operation.......................................................................................................................................................279
14.3 Memory map and register descriptions.........................................................................................................................281
14.3.1 Power Mode Protection register (SMC_PMPROT).....................................................................................281
14.3.2 Power Mode Control register (SMC_PMCTRL).........................................................................................283
14.3.3 VLLS Control register (SMC_VLLSCTRL)...............................................................................................284
14.3.4 Power Mode Status register (SMC_PMSTAT)...........................................................................................285
14.4 Functional description...................................................................................................................................................286
14.4.1 Power mode transitions................................................................................................................................286
14.4.2 Power mode entry/exit sequencing..............................................................................................................289
14.4.3 Run modes....................................................................................................................................................291
14.4.4 Wait modes..................................................................................................................................................293
14.4.5 Stop modes...................................................................................................................................................294
14.4.6 Debug in low power modes.........................................................................................................................297
Chapter 15
Power Management Controller
15.1 Introduction...................................................................................................................................................................299
15.2 Features.........................................................................................................................................................................299
15.3 Low-voltage detect (LVD) system................................................................................................................................299
15.3.1 LVD reset operation.....................................................................................................................................300
15.3.2 LVD interrupt operation...............................................................................................................................300
15.3.3 Low-voltage warning (LVW) interrupt operation.......................................................................................300
15.4 I/O retention..................................................................................................................................................................301
15.5 Memory map and register descriptions.........................................................................................................................301
15.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1)........................................................301
15.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2)........................................................303
15.5.3 Regulator Status And Control register (PMC_REGSC)..............................................................................304
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Chapter 16
Low-Leakage Wakeup Unit (LLWU)
16.1 Introduction...................................................................................................................................................................307
16.1.1 Features........................................................................................................................................................307
16.1.2 Modes of operation......................................................................................................................................308
16.1.3 Block diagram..............................................................................................................................................309
16.2 LLWU signal descriptions............................................................................................................................................310
16.3 Memory map/register definition...................................................................................................................................311
16.3.1 LLWU Pin Enable 1 register (LLWU_PE1)................................................................................................312
16.3.2 LLWU Pin Enable 2 register (LLWU_PE2)................................................................................................313
16.3.3 LLWU Pin Enable 3 register (LLWU_PE3)................................................................................................314
16.3.4 LLWU Pin Enable 4 register (LLWU_PE4)................................................................................................315
16.3.5 LLWU Module Enable register (LLWU_ME)............................................................................................316
16.3.6 LLWU Flag 1 register (LLWU_F1).............................................................................................................318
16.3.7 LLWU Flag 2 register (LLWU_F2).............................................................................................................319
16.3.8 LLWU Flag 3 register (LLWU_F3).............................................................................................................321
16.3.9 LLWU Pin Filter 1 register (LLWU_FILT1)..............................................................................................323
16.3.10 LLWU Pin Filter 2 register (LLWU_FILT2)..............................................................................................324
16.3.11 LLWU Reset Enable register (LLWU_RST)...............................................................................................325
16.4 Functional description...................................................................................................................................................326
16.4.1 LLS mode.....................................................................................................................................................326
16.4.2 VLLS modes................................................................................................................................................326
16.4.3 Initialization.................................................................................................................................................327
Chapter 17
Miscellaneous Control Module (MCM)
17.1 Introduction...................................................................................................................................................................329
17.1.1 Features........................................................................................................................................................329
17.2 Memory map/register descriptions...............................................................................................................................329
17.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)................................................................330
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17.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)............................................................330
17.2.3 Control Register (MCM_CR)......................................................................................................................331
Chapter 18
Crossbar Switch (AXBS)
18.1 Introduction...................................................................................................................................................................333
18.1.1 Features........................................................................................................................................................333
18.2 Memory Map / Register Definition...............................................................................................................................334
18.2.1 Priority Registers Slave (AXBS_PRSn)......................................................................................................335
18.2.2 Control Register (AXBS_CRSn).................................................................................................................338
18.2.3 Master General Purpose Control Register (AXBS_MGPCRn)...................................................................340
18.3 Functional Description..................................................................................................................................................340
18.3.1 General operation.........................................................................................................................................340
18.3.2 Register coherency.......................................................................................................................................341
18.3.3 Arbitration....................................................................................................................................................342
18.4 Initialization/application information...........................................................................................................................345
Chapter 19
Peripheral Bridge (AIPS-Lite)
19.1 Introduction...................................................................................................................................................................347
19.1.1 Features........................................................................................................................................................347
19.1.2 General operation.........................................................................................................................................347
19.2 Memory map/register definition...................................................................................................................................348
19.2.1 Master Privilege Register A (AIPSx_MPRA).............................................................................................350
19.2.2 Peripheral Access Control Register (AIPSx_PACRn).................................................................................352
19.2.3 Peripheral Access Control Register (AIPSx_PACRn).................................................................................357
19.3 Functional description...................................................................................................................................................362
19.3.1 Access support.............................................................................................................................................362
Chapter 20
Direct Memory Access Multiplexer (DMAMUX)
20.1 Introduction...................................................................................................................................................................363
20.1.1 Overview......................................................................................................................................................363
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20.1.2 Features........................................................................................................................................................364
20.1.3 Modes of operation......................................................................................................................................364
20.2 External signal description............................................................................................................................................365
20.3 Memory map/register definition...................................................................................................................................365
20.3.1 Channel Configuration register (DMAMUX_CHCFGn)............................................................................366
20.4 Functional description...................................................................................................................................................367
20.4.1 DMA channels with periodic triggering capability......................................................................................367
20.4.2 DMA channels with no triggering capability...............................................................................................369
20.4.3 "Always enabled" DMA sources.................................................................................................................369
20.5 Initialization/application information...........................................................................................................................370
20.5.1 Reset.............................................................................................................................................................371
20.5.2 Enabling and configuring sources................................................................................................................371
Chapter 21
Direct Memory Access Controller (eDMA)
21.1 Introduction...................................................................................................................................................................375
21.1.1 Block diagram..............................................................................................................................................375
21.1.2 Block parts...................................................................................................................................................376
21.1.3 Features........................................................................................................................................................378
21.2 Modes of operation.......................................................................................................................................................379
21.3 Memory map/register definition...................................................................................................................................379
21.3.1 Control Register (DMA_CR).......................................................................................................................391
21.3.2 Error Status Register (DMA_ES)................................................................................................................392
21.3.3 Enable Request Register (DMA_ERQ).......................................................................................................394
21.3.4 Enable Error Interrupt Register (DMA_EEI)...............................................................................................397
21.3.5 Clear Enable Error Interrupt Register (DMA_CEEI)..................................................................................399
21.3.6 Set Enable Error Interrupt Register (DMA_SEEI)......................................................................................400
21.3.7 Clear Enable Request Register (DMA_CERQ)...........................................................................................401
21.3.8 Set Enable Request Register (DMA_SERQ)...............................................................................................402
21.3.9 Clear DONE Status Bit Register (DMA_CDNE)........................................................................................403
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21.3.10 Set START Bit Register (DMA_SSRT)......................................................................................................404
21.3.11 Clear Error Register (DMA_CERR)............................................................................................................405
21.3.12 Clear Interrupt Request Register (DMA_CINT).........................................................................................406
21.3.13 Interrupt Request Register (DMA_INT)......................................................................................................406
21.3.14 Error Register (DMA_ERR)........................................................................................................................409
21.3.15 Hardware Request Status Register (DMA_HRS)........................................................................................411
21.3.16 Channel n Priority Register (DMA_DCHPRIn)..........................................................................................414
21.3.17 TCD Source Address (DMA_TCDn_SADDR)...........................................................................................415
21.3.18 TCD Signed Source Address Offset (DMA_TCDn_SOFF)........................................................................415
21.3.19 TCD Transfer Attributes (DMA_TCDn_ATTR).........................................................................................416
21.3.20 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCDn_NBYTES_MLNO).................................417
21.3.21 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
(DMA_TCDn_NBYTES_MLOFFNO).......................................................................................................417
21.3.22 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
(DMA_TCDn_NBYTES_MLOFFYES).....................................................................................................418
21.3.23 TCD Last Source Address Adjustment (DMA_TCDn_SLAST).................................................................420
21.3.24 TCD Destination Address (DMA_TCDn_DADDR)...................................................................................420
21.3.25 TCD Signed Destination Address Offset (DMA_TCDn_DOFF)................................................................421
21.3.26 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_CITER_ELINKYES)...........................................................................................................421
21.3.27 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_CITER_ELINKNO)............................................................................................................422
21.3.28 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCDn_DLASTSGA)..........423
21.3.29 TCD Control and Status (DMA_TCDn_CSR)............................................................................................424
21.3.30 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_BITER_ELINKYES)...........................................................................................................426
21.3.31 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_BITER_ELINKNO)............................................................................................................427
21.4 Functional description...................................................................................................................................................428
21.4.1 eDMA basic data flow.................................................................................................................................428
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21.4.2 Error reporting and handling........................................................................................................................431
21.4.3 Channel preemption.....................................................................................................................................433
21.4.4 Performance.................................................................................................................................................433
21.5 Initialization/application information...........................................................................................................................438
21.5.1 eDMA initialization.....................................................................................................................................438
21.5.2 Programming errors.....................................................................................................................................440
21.5.3 Arbitration mode considerations..................................................................................................................440
21.5.4 Performing DMA transfers (examples)........................................................................................................441
21.5.5 Monitoring transfer descriptor status...........................................................................................................445
21.5.6 Channel Linking...........................................................................................................................................446
21.5.7 Dynamic programming................................................................................................................................448
Chapter 22
External Watchdog Monitor (EWM)
22.1 Introduction...................................................................................................................................................................453
22.1.1 Features........................................................................................................................................................453
22.1.2 Modes of Operation.....................................................................................................................................454
22.1.3 Block Diagram.............................................................................................................................................455
22.2 EWM Signal Descriptions............................................................................................................................................456
22.3 Memory Map/Register Definition.................................................................................................................................456
22.3.1 Control Register (EWM_CTRL).................................................................................................................456
22.3.2 Service Register (EWM_SERV)..................................................................................................................457
22.3.3 Compare Low Register (EWM_CMPL)......................................................................................................457
22.3.4 Compare High Register (EWM_CMPH).....................................................................................................458
22.4 Functional Description..................................................................................................................................................459
22.4.1 The EWM_out Signal..................................................................................................................................459
22.4.2 The EWM_in Signal....................................................................................................................................459
22.4.3 EWM Counter..............................................................................................................................................460
22.4.4 EWM Compare Registers............................................................................................................................460
22.4.5 EWM Refresh Mechanism...........................................................................................................................461
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22.4.6 EWM Interrupt.............................................................................................................................................461
Chapter 23
Watchdog Timer (WDOG)
23.1 Introduction...................................................................................................................................................................463
23.2 Features.........................................................................................................................................................................463
23.3 Functional overview......................................................................................................................................................465
23.3.1 Unlocking and updating the watchdog.........................................................................................................466
23.3.2 Watchdog configuration time (WCT)..........................................................................................................467
23.3.3 Refreshing the watchdog..............................................................................................................................468
23.3.4 Windowed mode of operation......................................................................................................................468
23.3.5 Watchdog disabled mode of operation.........................................................................................................468
23.3.6 Low-power modes of operation...................................................................................................................469
23.3.7 Debug modes of operation...........................................................................................................................469
23.4 Testing the watchdog....................................................................................................................................................470
23.4.1 Quick test.....................................................................................................................................................470
23.4.2 Byte test........................................................................................................................................................471
23.5 Backup reset generator..................................................................................................................................................472
23.6 Generated resets and interrupts.....................................................................................................................................472
23.7 Memory map and register definition.............................................................................................................................473
23.7.1 Watchdog Status and Control Register High (WDOG_STCTRLH)...........................................................474
23.7.2 Watchdog Status and Control Register Low (WDOG_STCTRLL)............................................................475
23.7.3 Watchdog Time-out Value Register High (WDOG_TOVALH).................................................................476
23.7.4 Watchdog Time-out Value Register Low (WDOG_TOVALL)..................................................................476
23.7.5 Watchdog Window Register High (WDOG_WINH)..................................................................................477
23.7.6 Watchdog Window Register Low (WDOG_WINL)...................................................................................477
23.7.7 Watchdog Refresh register (WDOG_REFRESH).......................................................................................478
23.7.8 Watchdog Unlock register (WDOG_UNLOCK).........................................................................................478
23.7.9 Watchdog Timer Output Register High (WDOG_TMROUTH).................................................................478
23.7.10 Watchdog Timer Output Register Low (WDOG_TMROUTL)..................................................................479
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23.7.11 Watchdog Reset Count register (WDOG_RSTCNT)..................................................................................479
23.7.12 Watchdog Prescaler register (WDOG_PRESC)..........................................................................................480
23.8 Watchdog operation with 8-bit access..........................................................................................................................480
23.8.1 General guideline.........................................................................................................................................480
23.8.2 Refresh and unlock operations with 8-bit access.........................................................................................480
23.9 Restrictions on watchdog operation..............................................................................................................................481
Chapter 24
Multipurpose Clock Generator (MCG)
24.1 Introduction...................................................................................................................................................................485
24.1.1 Features........................................................................................................................................................485
24.1.2 Modes of Operation.....................................................................................................................................489
24.2 External Signal Description..........................................................................................................................................489
24.3 Memory Map/Register Definition.................................................................................................................................489
24.3.1 MCG Control 1 Register (MCG_C1)...........................................................................................................490
24.3.2 MCG Control 2 Register (MCG_C2)...........................................................................................................491
24.3.3 MCG Control 3 Register (MCG_C3)...........................................................................................................492
24.3.4 MCG Control 4 Register (MCG_C4)...........................................................................................................493
24.3.5 MCG Control 5 Register (MCG_C5)...........................................................................................................494
24.3.6 MCG Control 6 Register (MCG_C6)...........................................................................................................495
24.3.7 MCG Status Register (MCG_S)..................................................................................................................497
24.3.8 MCG Status and Control Register (MCG_SC)............................................................................................498
24.3.9 MCG Auto Trim Compare Value High Register (MCG_ATCVH)............................................................500
24.3.10 MCG Auto Trim Compare Value Low Register (MCG_ATCVL)..............................................................500
24.3.11 MCG Control 7 Register (MCG_C7)...........................................................................................................500
24.3.12 MCG Control 8 Register (MCG_C8)...........................................................................................................501
24.4 Functional description...................................................................................................................................................502
24.4.1 MCG mode state diagram............................................................................................................................502
24.4.2 Low Power Bit Usage..................................................................................................................................507
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24.4.3 MCG Internal Reference Clocks..................................................................................................................507
24.4.4 External Reference Clock............................................................................................................................507
24.4.5 MCG Fixed frequency clock .......................................................................................................................508
24.4.6 MCG PLL clock ..........................................................................................................................................508
24.4.7 MCG Auto TRIM (ATM)............................................................................................................................509
24.5 Initialization / Application information........................................................................................................................510
24.5.1 MCG module initialization sequence...........................................................................................................510
24.5.2 Using a 32.768 kHz reference......................................................................................................................512
24.5.3 MCG mode switching..................................................................................................................................513
Chapter 25
Oscillator (OSC)
25.1 Introduction...................................................................................................................................................................523
25.2 Features and Modes......................................................................................................................................................523
25.3 Block Diagram..............................................................................................................................................................524
25.4 OSC Signal Descriptions..............................................................................................................................................524
25.5 External Crystal / Resonator Connections....................................................................................................................525
25.6 External Clock Connections.........................................................................................................................................526
25.7 Memory Map/Register Definitions...............................................................................................................................527
25.7.1 OSC Memory Map/Register Definition.......................................................................................................527
25.8 Functional Description..................................................................................................................................................528
25.8.1 OSC Module States......................................................................................................................................528
25.8.2 OSC Module Modes.....................................................................................................................................530
25.8.3 Counter.........................................................................................................................................................532
25.8.4 Reference Clock Pin Requirements.............................................................................................................532
25.9 Reset..............................................................................................................................................................................532
25.10 Low Power Modes Operation.......................................................................................................................................533
25.11 Interrupts.......................................................................................................................................................................533
K30 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
20 Freescale Semiconductor, Inc.