NXP Semiconductors MK30DX64VMC7 User manual

K30 Sub-Family Reference Manual
Supports: MK30DX128VLL7, MK30DX256VLL7, MK30DX64VMC7,
MK30DX128VMC7, MK30DX256VMC7
Document Number: K30P100M72SF1RM
Rev. 1.1, Dec 2012

K30 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
2 Freescale Semiconductor, Inc.

Contents
Section number Title Page
Chapter 1
About This Document
1.1 Overview.......................................................................................................................................................................49
1.1.1 Purpose.........................................................................................................................................................49
1.1.2 Audience......................................................................................................................................................49
1.2 Conventions..................................................................................................................................................................49
1.2.1 Numbering systems......................................................................................................................................49
1.2.2 Typographic notation...................................................................................................................................50
1.2.3 Special terms................................................................................................................................................50
Chapter 2
Introduction
2.1 Overview.......................................................................................................................................................................51
2.2 Module Functional Categories......................................................................................................................................51
2.2.1 ARM Cortex-M4 Core Modules..................................................................................................................52
2.2.2 System Modules...........................................................................................................................................53
2.2.3 Memories and Memory Interfaces...............................................................................................................54
2.2.4 Clocks...........................................................................................................................................................54
2.2.5 Security and Integrity modules....................................................................................................................55
2.2.6 Analog modules...........................................................................................................................................55
2.2.7 Timer modules.............................................................................................................................................56
2.2.8 Communication interfaces...........................................................................................................................57
2.2.9 Human-machine interfaces..........................................................................................................................57
2.3 Orderable part numbers.................................................................................................................................................58
Chapter 3
Chip Configuration
3.1 Introduction...................................................................................................................................................................59
K30 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc. 3

Section number Title Page
3.2 Core modules................................................................................................................................................................59
3.2.1 ARM Cortex-M4 Core Configuration..........................................................................................................59
3.2.2 Nested Vectored Interrupt Controller (NVIC) Configuration......................................................................61
3.2.3 Asynchronous Wake-up Interrupt Controller (AWIC) Configuration.........................................................67
3.2.4 JTAG Controller Configuration...................................................................................................................69
3.3 System modules............................................................................................................................................................69
3.3.1 SIM Configuration.......................................................................................................................................69
3.3.2 System Mode Controller (SMC) Configuration...........................................................................................70
3.3.3 PMC Configuration......................................................................................................................................71
3.3.4 Low-Leakage Wake-up Unit (LLWU) Configuration.................................................................................71
3.3.5 MCM Configuration....................................................................................................................................73
3.3.6 Crossbar Switch Configuration....................................................................................................................74
3.3.7 Peripheral Bridge Configuration..................................................................................................................75
3.3.8 DMA request multiplexer configuration......................................................................................................76
3.3.9 DMA Controller Configuration...................................................................................................................79
3.3.10 External Watchdog Monitor (EWM) Configuration....................................................................................80
3.3.11 Watchdog Configuration..............................................................................................................................82
3.4 Clock modules..............................................................................................................................................................83
3.4.1 MCG Configuration.....................................................................................................................................83
3.4.2 OSC Configuration......................................................................................................................................84
3.4.3 RTC OSC configuration...............................................................................................................................85
3.5 Memories and memory interfaces.................................................................................................................................85
3.5.1 Flash Memory Configuration.......................................................................................................................85
3.5.2 Flash Memory Controller Configuration.....................................................................................................88
3.5.3 SRAM Configuration...................................................................................................................................89
3.5.4 SRAM Controller Configuration.................................................................................................................92
K30 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
4 Freescale Semiconductor, Inc.

Section number Title Page
3.5.5 System Register File Configuration.............................................................................................................93
3.5.6 VBAT Register File Configuration..............................................................................................................94
3.5.7 EzPort Configuration...................................................................................................................................94
3.6 Security.........................................................................................................................................................................96
3.6.1 CRC Configuration......................................................................................................................................96
K30 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc. 5

Section number Title Page
3.7 Analog...........................................................................................................................................................................96
3.7.1 16-bit SAR ADC with PGA Configuration.................................................................................................96
3.7.2 CMP Configuration......................................................................................................................................106
3.7.3 12-bit DAC Configuration...........................................................................................................................108
3.7.4 VREF Configuration....................................................................................................................................109
3.8 Timers...........................................................................................................................................................................110
3.8.1 PDB Configuration......................................................................................................................................110
3.8.2 FlexTimer Configuration.............................................................................................................................113
3.8.3 PIT Configuration........................................................................................................................................117
3.8.4 Low-power timer configuration...................................................................................................................118
3.8.5 CMT Configuration......................................................................................................................................120
3.8.6 RTC configuration.......................................................................................................................................121
3.9 Communication interfaces............................................................................................................................................122
3.9.1 CAN Configuration......................................................................................................................................122
3.9.2 SPI configuration.........................................................................................................................................124
3.9.3 I2C Configuration........................................................................................................................................128
3.9.4 UART Configuration...................................................................................................................................128
3.9.5 I2S configuration..........................................................................................................................................131
3.10 Human-machine interfaces...........................................................................................................................................134
3.10.1 GPIO configuration......................................................................................................................................134
3.10.2 TSI Configuration........................................................................................................................................135
3.10.3 Segment LCD Configuration.......................................................................................................................138
Chapter 4
Memory Map
4.1 Introduction...................................................................................................................................................................141
4.2 System memory map.....................................................................................................................................................141
4.2.1 Aliased bit-band regions..............................................................................................................................142
4.3 Flash Memory Map.......................................................................................................................................................143
4.3.1 Alternate Non-Volatile IRC User Trim Description....................................................................................144
K30 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
6 Freescale Semiconductor, Inc.

Section number Title Page
4.4 SRAM memory map.....................................................................................................................................................144
4.5 Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory maps...................................................................................145
4.5.1 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map........................................................................................145
4.5.2 Peripheral Bridge 1 (AIPS-Lite 1) Memory Map........................................................................................149
4.6 Private Peripheral Bus (PPB) memory map..................................................................................................................152
Chapter 5
Clock Distribution
5.1 Introduction...................................................................................................................................................................155
5.2 Programming model......................................................................................................................................................155
5.3 High-Level device clocking diagram............................................................................................................................155
5.4 Clock definitions...........................................................................................................................................................156
5.4.1 Device clock summary.................................................................................................................................157
5.5 Internal clocking requirements.....................................................................................................................................158
5.5.1 Clock divider values after reset....................................................................................................................159
5.5.2 VLPR mode clocking...................................................................................................................................159
5.6 Clock Gating.................................................................................................................................................................160
5.7 Module clocks...............................................................................................................................................................160
5.7.1 PMC 1-kHz LPO clock................................................................................................................................161
5.7.2 WDOG clocking..........................................................................................................................................162
5.7.3 Debug trace clock.........................................................................................................................................162
5.7.4 PORT digital filter clocking.........................................................................................................................162
5.7.5 LPTMR clocking..........................................................................................................................................163
5.7.6 FlexCAN clocking.......................................................................................................................................164
5.7.7 UART clocking............................................................................................................................................164
5.7.8 I2S/SAI clocking..........................................................................................................................................164
5.7.9 TSI clocking.................................................................................................................................................165
Chapter 6
Reset and Boot
6.1 Introduction...................................................................................................................................................................167
K30 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc. 7

Section number Title Page
6.2 Reset..............................................................................................................................................................................168
6.2.1 Power-on reset (POR)..................................................................................................................................168
6.2.2 System reset sources....................................................................................................................................168
6.2.3 MCU Resets.................................................................................................................................................172
6.2.4 Reset Pin .....................................................................................................................................................174
6.2.5 Debug resets.................................................................................................................................................174
6.3 Boot...............................................................................................................................................................................175
6.3.1 Boot sources.................................................................................................................................................175
6.3.2 Boot options.................................................................................................................................................175
6.3.3 FOPT boot options.......................................................................................................................................176
6.3.4 Boot sequence..............................................................................................................................................177
Chapter 7
Power Management
7.1 Introduction...................................................................................................................................................................179
7.2 Power modes.................................................................................................................................................................179
7.3 Entering and exiting power modes...............................................................................................................................181
7.4 Power mode transitions.................................................................................................................................................182
7.5 Power modes shutdown sequencing.............................................................................................................................183
7.6 Module Operation in Low Power Modes......................................................................................................................183
7.7 Clock Gating.................................................................................................................................................................186
Chapter 8
Security
8.1 Introduction...................................................................................................................................................................187
8.2 Flash Security...............................................................................................................................................................187
8.3 Security Interactions with other Modules.....................................................................................................................188
8.3.1 Security Interactions with EzPort................................................................................................................188
8.3.2 Security Interactions with Debug.................................................................................................................188
K30 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
8 Freescale Semiconductor, Inc.

Section number Title Page
Chapter 9
Debug
9.1 Introduction...................................................................................................................................................................189
9.1.1 References....................................................................................................................................................191
9.2 The Debug Port.............................................................................................................................................................191
9.2.1 JTAG-to-SWD change sequence.................................................................................................................192
9.2.2 JTAG-to-cJTAG change sequence...............................................................................................................192
9.3 Debug Port Pin Descriptions.........................................................................................................................................193
9.4 System TAP connection................................................................................................................................................193
9.4.1 IR Codes.......................................................................................................................................................193
9.5 JTAG status and control registers.................................................................................................................................194
9.5.1 MDM-AP Control Register..........................................................................................................................195
9.5.2 MDM-AP Status Register............................................................................................................................197
9.6 Debug Resets................................................................................................................................................................198
9.7 AHB-AP........................................................................................................................................................................199
9.8 ITM...............................................................................................................................................................................200
9.9 Core Trace Connectivity...............................................................................................................................................200
9.10 TPIU..............................................................................................................................................................................200
9.11 DWT.............................................................................................................................................................................200
9.12 Debug in Low Power Modes........................................................................................................................................201
9.12.1 Debug Module State in Low Power Modes.................................................................................................202
9.13 Debug & Security.........................................................................................................................................................202
Chapter 10
Signal Multiplexing and Signal Descriptions
10.1 Introduction...................................................................................................................................................................203
10.2 Signal Multiplexing Integration....................................................................................................................................203
10.2.1 Port control and interrupt module features..................................................................................................204
10.2.2 PCRn reset values for port A.......................................................................................................................204
10.2.3 Clock gating.................................................................................................................................................204
K30 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc. 9

Section number Title Page
10.2.4 Signal multiplexing constraints....................................................................................................................204
10.3 Pinout............................................................................................................................................................................205
10.3.1 K30 Signal Multiplexing and Pin Assignments...........................................................................................205
10.3.2 K30 Pinouts..................................................................................................................................................210
10.4 Module Signal Description Tables................................................................................................................................212
10.4.1 Core Modules...............................................................................................................................................212
10.4.2 System Modules...........................................................................................................................................213
10.4.3 Clock Modules.............................................................................................................................................214
10.4.4 Memories and Memory Interfaces...............................................................................................................214
10.4.5 Analog..........................................................................................................................................................215
10.4.6 Timer Modules.............................................................................................................................................216
10.4.7 Communication Interfaces...........................................................................................................................218
10.4.8 Human-Machine Interfaces (HMI)..............................................................................................................220
Chapter 11
Port control and interrupts (PORT)
11.1 Introduction...................................................................................................................................................................223
11.1.1 Overview......................................................................................................................................................223
11.1.2 External signal description...........................................................................................................................224
11.1.3 Detailed signal description...........................................................................................................................225
11.1.4 Memory map and register definition............................................................................................................225
11.1.5 Functional description..................................................................................................................................235
Chapter 12
System Integration Module (SIM)
12.1 Introduction...................................................................................................................................................................239
12.1.1 Features........................................................................................................................................................239
12.2 Memory map and register definition.............................................................................................................................240
12.2.1 System Options Register 1 (SIM_SOPT1)..................................................................................................241
12.2.2 System Options Register 2 (SIM_SOPT2)..................................................................................................242
12.2.3 System Options Register 4 (SIM_SOPT4)..................................................................................................244
K30 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
10 Freescale Semiconductor, Inc.