NXP Semiconductors UM10204 User manual

UM10204
I2C-bus specification and user manual
Rev. 5 — 9 October 2012 User manual
Document information
Info Content
Keywords I2C, I2C-bus, Standard-mode, Fast-mode, Fast-mode Plus, Fm+,
Ultra Fast-mode, UFm, High Speed, Hs, inter-IC, SDA, SCL, USDA, USCL
Abstract Philips Semiconductors (now NXP Semiconductors) developed a simple
bidirectional 2-wire bus for efficient inter-IC control. This bus is called the
Inter-IC or I2C-bus. Only two bus lines are required: a serial data line
(SDA) and a serial clock line (SCL). Serial, 8-bit oriented, bidirectional
data transfers can be made at up to 100 kbit/s in the Standard-mode, up to
400 kbit/sin the Fast-mode, up to 1 Mbit/s in the Fast-mode Plus (Fm+), or
up to 3.4 Mbit/s in the High-speed mode. The Ultra Fast-mode is a
uni-directional mode with data transfers of up to 5 Mbit/s.

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For more information, please visit: http://www.nxp.com
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I2C-bus specification and user manual
Revision history
Rev Date Description
v.5 20121009 User manual; fifth release
Modifications: •Section 3.1.7 “Clock synchronization”, first paragraph, first sentence changed from “idle bus”
to “free bus”
•Section 3.1.8 “Arbitration”, third paragraph, second sentence changed from “the bus is idle”
to “the bus is free”
•Section 3.1.12 “Reserved addresses”:
–Table 3 “Reserved addresses”, slave address 1111 1XX: R/W bit changed from “X” to “1”;
description changed from “reserved for future purposes” to “device ID”
–deleted (old) third paragraph
•Section 3.1.17 “Device ID”:
–in numbered list following second paragraph: “START command” changed to “START
condition”
–in numbered list following second paragraph: “STOP command” changed to “STOP condition”
–in Remark paragraph: “NACK command” changed to “NACK”
–Table 4 “Assigned manufacturer IDs”updated
•Section 3.2.8 “10-bit addressing”:
–fifth paragraph (bullet item): “NA1” changed to “W” in third sentence; deleted “(NA2)” from
fourth sentence
–Figure 29 “A master-transmitter addresses a slave-receiver with a 10-bit address”modified
•Section 3.2.9 “Reserved addresses in UFm”: deleted (old) third paragraph
•Section 7.2.1 “Reduced fSCL”, third paragraph corrected from “30 % to 30 %, or 70 % to 70 %”
to “30 % to 70 %, or 70 % to 30 %”
v.4 20120213 User manual Rev. 4
v.3 20070619 Many of today’s applications require longer buses and/or faster speeds. Fast-mode Plus was
introduced to meet this need by increasing drive strength by as much as 10×and increasing the data
rate to 1 Mbit/s while maintaining downward compatibility to Fast-mode and Standard-mode speeds
and software commands.
v2.1 2000 Version 2.1 of the I2C-bus specification
v2.0 1998 The I2C-bus has become a de facto world standard that is now implemented in over 1000 different ICs
and licensed to more than 50 companies. Many of today’s applications, however, require higher bus
speeds and lower supply voltages. This updated version of the I2C-bus specification meets those
requirements.
v1.0 1992 Version 1.0 of the I2C-bus specification
Original 1982 first release

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I2C-bus specification and user manual
1. Introduction
The I2C-bus is a de facto world standard that is now implemented in over 1000 different
ICs manufactured by more than 50 companies. Additionally, the versatile I2C-bus is used
in various control architectures such as System Management Bus (SMBus), Power
Management Bus (PMBus), Intelligent Platform Management Interface (IPMI), Display
Data Channel (DDC) and Advanced Telecom Computing Architecture (ATCA).
This document assists device and system designers to understand how the I2C-bus works
and implement a working application. Various operating modes are described. It contains
a comprehensive introduction to the I2C-bus data transfer, handshaking and bus
arbitration schemes. Detailed sections cover the timing and electrical specifications for the
I2C-bus in each of its operating modes.
Designers of I2C-compatible chips should use this document as a reference and ensure
that new devices meet all limits specified in this document. Designers of systems that
include I2C devices should review this document and also refer to individual component
data sheets.
2. I2C-bus features
In consumer electronics, telecommunications and industrial electronics, there are often
many similarities between seemingly unrelated designs. For example, nearly every
system includes:
•Some intelligent control, usually a single-chip microcontroller
•General-purpose circuits like LCD and LED drivers, remote I/O ports, RAM,
EEPROM, real-time clocks or A/D and D/A converters
•Application-oriented circuits such as digital tuning and signal processing circuits for
radio and video systems, temperature sensors, and smart cards
To exploit these similarities to the benefit of both systems designers and equipment
manufacturers, as well as to maximize hardware efficiency and circuit simplicity, Philips
Semiconductors (now NXP Semiconductors) developed a simple bidirectional 2-wire bus
for efficient inter-IC control. This bus is called the Inter IC or I2C-bus. All I2C-bus
compatible devices incorporate an on-chip interface which allows them to communicate
directly with each other via the I2C-bus. This design concept solves the many interfacing
problems encountered when designing digital control circuits.
Here are some of the features of the I2C-bus:
•Only two bus lines are required; a serial data line (SDA) and a serial clock line (SCL).
•Each device connected to the bus is software addressable by a unique address and
simple master/slave relationships exist at all times; masters can operate as
master-transmitters or as master-receivers.
•It is a true multi-master bus including collision detection and arbitration to prevent data
corruption if two or more masters simultaneously initiate data transfer.
•Serial, 8-bit oriented, bidirectional data transfers can be made at up to 100 kbit/s in
the Standard-mode, up to 400 kbit/s in the Fast-mode, up to 1 Mbit/s in Fast-mode
Plus, or up to 3.4 Mbit/s in the High-speed mode.

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I2C-bus specification and user manual
•Serial, 8-bit oriented, unidirectional data transfers up to 5 Mbit/s in Ultra Fast-mode
•On-chip filtering rejects spikes on the bus data line to preserve data integrity.
•The number of ICs that can be connected to the same bus is limited only by a
maximum bus capacitance. More capacitance may be allowed under some
conditions. Refer to Section 7.2.
Figure 1 shows an example of I2C-bus applications.
2.1 Designer benefits
I2C-bus compatible ICs allow a system design to progress rapidly directly from a
functional block diagram to a prototype. Moreover, since they ‘clip’ directly onto the
I2C-bus without any additional external interfacing, they allow a prototype system to be
modified or upgraded simply by ‘clipping’ or ‘unclipping’ ICs to or from the bus.
Here are some of the features of I2C-bus compatible ICs that are particularly attractive to
designers:
•Functional blocks on the block diagram correspond with the actual ICs; designs
proceed rapidly from block diagram to final schematic.
•No need to design bus interfaces because the I2C-bus interface is already integrated
on-chip.
Fig 1. Example of I2C-bus applications
I2C
A/D or D/A
Converters
I2C
General Purpose
I/O Expanders
I2C
LED Controllers
VDD4
I2C
Repeaters/
Hubs/Extenders
I2C
DIP Switches
VDD5
I2C
Slave
VDD0
VDD1
PCA9541
I2C
Master Selector/
Demux
I2C
Multiplexers
and Switches
VDD2
I2C Port
via HW or
Bit Banging
I2C
Bus Controllers
MCUs
8MCUs
I2C
Serial EEPROMs
LCD Drivers
(with I2C)
I2C
Real Time Clock/
Calendars
VDD3
I2C
Temperature
Sensors
Bridges
(with I2C)
SPI
UART
USB
002aac858

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I2C-bus specification and user manual
•Integrated addressing and data-transfer protocol allow systems to be completely
software-defined.
•The same IC types can often be used in many different applications.
•Design-time reduces as designers quickly become familiar with the frequently used
functional blocks represented by I2C-bus compatible ICs.
•ICs can be added to or removed from a system without affecting any other circuits on
the bus.
•Fault diagnosis and debugging are simple; malfunctions can be immediately traced.
•Software development time can be reduced by assembling a library of reusable
software modules.
In addition to these advantages, the CMOS ICs in the I2C-bus compatible range offer
designers special features which are particularly attractive for portable equipment and
battery-backed systems.
They all have:
•Extremely low current consumption
•High noise immunity
•Wide supply voltage range
•Wide operating temperature range.
2.2 Manufacturer benefits
I2C-bus compatible ICs not only assist designers, they also give a wide range of benefits
to equipment manufacturers because:
•The simple 2-wire serial I2C-bus minimizes interconnections so ICs have fewer pins
and there are not so many PCB tracks; result — smaller and less expensive PCBs.
•The completely integrated I2C-bus protocol eliminates the need for address decoders
and other ‘glue logic’.
•The multi-master capability of the I2C-bus allows rapid testing and alignment of
end-user equipment via external connections to an assembly line.
•The availability of I2C-bus compatible ICs in various leadless packages reduces
space requirements even more.
These are just some of the benefits. In addition, I2C-bus compatible ICs increase system
design flexibility by allowing simple construction of equipment variants and easy
upgrading to keep designs up-to-date. In this way, an entire family of equipment can be
developed around a basic model. Upgrades for new equipment, or enhanced-feature
models (that is, extended memory, remote control, etc.) can then be produced simply by
clipping the appropriate ICs onto the bus. If a larger ROM is needed, it is simply a matter
of selecting a microcontroller with a larger ROM from our comprehensive range. As new
ICs supersede older ones, it is easy to add new features to equipment or to increase its
performance by simply unclipping the outdated IC from the bus and clipping on its
successor.

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I2C-bus specification and user manual
2.3 IC designer benefits
Designers of microcontrollers are frequently under pressure to conserve output pins. The
I2C protocol allows connection of a wide variety of peripherals without the need for
separate addressing or chip enable signals. Additionally, a microcontroller that includes an
I2C interface is more successful in the marketplace due to the wide variety of existing
peripheral devices available.
3. The I2C-bus protocol
3.1 Standard-mode, Fast-mode and Fast-mode Plus I2C-bus protocols
Two wires, serial data (SDA) and serial clock (SCL), carry information between the
devices connected to the bus. Each device is recognized by a unique address (whether
it is a microcontroller, LCD driver, memory or keyboard interface) and can operate as
either a transmitter or receiver, depending on the function of the device. An LCD driver
may be only a receiver, whereas a memory can both receive and transmit data. In addition
to transmitters and receivers, devices can also be considered as masters or slaves when
performing data transfers (see Table 1). A master is the device which initiates a data
transfer on the bus and generates the clock signals to permit that transfer. At that time,
any device addressed is considered a slave.
The I2C-bus is a multi-master bus. This means that more than one device capable of
controlling the bus can be connected to it. As masters are usually microcontrollers, let us
consider the case of a data transfer between two microcontrollers connected to the
I2C-bus (see Figure 2).
Table 1. Definition of I2C-bus terminology
Term Description
Transmitter the device which sends data to the bus
Receiver the device which receives data from the bus
Master the device which initiates a transfer, generates clock signals and
terminates a transfer
Slave the device addressed by a master
Multi-master more than one master can attempt to control the bus at the same time
without corrupting the message
Arbitration procedure to ensure that, if more than one master simultaneously tries to
control the bus, only one is allowed to do so and the winning message is
not corrupted
Synchronization procedure to synchronize the clock signals of two or more devices

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I2C-bus specification and user manual
This example highlights the master-slave and receiver-transmitter relationships found on
the I2C-bus. Note that these relationships are not permanent, but only depend on the
direction of data transfer at that time. The transfer of data would proceed as follows:
1. Suppose microcontroller A wants to send information to microcontroller B:
–microcontroller A (master), addresses microcontroller B (slave)
–microcontroller A (master-transmitter), sends data to microcontroller B
(slave-receiver)
–microcontroller A terminates the transfer.
2. If microcontroller A wants to receive information from microcontroller B:
–microcontroller A (master) addresses microcontroller B (slave)
–microcontroller A (master-receiver) receives data from microcontroller B
(slave-transmitter)
–microcontroller A terminates the transfer.
Even in this case, the master (microcontroller A) generates the timing and terminates the
transfer.
The possibility of connecting more than one microcontroller to the I2C-bus means that
more than one master could try to initiate a data transfer at the same time. To avoid the
chaos that might ensue from such an event, an arbitration procedurehas been developed.
This procedure relies on the wired-AND connection of all I2C interfaces to the I2C-bus.
If two or more masters try to put information onto the bus, the first to produce a ‘one’ when
the other produces a ‘zero’ loses the arbitration. The clock signals during arbitration are a
synchronized combination of the clocks generated by the masters using the wired-AND
connection to the SCL line (for more detailed information concerning arbitration see
Section 3.1.8).
Generation of clock signals on the I2C-bus is always the responsibility of master devices;
each master generates its own clock signals when transferring data on the bus. Bus clock
signals from a master can only be altered when they are stretched by a slow slave device
holding down the clock line or by another master when arbitration occurs.
Table 2 summarizes the use of mandatory and optional portions of the I2C-bus
specification and which system configurations use them.
Fig 2. Example of an I2C-bus configuration using two microcontrollers
mbc645
SDA
SCL
MICRO -
CONTROLLER
A
STATIC
RAM OR
EEPROM
LCD
DRIVER
GATE
ARRAY ADC
MICRO -
CONTROLLER
B

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[1] Also refers to a master acting as a slave.
[2] Clock stretching is a feature of some slaves. If no slaves in a system can stretch the clock (hold SCL LOW),
the master need not be designed to handle this procedure.
[3] ‘Bit banging’ (software emulation) multi-master systems should consider a START byte. See
Section 3.1.15.
3.1.1 SDA and SCL signals
Both SDA and SCL are bidirectional lines, connected to a positive supply voltage via a
current-source or pull-up resistor (see Figure 3). When the bus is free, both lines are
HIGH. The output stages of devices connected to the bus must have an open-drain or
open-collector to perform the wired-AND function. Data on the I2C-bus can be transferred
at rates of up to 100 kbit/s in the Standard-mode, up to 400 kbit/s in the Fast-mode, up to
1 Mbit/s in Fast-mode Plus, or up to 3.4 Mbit/s in the High-speed mode. The bus
capacitance limits the number of interfaces connected to the bus.
For a single master application, the master’s SCL output can be a push-pull driver design
if there are no devices on the bus which would stretch the clock.
Table 2. Applicability of I2C-bus protocol features
M = mandatory; O = optional; n/a = not applicable.
Feature Configuration
Single master Multi-master Slave[1]
START condition M M M
STOP condition M M M
Acknowledge M M M
Synchronization n/a M n/a
Arbitration n/a M n/a
Clock stretching O[2] O[2] O
7-bit slave address M M M
10-bit slave address O O O
General Call address O O O
Software Reset O O O
START byte n/a O[3] n/a
Device ID n/a n/a O
VDD2, VDD3 are device-dependent (for example, 12 V).
Fig 3. Devices with various supply voltages sharing the same bus
CMOS CMOS NMOS BIPOLAR
002aac860
V
DD1
=
5 V ± 10 %
Rp Rp
SDA
SCL
V
DD2
V
DD3

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3.1.2 SDA and SCL logic levels
Due to the variety of different technology devices (CMOS, NMOS, bipolar) that can be
connected to the I2C-bus, the levels of the logical ‘0’ (LOW) and ‘1’ (HIGH) are not fixed
and depend on the associated level of VDD. Input reference levels are set as 30 % and
70 % of VDD; VIL is 0.3VDD and VIH is 0.7VDD. See Figure 38, timing diagram. Some
legacy device input levels were fixed at VIL = 1.5 V and VIH = 3.0 V, but all new devices
require this 30 %/70 % specification. See Section 6 for electrical specifications.
3.1.3 Data validity
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH
or LOW state of the data line can only change when the clock signal on the SCL line is
LOW (see Figure 4). One clock pulse is generated for each data bit transferred.
3.1.4 START and STOP conditions
All transactions begin with a START (S) and are terminated by a STOP (P) (see Figure 5).
A HIGH to LOW transition on the SDA line while SCL is HIGH defines a START condition.
A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition.
START and STOP conditions are always generated by the master. The bus is considered
to be busy after the START condition. The bus is considered to be free again a certain
time after the STOP condition. This bus free situation is specified in Section 6.
The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition. In
this respect, the START (S) and repeated START (Sr) conditions are functionally identical.
For the remainder of this document, therefore, the S symbol is used as a generic term to
represent both the START and repeated START conditions, unless Sr is particularly
relevant.
Fig 4. Bit transfer on the I2C-bus
mba607
data line
stable;
data valid
change
of data
allowed
SDA
SCL
Fig 5. START and STOP conditions
mba608
SDA
SCL P
STOP condition
S
START condition

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Detection of START and STOP conditions by devices connected to the bus is easy if they
incorporate the necessary interfacing hardware. However, microcontrollers with no such
interface have to sample the SDA line at least twice per clock period to sense the
transition.
3.1.5 Byte format
Every byte put on the SDA line must be eight bits long. The number of bytes that can be
transmitted per transfer is unrestricted. Each byte must be followed by an Acknowledge
bit. Data is transferred with the Most Significant Bit (MSB) first (see Figure 6). If a slave
cannot receive or transmit another complete byte of datauntil it has performed some other
function, for example servicing an internal interrupt, it can hold the clock line SCL LOW to
force the master into a wait state. Data transfer then continues when the slave is ready for
another byte of data and releases clock line SCL.
3.1.6 Acknowledge (ACK) and Not Acknowledge (NACK)
The acknowledge takes place after every byte. The acknowledge bit allows the receiver to
signal the transmitter that the byte was successfully received and another byte may be
sent. The master generates all clock pulses, including the acknowledge ninth clock pulse.
The Acknowledge signal is defined as follows: the transmitter releases the SDA line
during the acknowledge clock pulse so the receiver can pull the SDA line LOW and it
remains stable LOW during the HIGH period of this clock pulse (see Figure 4). Set-up and
hold times (specified in Section 6) must also be taken into account.
When SDA remains HIGH during this ninth clock pulse, this is defined as the Not
Acknowledge signal. The master can then generate either a STOP condition to abort the
transfer, or a repeated START condition to start a new transfer. There are five conditions
that lead to the generation of a NACK:
1. No receiver is present on the bus with the transmitted address so there is no device to
respond with an acknowledge.
2. The receiver is unable to receive or transmit because it is performing some real-time
function and is not ready to start communication with the master.
3. During the transfer, the receiver gets data or commands that it does not understand.
4. During the transfer, the receiver cannot receive any more data bytes.
5. A master-receiver must signal the end of the transfer to the slave transmitter.
Fig 6. Data transfer on the I2C-bus
S or Sr Sr or P
SDA
SCL
MSB
1 2 7 8 9 1 2 3 to 8 9
ACK ACK
002aac861
START or
repeated START
condition
STOP or
repeated START
condition
acknowledgement
signal from slave
byte complete,
interrupt within slave clock line held LOW while interrupts are serviced
P
Sr
acknowledgement
signal from receiver