NXP Semiconductors Freescale K22 User manual

K22 Sub-Family Reference Manual
Supports: MK22FX512VLK12, MK22FN1M0VLK12
Document Number: K22P80M120SF5RM
Rev. 4, November 2014

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Contents
Section number Title Page
Chapter 1
About This Document
1.1 Overview.......................................................................................................................................................................53
1.1.1 Purpose.........................................................................................................................................................53
1.1.2 Audience......................................................................................................................................................53
1.2 Conventions..................................................................................................................................................................53
1.2.1 Numbering systems......................................................................................................................................53
1.2.2 Typographic notation...................................................................................................................................54
1.2.3 Special terms................................................................................................................................................54
Chapter 2
Introduction
2.1 Overview.......................................................................................................................................................................55
2.2 Module Functional Categories......................................................................................................................................55
2.2.1 ARM® Cortex™-M4 Core Modules...........................................................................................................56
2.2.2 System Modules...........................................................................................................................................57
2.2.3 Memories and Memory Interfaces...............................................................................................................58
2.2.4 Clocks...........................................................................................................................................................59
2.2.5 Security and Integrity modules....................................................................................................................59
2.2.6 Analog modules...........................................................................................................................................59
2.2.7 Timer modules.............................................................................................................................................60
2.2.8 Communication interfaces...........................................................................................................................61
2.2.9 Human-machine interfaces..........................................................................................................................62
2.3 Orderable part numbers.................................................................................................................................................62
Chapter 3
Chip Configuration
3.1 Introduction...................................................................................................................................................................65
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Section number Title Page
3.2 Core modules................................................................................................................................................................65
3.2.1 ARM Cortex-M4 Core Configuration..........................................................................................................65
3.2.2 Nested Vectored Interrupt Controller (NVIC) Configuration......................................................................67
3.2.3 Asynchronous Wake-up Interrupt Controller (AWIC) Configuration.........................................................73
3.2.4 JTAG Controller Configuration...................................................................................................................74
3.3 System modules............................................................................................................................................................75
3.3.1 SIM Configuration.......................................................................................................................................75
3.3.2 System Mode Controller (SMC) Configuration...........................................................................................76
3.3.3 PMC Configuration......................................................................................................................................76
3.3.4 Low-Leakage Wake-up Unit (LLWU) Configuration.................................................................................77
3.3.5 MCM Configuration....................................................................................................................................79
3.3.6 Crossbar Switch Configuration....................................................................................................................80
3.3.7 Memory Protection Unit (MPU) Configuration...........................................................................................82
3.3.8 Peripheral Bridge Configuration..................................................................................................................85
3.3.9 DMA request multiplexer configuration......................................................................................................86
3.3.10 DMA Controller Configuration...................................................................................................................88
3.3.11 External Watchdog Monitor (EWM) Configuration....................................................................................89
3.3.12 Watchdog Configuration..............................................................................................................................91
3.4 Clock modules..............................................................................................................................................................92
3.4.1 MCG Configuration.....................................................................................................................................92
3.4.2 OSC Configuration......................................................................................................................................93
3.4.3 RTC OSC configuration...............................................................................................................................94
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Section number Title Page
3.5 Memories and memory interfaces.................................................................................................................................94
3.5.1 Flash Memory Configuration.......................................................................................................................94
3.5.2 Flash Memory Controller Configuration.....................................................................................................98
3.5.3 SRAM Configuration...................................................................................................................................99
3.5.4 System Register File Configuration.............................................................................................................102
3.5.5 VBAT Register File Configuration..............................................................................................................103
3.5.6 EzPort Configuration...................................................................................................................................104
3.5.7 FlexBus Configuration.................................................................................................................................105
3.6 Security.........................................................................................................................................................................108
3.6.1 CRC Configuration......................................................................................................................................108
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Section number Title Page
3.7 Analog...........................................................................................................................................................................109
3.7.1 16-bit SAR ADC Configuration..................................................................................................................109
3.7.2 CMP Configuration......................................................................................................................................115
3.7.3 12-bit DAC Configuration...........................................................................................................................117
3.7.4 VREF Configuration....................................................................................................................................118
3.8 Timers...........................................................................................................................................................................119
3.8.1 PDB Configuration......................................................................................................................................120
3.8.2 FlexTimer Configuration.............................................................................................................................123
3.8.3 PIT Configuration........................................................................................................................................127
3.8.4 Low-power timer configuration...................................................................................................................128
3.8.5 CMT Configuration......................................................................................................................................130
3.8.6 RTC configuration.......................................................................................................................................131
3.9 Communication interfaces............................................................................................................................................132
3.9.1 Universal Serial Bus (USB) FS Subsystem.................................................................................................132
3.9.2 CAN Configuration......................................................................................................................................138
3.9.3 SPI configuration.........................................................................................................................................140
3.9.4 I2C Configuration........................................................................................................................................143
3.9.5 UART Configuration...................................................................................................................................144
3.9.6 SDHC Configuration....................................................................................................................................147
3.9.7 I2S configuration..........................................................................................................................................148
3.10 Human-machine interfaces...........................................................................................................................................151
3.10.1 GPIO configuration......................................................................................................................................151
Chapter 4
Memory Map
4.1 Introduction...................................................................................................................................................................153
4.2 System memory map.....................................................................................................................................................153
4.2.1 Aliased bit-band regions..............................................................................................................................154
4.3 Flash Memory Map.......................................................................................................................................................155
4.3.1 Alternate Non-Volatile IRC User Trim Description....................................................................................156
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4.4 SRAM memory map.....................................................................................................................................................157
4.5 Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory map....................................................................................157
4.5.1 Read-after-write sequence and required serialization of memory operations..............................................157
4.5.2 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map........................................................................................158
4.5.3 Peripheral Bridge 1 (AIPS-Lite 1) Memory Map........................................................................................161
4.6 Private Peripheral Bus (PPB) memory map..................................................................................................................165
Chapter 5
Clock Distribution
5.1 Introduction...................................................................................................................................................................167
5.2 Programming model......................................................................................................................................................167
5.3 High-Level device clocking diagram............................................................................................................................167
5.4 Clock definitions...........................................................................................................................................................168
5.4.1 Device clock summary.................................................................................................................................169
5.5 Internal clocking requirements.....................................................................................................................................171
5.5.1 Clock divider values after reset....................................................................................................................171
5.5.2 VLPR mode clocking...................................................................................................................................172
5.6 Clock Gating.................................................................................................................................................................172
5.7 Module clocks...............................................................................................................................................................172
5.7.1 PMC 1-kHz LPO clock................................................................................................................................174
5.7.2 WDOG clocking..........................................................................................................................................174
5.7.3 Debug trace clock.........................................................................................................................................175
5.7.4 PORT digital filter clocking.........................................................................................................................175
5.7.5 LPTMR clocking..........................................................................................................................................176
5.7.6 USB FS OTG Controller clocking...............................................................................................................176
5.7.7 FlexCAN clocking.......................................................................................................................................177
5.7.8 UART clocking............................................................................................................................................177
5.7.9 SDHC clocking............................................................................................................................................178
5.7.10 I2S/SAI clocking..........................................................................................................................................178
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Section number Title Page
Chapter 6
Reset and Boot
6.1 Introduction...................................................................................................................................................................181
6.2 Reset..............................................................................................................................................................................182
6.2.1 Power-on reset (POR)..................................................................................................................................182
6.2.2 System reset sources....................................................................................................................................182
6.2.3 MCU Resets.................................................................................................................................................186
6.2.4 Reset Pin .....................................................................................................................................................188
6.2.5 Debug resets.................................................................................................................................................188
6.3 Boot...............................................................................................................................................................................189
6.3.1 Boot sources.................................................................................................................................................189
6.3.2 Boot options.................................................................................................................................................190
6.3.3 FOPT boot options.......................................................................................................................................190
6.3.4 Boot sequence..............................................................................................................................................191
Chapter 7
Power Management
7.1 Introduction...................................................................................................................................................................193
7.2 Power Modes Description.............................................................................................................................................193
7.3 Entering and exiting power modes...............................................................................................................................195
7.4 Power mode transitions.................................................................................................................................................196
7.5 Power modes shutdown sequencing.............................................................................................................................197
7.6 Module Operation in Low Power Modes......................................................................................................................198
7.7 Clock Gating.................................................................................................................................................................201
Chapter 8
Security
8.1 Introduction...................................................................................................................................................................203
8.2 Flash Security...............................................................................................................................................................203
8.3 Security Interactions with other Modules.....................................................................................................................204
8.3.1 Security interactions with FlexBus..............................................................................................................204
8.3.2 Security Interactions with EzPort................................................................................................................204
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Section number Title Page
8.3.3 Security Interactions with Debug.................................................................................................................204
Chapter 9
Debug
9.1 Introduction...................................................................................................................................................................207
9.1.1 References....................................................................................................................................................209
9.2 The Debug Port.............................................................................................................................................................209
9.2.1 JTAG-to-SWD change sequence.................................................................................................................210
9.2.2 JTAG-to-cJTAG change sequence...............................................................................................................210
9.3 Debug Port Pin Descriptions.........................................................................................................................................211
9.4 System TAP connection................................................................................................................................................211
9.4.1 IR Codes.......................................................................................................................................................211
9.5 JTAG status and control registers.................................................................................................................................212
9.5.1 MDM-AP Control Register..........................................................................................................................213
9.5.2 MDM-AP Status Register............................................................................................................................215
9.6 Debug Resets................................................................................................................................................................216
9.7 AHB-AP........................................................................................................................................................................217
9.8 ITM...............................................................................................................................................................................218
9.9 Core Trace Connectivity...............................................................................................................................................218
9.10 Embedded Trace Macrocell v3.5 (ETM)......................................................................................................................218
9.11 Coresight Embedded Trace Buffer (ETB)....................................................................................................................219
9.11.1 Performance Profiling with the ETB...........................................................................................................219
9.11.2 ETB Counter Control...................................................................................................................................220
9.12 TPIU..............................................................................................................................................................................220
9.13 DWT.............................................................................................................................................................................220
9.14 Debug in Low Power Modes........................................................................................................................................221
9.14.1 Debug Module State in Low Power Modes.................................................................................................222
9.15 Debug & Security.........................................................................................................................................................222
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Section number Title Page
Chapter 10
Signal Multiplexing and Signal Descriptions
10.1 Introduction...................................................................................................................................................................223
10.2 Signal Multiplexing Integration....................................................................................................................................223
10.2.1 Port control and interrupt module features..................................................................................................224
10.2.2 PCRn reset values for port A.......................................................................................................................224
10.2.3 Clock gating.................................................................................................................................................224
10.2.4 Signal multiplexing constraints....................................................................................................................224
10.3 Pinout............................................................................................................................................................................225
10.3.1 K22 Signal Multiplexing and Pin Assignments...........................................................................................225
10.3.2 K22 Pinouts..................................................................................................................................................228
10.4 Module Signal Description Tables................................................................................................................................229
10.4.1 Core Modules...............................................................................................................................................230
10.4.2 System Modules...........................................................................................................................................230
10.4.3 Clock Modules.............................................................................................................................................231
10.4.4 Memories and Memory Interfaces...............................................................................................................231
10.4.5 Analog..........................................................................................................................................................234
10.4.6 Timer Modules.............................................................................................................................................236
10.4.7 Communication Interfaces...........................................................................................................................238
10.4.8 Human-Machine Interfaces (HMI)..............................................................................................................240
Chapter 11
Port control and interrupts (PORT)
11.1 Introduction...................................................................................................................................................................243
11.2 Overview.......................................................................................................................................................................243
11.2.1 Features........................................................................................................................................................243
11.2.2 Modes of operation......................................................................................................................................244
11.3 External signal description............................................................................................................................................245
11.4 Detailed signal description............................................................................................................................................245
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11.5 Memory map and register definition.............................................................................................................................245
11.5.1 Pin Control Register n (PORTx_PCRn).......................................................................................................252
11.5.2 Global Pin Control Low Register (PORTx_GPCLR)..................................................................................254
11.5.3 Global Pin Control High Register (PORTx_GPCHR).................................................................................255
11.5.4 Interrupt Status Flag Register (PORTx_ISFR)............................................................................................256
11.5.5 Digital Filter Enable Register (PORTx_DFER)...........................................................................................256
11.5.6 Digital Filter Clock Register (PORTx_DFCR)............................................................................................257
11.5.7 Digital Filter Width Register (PORTx_DFWR)..........................................................................................257
11.6 Functional description...................................................................................................................................................258
11.6.1 Pin control....................................................................................................................................................258
11.6.2 Global pin control........................................................................................................................................259
11.6.3 External interrupts........................................................................................................................................259
11.6.4 Digital filter..................................................................................................................................................260
Chapter 12
System Integration Module (SIM)
12.1 Introduction...................................................................................................................................................................261
12.1.1 Features........................................................................................................................................................261
12.2 Memory map and register definition.............................................................................................................................262
12.2.1 System Options Register 1 (SIM_SOPT1)..................................................................................................263
12.2.2 SOPT1 Configuration Register (SIM_SOPT1CFG)....................................................................................265
12.2.3 System Options Register 2 (SIM_SOPT2)..................................................................................................266
12.2.4 System Options Register 4 (SIM_SOPT4)..................................................................................................268
12.2.5 System Options Register 5 (SIM_SOPT5)..................................................................................................271
12.2.6 System Options Register 7 (SIM_SOPT7)..................................................................................................273
12.2.7 System Device Identification Register (SIM_SDID)...................................................................................275
12.2.8 System Clock Gating Control Register 1 (SIM_SCGC1)............................................................................276
12.2.9 System Clock Gating Control Register 2 (SIM_SCGC2)............................................................................277
12.2.10 System Clock Gating Control Register 3 (SIM_SCGC3)............................................................................278
12.2.11 System Clock Gating Control Register 4 (SIM_SCGC4)............................................................................280
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12.2.12 System Clock Gating Control Register 5 (SIM_SCGC5)............................................................................282
12.2.13 System Clock Gating Control Register 6 (SIM_SCGC6)............................................................................284
12.2.14 System Clock Gating Control Register 7 (SIM_SCGC7)............................................................................287
12.2.15 System Clock Divider Register 1 (SIM_CLKDIV1)...................................................................................287
12.2.16 System Clock Divider Register 2 (SIM_CLKDIV2)...................................................................................290
12.2.17 Flash Configuration Register 1 (SIM_FCFG1)...........................................................................................291
12.2.18 Flash Configuration Register 2 (SIM_FCFG2)...........................................................................................294
12.2.19 Unique Identification Register High (SIM_UIDH).....................................................................................295
12.2.20 Unique Identification Register Mid-High (SIM_UIDMH)..........................................................................296
12.2.21 Unique Identification Register Mid Low (SIM_UIDML)...........................................................................296
12.2.22 Unique Identification Register Low (SIM_UIDL)......................................................................................297
12.3 Functional description...................................................................................................................................................297
Chapter 13
Reset Control Module (RCM)
13.1 Introduction...................................................................................................................................................................299
13.2 Reset memory map and register descriptions...............................................................................................................299
13.2.1 System Reset Status Register 0 (RCM_SRS0)............................................................................................300
13.2.2 System Reset Status Register 1 (RCM_SRS1)............................................................................................301
13.2.3 Reset Pin Filter Control register (RCM_RPFC)..........................................................................................303
13.2.4 Reset Pin Filter Width register (RCM_RPFW)...........................................................................................304
13.2.5 Mode Register (RCM_MR).........................................................................................................................305
Chapter 14
System Mode Controller (SMC)
14.1 Introduction...................................................................................................................................................................307
14.2 Modes of operation.......................................................................................................................................................307
14.3 Memory map and register descriptions.........................................................................................................................309
14.3.1 Power Mode Protection register (SMC_PMPROT).....................................................................................310
14.3.2 Power Mode Control register (SMC_PMCTRL).........................................................................................311
14.3.3 VLLS Control register (SMC_VLLSCTRL)...............................................................................................313
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14.3.4 Power Mode Status register (SMC_PMSTAT)...........................................................................................314
14.4 Functional description...................................................................................................................................................314
14.4.1 Power mode transitions................................................................................................................................314
14.4.2 Power mode entry/exit sequencing..............................................................................................................317
14.4.3 Run modes....................................................................................................................................................319
14.4.4 Wait modes..................................................................................................................................................321
14.4.5 Stop modes...................................................................................................................................................322
14.4.6 Debug in low power modes.........................................................................................................................325
Chapter 15
Power Management Controller (PMC)
15.1 Introduction...................................................................................................................................................................327
15.2 Features.........................................................................................................................................................................327
15.3 Low-voltage detect (LVD) system................................................................................................................................327
15.3.1 LVD reset operation.....................................................................................................................................328
15.3.2 LVD interrupt operation...............................................................................................................................328
15.3.3 Low-voltage warning (LVW) interrupt operation.......................................................................................328
15.4 I/O retention..................................................................................................................................................................329
15.5 Memory map and register descriptions.........................................................................................................................329
15.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1)........................................................330
15.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2)........................................................331
15.5.3 Regulator Status And Control register (PMC_REGSC)..............................................................................332
Chapter 16
Low-Leakage Wakeup Unit (LLWU)
16.1 Introduction...................................................................................................................................................................335
16.1.1 Features........................................................................................................................................................335
16.1.2 Modes of operation......................................................................................................................................336
16.1.3 Block diagram..............................................................................................................................................337
16.2 LLWU signal descriptions............................................................................................................................................338
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16.3 Memory map/register definition...................................................................................................................................339
16.3.1 LLWU Pin Enable 1 register (LLWU_PE1)................................................................................................340
16.3.2 LLWU Pin Enable 2 register (LLWU_PE2)................................................................................................341
16.3.3 LLWU Pin Enable 3 register (LLWU_PE3)................................................................................................342
16.3.4 LLWU Pin Enable 4 register (LLWU_PE4)................................................................................................343
16.3.5 LLWU Module Enable register (LLWU_ME)............................................................................................344
16.3.6 LLWU Flag 1 register (LLWU_F1).............................................................................................................346
16.3.7 LLWU Flag 2 register (LLWU_F2).............................................................................................................347
16.3.8 LLWU Flag 3 register (LLWU_F3).............................................................................................................349
16.3.9 LLWU Pin Filter 1 register (LLWU_FILT1)..............................................................................................351
16.3.10 LLWU Pin Filter 2 register (LLWU_FILT2)..............................................................................................352
16.3.11 LLWU Reset Enable register (LLWU_RST)...............................................................................................353
16.4 Functional description...................................................................................................................................................354
16.4.1 LLS mode.....................................................................................................................................................354
16.4.2 VLLS modes................................................................................................................................................354
16.4.3 Initialization.................................................................................................................................................355
Chapter 17
Miscellaneous Control Module (MCM)
17.1 Introduction...................................................................................................................................................................357
17.1.1 Features........................................................................................................................................................357
17.2 Memory map/register descriptions...............................................................................................................................357
17.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)................................................................358
17.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)............................................................359
17.2.3 Control Register (MCM_CR)......................................................................................................................360
17.2.4 Interrupt Status Register (MCM_ISCR)......................................................................................................362
17.2.5 ETB Counter Control register (MCM_ETBCC)..........................................................................................365
17.2.6 ETB Reload register (MCM_ETBRL).........................................................................................................366
17.2.7 ETB Counter Value register (MCM_ETBCNT)..........................................................................................366
17.2.8 Process ID register (MCM_PID).................................................................................................................367
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17.3 Functional description...................................................................................................................................................367
17.3.1 Interrupts......................................................................................................................................................367
Chapter 18
Crossbar Switch (AXBS)
18.1 Introduction...................................................................................................................................................................369
18.1.1 Features........................................................................................................................................................369
18.2 Memory Map / Register Definition...............................................................................................................................370
18.2.1 Priority Registers Slave (AXBS_PRSn)......................................................................................................371
18.2.2 Control Register (AXBS_CRSn).................................................................................................................374
18.2.3 Master General Purpose Control Register (AXBS_MGPCRn)...................................................................375
18.3 Functional Description..................................................................................................................................................376
18.3.1 General operation.........................................................................................................................................376
18.3.2 Register coherency.......................................................................................................................................377
18.3.3 Arbitration....................................................................................................................................................377
18.4 Initialization/application information...........................................................................................................................380
Chapter 19
Memory Protection Unit (MPU)
19.1 Introduction...................................................................................................................................................................381
19.2 Overview.......................................................................................................................................................................381
19.2.1 Block diagram..............................................................................................................................................381
19.2.2 Features........................................................................................................................................................382
19.3 Memory map/register definition...................................................................................................................................383
19.3.1 Control/Error Status Register (MPU_CESR)..............................................................................................386
19.3.2 Error Address Register, slave port n (MPU_EARn)....................................................................................387
19.3.3 Error Detail Register, slave port n (MPU_EDRn).......................................................................................388
19.3.4 Region Descriptor n, Word 0 (MPU_RGDn_WORD0)..............................................................................389
19.3.5 Region Descriptor n, Word 1 (MPU_RGDn_WORD1)..............................................................................390
19.3.6 Region Descriptor n, Word 2 (MPU_RGDn_WORD2)..............................................................................390
19.3.7 Region Descriptor n, Word 3 (MPU_RGDn_WORD3)..............................................................................393
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19.3.8 Region Descriptor Alternate Access Control n (MPU_RGDAACn)...........................................................394
19.4 Functional description...................................................................................................................................................396
19.4.1 Access evaluation macro..............................................................................................................................396
19.4.2 Putting it all together and error terminations...............................................................................................398
19.4.3 Power management......................................................................................................................................398
19.5 Initialization information..............................................................................................................................................399
19.6 Application information................................................................................................................................................399
Chapter 20
Peripheral Bridge (AIPS-Lite)
20.1 Introduction...................................................................................................................................................................403
20.1.1 Features........................................................................................................................................................403
20.1.2 General operation.........................................................................................................................................403
20.2 Functional description...................................................................................................................................................404
20.2.1 Access support.............................................................................................................................................404
Chapter 21
Direct Memory Access Multiplexer (DMAMUX)
21.1 Introduction...................................................................................................................................................................405
21.1.1 Overview......................................................................................................................................................405
21.1.2 Features........................................................................................................................................................406
21.1.3 Modes of operation......................................................................................................................................406
21.2 External signal description............................................................................................................................................407
21.3 Memory map/register definition...................................................................................................................................407
21.3.1 Channel Configuration register (DMAMUX_CHCFGn)............................................................................408
21.4 Functional description...................................................................................................................................................409
21.4.1 DMA channels with periodic triggering capability......................................................................................409
21.4.2 DMA channels with no triggering capability...............................................................................................411
21.4.3 Always-enabled DMA sources....................................................................................................................411
21.5 Initialization/application information...........................................................................................................................413
21.5.1 Reset.............................................................................................................................................................413
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21.5.2 Enabling and configuring sources................................................................................................................413
Chapter 22
Direct Memory Access Controller (eDMA)
22.1 Introduction...................................................................................................................................................................417
22.1.1 Block diagram..............................................................................................................................................417
22.1.2 Block parts...................................................................................................................................................418
22.1.3 Features........................................................................................................................................................419
22.2 Modes of operation.......................................................................................................................................................421
22.3 Memory map/register definition...................................................................................................................................421
22.3.1 Control Register (DMA_CR).......................................................................................................................433
22.3.2 Error Status Register (DMA_ES)................................................................................................................436
22.3.3 Enable Request Register (DMA_ERQ).......................................................................................................438
22.3.4 Enable Error Interrupt Register (DMA_EEI)...............................................................................................440
22.3.5 Clear Enable Error Interrupt Register (DMA_CEEI)..................................................................................442
22.3.6 Set Enable Error Interrupt Register (DMA_SEEI)......................................................................................443
22.3.7 Clear Enable Request Register (DMA_CERQ)...........................................................................................444
22.3.8 Set Enable Request Register (DMA_SERQ)...............................................................................................445
22.3.9 Clear DONE Status Bit Register (DMA_CDNE)........................................................................................446
22.3.10 Set START Bit Register (DMA_SSRT)......................................................................................................447
22.3.11 Clear Error Register (DMA_CERR)............................................................................................................448
22.3.12 Clear Interrupt Request Register (DMA_CINT).........................................................................................449
22.3.13 Interrupt Request Register (DMA_INT)......................................................................................................450
22.3.14 Error Register (DMA_ERR)........................................................................................................................452
22.3.15 Hardware Request Status Register (DMA_HRS)........................................................................................455
22.3.16 Channel n Priority Register (DMA_DCHPRIn)..........................................................................................457
22.3.17 TCD Source Address (DMA_TCDn_SADDR)...........................................................................................458
22.3.18 TCD Signed Source Address Offset (DMA_TCDn_SOFF)........................................................................458
22.3.19 TCD Transfer Attributes (DMA_TCDn_ATTR).........................................................................................459
22.3.20 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCDn_NBYTES_MLNO).................................460
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22.3.21 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
(DMA_TCDn_NBYTES_MLOFFNO).......................................................................................................460
22.3.22 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
(DMA_TCDn_NBYTES_MLOFFYES).....................................................................................................462
22.3.23 TCD Last Source Address Adjustment (DMA_TCDn_SLAST).................................................................463
22.3.24 TCD Destination Address (DMA_TCDn_DADDR)...................................................................................463
22.3.25 TCD Signed Destination Address Offset (DMA_TCDn_DOFF)................................................................464
22.3.26 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_CITER_ELINKYES)...........................................................................................................464
22.3.27 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_CITER_ELINKNO)............................................................................................................466
22.3.28 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCDn_DLASTSGA)..........467
22.3.29 TCD Control and Status (DMA_TCDn_CSR)............................................................................................467
22.3.30 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_BITER_ELINKYES)...........................................................................................................470
22.3.31 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_BITER_ELINKNO)............................................................................................................471
22.4 Functional description...................................................................................................................................................472
22.4.1 eDMA basic data flow.................................................................................................................................472
22.4.2 Error reporting and handling........................................................................................................................475
22.4.3 Channel preemption.....................................................................................................................................476
22.4.4 Performance.................................................................................................................................................477
22.5 Initialization/application information...........................................................................................................................481
22.5.1 eDMA initialization.....................................................................................................................................481
22.5.2 Programming errors.....................................................................................................................................483
22.5.3 Arbitration mode considerations..................................................................................................................484
22.5.4 Performing DMA transfers (examples)........................................................................................................484
22.5.5 Monitoring transfer descriptor status...........................................................................................................488
22.5.6 Channel Linking...........................................................................................................................................490
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Section number Title Page
22.5.7 Dynamic programming................................................................................................................................491
Chapter 23
External Watchdog Monitor (EWM)
23.1 Introduction...................................................................................................................................................................495
23.1.1 Features........................................................................................................................................................495
23.1.2 Modes of Operation.....................................................................................................................................496
23.1.3 Block Diagram.............................................................................................................................................497
23.2 EWM Signal Descriptions............................................................................................................................................498
23.3 Memory Map/Register Definition.................................................................................................................................498
23.3.1 Control Register (EWM_CTRL).................................................................................................................498
23.3.2 Service Register (EWM_SERV)..................................................................................................................499
23.3.3 Compare Low Register (EWM_CMPL)......................................................................................................499
23.3.4 Compare High Register (EWM_CMPH).....................................................................................................500
23.4 Functional Description..................................................................................................................................................501
23.4.1 The EWM_out Signal..................................................................................................................................501
23.4.2 The EWM_in Signal....................................................................................................................................502
23.4.3 EWM Counter..............................................................................................................................................502
23.4.4 EWM Compare Registers............................................................................................................................502
23.4.5 EWM Refresh Mechanism...........................................................................................................................503
23.4.6 EWM Interrupt.............................................................................................................................................503
Chapter 24
Watchdog Timer (WDOG)
24.1 Introduction...................................................................................................................................................................505
24.2 Features.........................................................................................................................................................................505
24.3 Functional overview......................................................................................................................................................507
24.3.1 Unlocking and updating the watchdog.........................................................................................................508
24.3.2 Watchdog configuration time (WCT)..........................................................................................................509
24.3.3 Refreshing the watchdog..............................................................................................................................510
24.3.4 Windowed mode of operation......................................................................................................................510
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24.3.5 Watchdog disabled mode of operation.........................................................................................................510
24.3.6 Debug modes of operation...........................................................................................................................511
24.4 Testing the watchdog....................................................................................................................................................511
24.4.1 Quick test.....................................................................................................................................................512
24.4.2 Byte test........................................................................................................................................................512
24.5 Backup reset generator..................................................................................................................................................513
24.6 Generated resets and interrupts.....................................................................................................................................514
24.7 Memory map and register definition.............................................................................................................................514
24.7.1 Watchdog Status and Control Register High (WDOG_STCTRLH)...........................................................515
24.7.2 Watchdog Status and Control Register Low (WDOG_STCTRLL)............................................................517
24.7.3 Watchdog Time-out Value Register High (WDOG_TOVALH).................................................................517
24.7.4 Watchdog Time-out Value Register Low (WDOG_TOVALL)..................................................................518
24.7.5 Watchdog Window Register High (WDOG_WINH)..................................................................................518
24.7.6 Watchdog Window Register Low (WDOG_WINL)...................................................................................519
24.7.7 Watchdog Refresh register (WDOG_REFRESH).......................................................................................519
24.7.8 Watchdog Unlock register (WDOG_UNLOCK).........................................................................................519
24.7.9 Watchdog Timer Output Register High (WDOG_TMROUTH).................................................................520
24.7.10 Watchdog Timer Output Register Low (WDOG_TMROUTL)..................................................................520
24.7.11 Watchdog Reset Count register (WDOG_RSTCNT)..................................................................................521
24.7.12 Watchdog Prescaler register (WDOG_PRESC)..........................................................................................521
24.8 Watchdog operation with 8-bit access..........................................................................................................................521
24.8.1 General guideline.........................................................................................................................................521
24.8.2 Refresh and unlock operations with 8-bit access.........................................................................................522
24.9 Restrictions on watchdog operation..............................................................................................................................523
Chapter 25
Multipurpose Clock Generator (MCG)
25.1 Introduction...................................................................................................................................................................525
25.1.1 Features........................................................................................................................................................525
25.1.2 Modes of Operation.....................................................................................................................................528
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