NXP Semiconductors MPC5746R Guide

NXP Semiconductors
Application Note
Document Number: AN4998
Rev. 1, 07/2019
Contents
1 Introduction
MPC5746R is a multi-core 32-bit microcontroller
intended for automotive powertrain applications. It is
based upon e200z4 Power® Architecture cores running at
up to 200 MHz.
Throughout this application note, MPC5746R refers to
the family of devices: MPC5743R, MPC5745R, and
MPC5746R.
This application note details the options of MPC5746R
power supplies and the correct external circuitry required
for each supply, including digital, analog, and SRAM
standby. It also discusses configuration options for clock,
reset, and ADCs, as well as recommended debug and
peripheral communication connections, and other major
external hardware required for the device.
Please note that information from the MPC5746R
Reference Manual, Data Sheet, and/or Errata report may
be repeated in this application note for the convenience
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 MPC5746R Package Options Overview . . . . . . . . . 2
3 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
4 Clock Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5 Device Reset Configuration. . . . . . . . . . . . . . . . . . 22
6 Input/Output Pins. . . . . . . . . . . . . . . . . . . . . . . . . . 24
7 Debug Options available . . . . . . . . . . . . . . . . . . . . 28
8 Emulation device . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9 ADC and Analog . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10 Example Communication Peripheral connections . 40
11 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
12 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . 51
MPC5746R Hardware Design
Guide
by: NXP Semiconductors

MPC5746R Hardware Design Guide, Rev. 1
MPC5746R Package Options Overview
NXP Semiconductors2
of the reader. The Reference Manual, Data Sheet and Errata report are the official specifications for
MPC5746R and should be reviewed for the most up-to-date information available for this device.
2 MPC5746R Package Options Overview
The MPC5746R is available in four different package options; three of these are intended for production
and one is intended to provide additional features to support debug and calibration.
The package selection should be based on the number of input/output pins required for the application and
the area available for the target system. The following table shows the sizes of different packages. See the
MPC5746R Data Sheet for complete package dimensions and ball placement. Drawings are also available
on the NXP web site; search for the case outline number shown in Table 2.
3 Power Supply
MPC5746R provides several options for providing power supply voltages. The main power supplies
required are 1.25 V, 5 V and 3.3 V depending on the requirements of the application. The on-chip flash
memory supply is generated internally. The SRAM has a separate supply input for data retention features,
if they are required.
In addition the MPC5746R microcontroller includes a robust power management infrastructure that
enables applications to select among various user modes and to monitor internal voltages for high- and
Table 1. MPC5746R Package Options
Package Target Description
144 LQFP
Production
Provides access to the primary features of the device. Packages with additional pins provide
additional features and/or additional GPIO. No Nexus High Speed Aurora Trace interface is
provided on any production package, only JTAG.
176 LQFP
252 MAPBGA
292 MAPBGA Development
Provides access to primary features of device, plus Nexus High Speed Aurora Trace and
overlay/trace memory that can be used for calibration. This package is designed for debug
and calibration development use and is typically provided mounted to an interposer/adapter
system to connect to either a 144LQFP, 176 LQFP or 252 MAPBGA footprint. The Aurora
debug interface connector is provided on this adapter board, eliminating the need for the
customer to route the high speed Aurora differential pairs and allowing use on the customer
PCB.
Table 2. Package Sizes
Package Physical Size (mm) Case Outline Number
144 LQFP 20 x 20 98ASS23177W
176 LQFP 24 x 24 98ASS23479W
252 MAPBGA 17 x 17 98ASA00468D
292 MAPBGA1
1Only for development purpose and not intended for production.
17 x 17 98ASA00261D

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MPC5746R Hardware Design Guide, Rev. 1
NXP Semiconductors 3
low-voltage conditions. The monitoring capability is also used to ensure supply voltages and internal
voltages are within the required ranges before the microcontroller can exit reset. The MPC5746R MCU
supports three different input voltages:
• 1.25 V (required) for the internal logic. This supply may be provided externally or generated from
either the 3.3 V or 5.0 V supply using an external NPN Bipolar Junction Transistor (BJT) ballast
transistor and the internal 1.25 V regulator control.
• 5 V (required) for the Power Management controller, I/O, Debug, ADCs and external
communication interfaces
• 3.3 V (optional) for I/O, Debug and external communication interfaces
The 3.3 V supply required for the flash memory is generated by an on-chip regulator. This regulator
requires an external decoupling capacitor on VDD_HV_FLA.
3.1 Power Supply Signals and Pins
Table 3 lists all power domains with corresponding pin names.
Table 3. MCU Supply Pins
Domain Name Supply Voltage1
1Nominal voltage, see MPC5746R Data Sheet for actual voltage specifications.
Description
VDD_LV2
2This supply may be optionally provided by the on-chip regulator using a pass transistor. See Section 3.1.2
1.25 V Core Logic Low Voltage Supply
VDD_HV_IO_MAIN 5.0 V Main I/O Voltage Supply
VDD_HV_ADV_SAR 5.0 V SAR ADC Voltage Supply
VDD_HV_ADR_SAR 5.0 V SAR ADC Voltage Reference
VDD_HV_ADV_SD 5.0 V Sigma-Delta ADC Voltage Supply
VDD_HV_ADR_SD 5.0 V Sigma-Delta ADC Voltage Reference
VDD_HV_IO_JTAG 3.3 V or 5.0 V Production Device JTAG I/O and External Oscillator
Voltage Supply
VDD_HV_IO_FEC 3.3 V or 5.0 V Ethernet I/O Supply
VDD_HV_IO_MSC 3.3 V or 5.0 V Microsecond Channel I/O Supply
VDD_HV_PMC 5.0 V Power Management Controller Supply
VDD_HV_FLA3
3No connection to external supply required, but it does require a bypass capacitor.
3.3 V PMC Flash Regulator Bypass Capacitor
VDD_LV_BD4
4Only present on the 292 MAPBGA emulation device.
1.25 V Emulation Device Core Logic Low Voltage Supply
VDD_HV_IO_BD43.3 V or 5.0 V Emulation Device Main I/O Voltage Supply
VDDSTBY5
5Ramp rate must be less than 16.6 kV/s as per limitation for the 0N94H mask set. Refer to the latest MPC5746R Data
Sheet for additional requirements.
1.3 V–5.9 V Standby RAM Supply Input

MPC5746R Hardware Design Guide, Rev. 1
Power Supply
NXP Semiconductors4
Some of the supplies can be powered with different supply voltages. In particular, the MCU allows
flexibility in the supply of voltages that power selected input and output pins. These supplies are “high”
supplies and can be connected to either a nominal 3.3 V or 5.0 V supply. In addition we recommend
keeping all supply slew rates below 25 V/ms.
Refer to the MPC5746R Data Sheet to learn what voltages can be connected to the power pins. Supply
pins/balls differ from package to package. Please refer to section 3.1.1 for package differences.
The following table shows several power supply design schemes. The flexibility of the supply
configurations provides the board designer several options for optimizing the design.
Please refer to the IO description attached to the MPC5746R Reference Manual for more details.
3.1.1 Power supply package differences
There are different numbers of balls/pins available for the power supplies in each of the MPC5746R
package options. In addition, for some package options, some power supplies are not available. The table
below shows, for each package, the number of balls available for the power supply input to the device.
All supply balls that are available on the package should be connected to a supply voltage.
Table 4. Power supply schemes
Supply options Reference
Single 5 V supply Section 3.1.2
Multi supply with 5 V and 3.3 V Section 3.1.3
Multi supply with 5 V and 1.25 V Section 3.1.4
Table 5. Number of power supply balls/pins versus package
Supply Domain Nominal Voltage 144LQFP 176LQFP 252BGA
VDD_LV11.25 V 6 6 14
VDD_HV_IO_MAIN 5.0 V 5 5 7
VDD_HV_ADV_SAR 5.0 V 1 1 2
VDD_HV_ADR_SAR 5.0 V 1 1 1
VDD_HV_ADV_SD 5.0 V 1 1 1
VDD_HV_ADR_SD 5.0 V 1 1 1
VDD_HV_IO_JTAG 3.3 V or 5.0 V 1 1 1
VDD_HV_IO_FEC 3.3 V or 5.0 V 1 1 1
VDD_HV_IO_MSC 3.3 V or 5.0 V 1 1 1
VDD_HV_PMC 5.0 V 1 1 1
VDD_HV_FLA23.3 V 1 1 1
VDD_LV_BD31.25 V - - -

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MPC5746R Hardware Design Guide, Rev. 1
NXP Semiconductors 5
3.1.2 Single 5 V Supply
This topology uses a single 5 V supply for all I/O, with the internal regulator providing the 1.25 V for the
VDD_LV core supply. Note that most Fast Ethernet Controller (FEC) physical layer interfaces require 3.3
V signals, so the FEC would not normally be operational in this configuration.
Figure 1. Single 5 V Supply (no Ethernet)
1 VDDSTBY may need to be powered by a separate supply in the case where the standby SRAM data retention feature is required. This figure is intended to illustrate that a single 5 V supply
may be used where appropriate for the design.
2 VDD_HV_IO_JTAG is typically powered by a 3.3 V supply for compatibility with many debug tools. However if tools support 5 V or JTAG access is not required, a 5 V supply may be used and
the JTAG pins can be used as normal GPIO.
VDD_HV_IO_BD43.3 V or 5.0 V - - -
VDDSTBY41.3 V - 5.9 V 1 1 1
1This supply may be optionally provided by the on-chip regulator using a pass transistor. See Section 3.1.2
2Except bypass capacitor no connection to external supply required.
3Only present on the 292 MAPBGA emulation device.
4Ramp rate must be less than 16.6 kV/s as per limitation for the 0N94H mask set. Refer to the latest
MPC5746R Data Sheet for additional requirements.
Table 5. Number of power supply balls/pins versus package
Supply Domain Nominal Voltage 144LQFP 176LQFP 252BGA

MPC5746R Hardware Design Guide, Rev. 1
Power Supply
NXP Semiconductors6
3.1.3 Multi Supply - 5 V and 3.3 V
In this configuration there are dual supply voltages, 5 V and 3.3 V. The 5 V supply provides the I/O supply,
the internal regulator provides the 1.25 V core supply and the 3.3 V supply is used to power the FEC
subnet.
Figure 2. Multi Supply, 5 V and 3.3 V with Ethernet
NOTE
VDD_HV_IO_JTAG and/or VDD_HV_IO_MSC could also be powered by
3.3 V.
3.1.4 Multi Supply: 5.0 V and 1.25 V
In this configuration there are dual supply voltages, 5 V and 1.25 V. I/O is powered by the 5 V supply and
the core voltage is powered by the 1.25 V supply. Note that most Fast Ethernet Controller (FEC) physical
layer interfaces require 3.3 V signals, so the FEC would not normally be operational in this configuration.

Power Supply
MPC5746R Hardware Design Guide, Rev. 1
NXP Semiconductors 7
Figure 3. Multi Supply, 5 V and 1.25 V without Ethernet
3.1.5 Decoupling Capacitor Recommendation for supply domains
Table 6 shows all power domains and the suggested decoupling and/or filter capacitors for their
corresponding pins. These values are provided as a guideline and will vary depending on the application
and capability of the power supplies used.
Table 6. Supply Decoupling Requirements
Domain Supply Voltage Bulk Bypass (each pin)
VDD_LV11.25 V 4.7 μF2220nF ~ 47 nF
VDD_HV_IO_MAIN 5.0 V 4.7 uF3100nF ~ 10 nF
VDD_HV_ADV_SAR 5.0 V 10 μF 220nF ~ 100 nF
VDD_HV_ADR_SAR 5.0 V – 220nF ~ 100 nF
VDD_HV_ADV_SD 5.0 V 4.7 μF 220nF ~ 100 nF
VDD_HV_ADR_SD 5.0 V – 220nF ~ 100 nF
VDD_HV_IO_JTAG 3.3 V or 5.0 V 4.7 μF 220nF ~ 100 nF
VDD_HV_IO_FEC 5.0 V or 3.3 V 4.7 μF 220nF ~ 100 nF
VDD_HV_IO_MSC 5.0 V or 3.3 V 4.7 μF 220nF ~ 100 nF
VDD_HV_PMC 5.0 V 4.7 μF 220nF ~ 47 nF

MPC5746R Hardware Design Guide, Rev. 1
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NXP Semiconductors8
3.2 On-chip 1.25 V Regulator
In order to lower system cost, MPC5746R provides an on-chip regulator that can use an external NPN pass
transistor to provide the 1.25 V core supply voltage from either a 5.0 V or 3.3 V supply. The recommended
external circuits are shown in Figure 4.
Figure 4. 1.25 V Supply with external pass Transistor
When the 5.0 V supply configuration is in use, the internal regulator regulates the BJT emitter voltage to
1.25[V], which is used as the core supply (VDD_LV). The remaining energy needs to be dissipated via the
transistor as heat. The capability of the transistor package to dissipate heat degrades as the temperature
increases. To overcome such problems, the user should analyze the thermal capabilities of the transistor and
add sufficient heat dissipation options as needed.
VDD_HV_FLA43.3 V 1 μF~2.2 μF 1 nF
VDD_LV_BD51.25 V 4.7 μF 100 nF
VDD_HV_IO_BD55.0 V 4.7 μF 100 nF
VDDSTBY 1.3 V–5.9 V 1 μF 100 nF
1This supply may be optionally provided by the on-chip regulator using a bipolar junction transistor (BJT). See Section 3.1.2.
2Recommend 4 x 4.7 uF bulk capacitors with lower ESR (each < 200 mΩ) for VDD_LV supply domain.
3Recommend 5 x 4.7 uF bulk capacitors for VDD_HV_IO_MAIN supply domain.
4No connection to external supply required.
5Only present on the 292 MAPBGA emulation device.
Table 6. Supply Decoupling Requirements
Domain Supply Voltage Bulk Bypass (each pin)

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MPC5746R Hardware Design Guide, Rev. 1
NXP Semiconductors 9
There are several options available: 1) use a heat sink 2) populate a copper layer(s) beneath the transistor with
thermal VIAS to improve the heat dissipation. NXP recommends consulting the transistor vendor to obtain
optimal thermal design.
As another option, an external resistor can be used to minimize the extra heat. The resistor will drop the
collector voltage to mitigate the heat dissipation of the pass transistor (BJT). In this case, the collector voltage
needs to be maintained at 3 V or above.
NXP recommends a low inductance between the transistor base and the VRC_CTRL pin/pad. This should be
less than 100nH. An inductance of 15nH is an optimal value.
The following examples explain how to calculate the power dissipation of the BJT with different resistor (R)
values.
Example.1:
Supply voltage is 5.0 V, R=1.8 Ω, Max current consumption at VDD_LV (Ivdd_lv) = 700 [mA] and
nominal VDD_LV = 1.25 [V]
Voltage drop across the R = 1.8 Ω x 700mA = 1.260 [v], voltage at collector 5 V-1.26 V = 3.74 [V] (>
3 V)
Power dissipation on BJT transistor P (Tr): P (Tr) = (5 - 1.25 - 1.26) x 0.7 = 1.743 [w]
Power dissipation on resistor P(R): P(R)= 1.26 x 0.7 = 0.882 [w]
Example.2:
Supply voltage is 5.0 V, R=2.0 Ω, Max current consumption at VDD_LV (Ivdd_lv) = 700 [mA] and
nominal VDD_LV = 1.25 [V]
Voltage drop across the R = 2.0 Ω x 700mA = 1.400 [V], voltage at collector 5 V-1.4 V = 3.6 [V] (> 3
V)
Power dissipation on BJT transistor P (Tr) given by: P (Tr) = (5 - 1.25 - 1.40) x 0.7 = 1.645 [w]
Power dissipation on resistor P(R) given by: P(R)= 1.40 x 0.7 = 0.980 [w]
3.2.1 Recommended Pass Transistor
The on-chip 1.25 V regulator requires an external BJT for operation. Refer to the following table for
recommended pass transistors. Please refer to the MPC5746R Data Sheet to obtain the requirements for
the BJT device.
Table 7. Recommended pass Transistors
Transistor Collector capacitor (CC)Base capacitor Resistor Supply options
ON semiconductor
NJD2873T4
4.7 uF (min) ESR<200 mΩ-2 Ω 5.0 V
ON semiconductor
NJD2873T4
4.7 uF (min) ESR<200 mΩ - - 3.3 V
ROHM 2SCR574D3 A07 4.7 uF (min) ESR<200 mΩ1 uF - 3.3 V

MPC5746R Hardware Design Guide, Rev. 1
Power Supply
NXP Semiconductors10
3.3 External 1.25 V Supply
If an external regulator is used for the VDD_LV supply, the pass transistor is not required. In this case, the
internal voltage regulator driver should be disabled by setting the REG_SEL bit in the Miscellaneous
Device Configuration Format (DCF) client. This is accomplished via a DCF record programmed into the
UTEST flash memory. See the DCF Chapter of the MPC5746R Reference Manual for complete
information regarding the use of DCF records and UTEST flash memory.
Note that the VRC_CTRL will remain active until the Reset Generation Module (RGM) enters the reset
phase 3, where the UTEST configuration is read. When using an external VDD_LV supply, the
VRC_CTRL pin should be left floating (no connect). See the RGM chapter of the MPC5746R Reference
Manual for more information.
3.4 Input and output pins power supply segmentation
Each I/O pin is associated with one of the power domains. The majority of the I/O pins are powered by the
VDD_HV_IO_MAIN. The VDD_HV_IO_JTAG, VDD_HV_IO_FEC, and VDD_HV_IO_MSC domains
are primarily intended to allow the JTAG, FEC and MSC interfaces to be operated at a voltage level
different from the VDD_HV_IO_MAIN domain if desired. However, they can also be used to power a
limited amount of I/O pins at an alternative voltage level.
The voltage level supplied on any I/O domain determines the output voltage level and input transition
levels for the I/O pins associated with that domain. Each power domain with corresponding I/O pins is
shown in Table 8. Each power domain needs to be maintained below 80 mA. In addition, the sum of all
I/O power domains should be maintained below 200mA as described in the MPC5746R Data Sheet. Note
that, not all of the listed I/O pins are available on some packages.1
Table 8. Power Domains vs. I/O
Power Domain I/O Pins
VDD_HV_IO_MAIN
PD[0–15]
PE[0]
PF[0–13]
PG[1–7, 9–15]
PH[0–15]
PI[0–5]
PJ[0–15]
PK[0–2, 4–5, 7–14]
PL[0–1]
VDD_HV_IO_JTAG PB[0–1]
VDD_HV_IO_FEC PC[0–13]
VDD_HV_IO_MSC PA[0–13]
VDD_HV_ADV_SAR
PW[0–3]
PX[0–15]
PY[0–15]
VDD_HV_ADV_SD PZ[0–15]

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MPC5746R Hardware Design Guide, Rev. 1
NXP Semiconductors 11
3.5 Decoupling capacitor layout priorities
When trade offs must be made in the layout, it is important to ensure that the highest priority decoupling
capacitors are placed as close as possible to the MCU. The list below orders the power supply domains
from highest to lowest priority in terms of decoupling capacitor placement.
• Highest priority is given to the analog-to-digital converters reference and power supply
decoupling: VDD_HV_ADR_SAR, VDD_HV_ADR_SD, VDD_HV_ADV_SAR, and
VDD_HV_ADV_SD. Clean supplies are vital to ensure that the highest accuracy is achieved with
the ADCs. In addition, linear supplies must be used as analog references. The supply for the
oscillator (VDD_HV_IO_JTAG) is also prioritized as this helps to ensure reliable and stable
operation from the external oscillator.
• Medium priority is given to VDD_LV, VDD_HV_PMC, and VDD_HV_FLA. VDD_LV is the
main supply for the on-chip digital logic, including the cores, and this is prioritized because it
affects the largest amount of logic on the device. VDD_HV_PMC powers the flash regulator and
VDD_HV_FLA is the output of this regulator. A good supply to the flash memory ensures reliable
flash programming and erasing.
• VDD_HV_IO_MAIN, VDD_IO_MSC, and VDDSTBY are given lower priority. Although it is
still important that these supplies have a clean power signal, the hardware they power is less
affected by noise.
3.6 Supply monitoring
MPC5746R monitors the voltage supplies internally. The function of the power-on reset (POR),
low-voltage detect (LVD) and high-voltage detect (HVD) circuits is to hold the device in reset until critical
1.See the MPC5746R Reference Manual for complete information on the power segmentation, input multiplexing and
other pin characteristics.
Table 9. Decoupling Capacitor Layout Priorities
Priority Domain Description
1VDD_HV_ADR_SAR
VDD_HV_ADR_SD
ADC references
2VDD_HV_ADV_SAR
VDD_HV_ADV_SD
ADC supplies
3 VDD_HV_IO_JTAG JTAG debug and XOSC supply
4 VDD_LV Core(s) supply
5VDD_HV_PMC Power Management Controller
supply
6 VDD_HV_FLA Flash memory supply/decouple
7 VDD_HV_IO_MAIN GPIO supply
8 VDD_HV_IO_MSC Microsecond channel supply
9 VDDSTBY SRAM standby voltage

MPC5746R Hardware Design Guide, Rev. 1
Power Supply
NXP Semiconductors12
voltages are in specification. LVD/HVD monitor limits are shown in Table 10 for your reference. Use the
latest MPC5746R Data Sheet for the final specification values. The device is held in reset regardless of
how slow the supply voltage rise is, until the point at which the POR and LVDs are released.
Table 10. Voltage monitor electrical characteristics
By default VDD_LV internal POR (POR085_c/POR098_c), internal core voltage monitor
(LVD_core_hot), VDD_HV_PMC voltage monitor (LVD_HV) and VDD_HV_IO_MAIN voltage
monitor (LVD_IO) are enabled. As shown in the mask option field under configuration column of the
Table 10, the user can enable/disable the voltage monitors of LVD/HVD by either of following methods.
1. Program the PMC_REE register directly by the application software. But, this method is only valid
for LVD_core_cold, HVD_core, HVD_HV and LVD_SAR configurations.
2. Program the PMC_REE_DCF_client DCF record into the UTEST area. With this option, the user
can disable the LVD_core_hot, enable the LVD_core_cold, HVD_core, HVD_HV and LVD_SAR
configurations. Note that the default configuration will remain active until the RGM enter phase 3,
where the UTEST configuration is read.
The POR and LVD circuits function correctly even if the input voltage is non-monotonic. A diagram
illustrating the on-chip LVD/HVD circuits is shown in Figure 5. For detailed information on the
low-voltage detect (LVD) and high-voltage detect (HVD) circuits, please refer to the MPC5746R
Reference Manual and Data Sheet.

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MPC5746R Hardware Design Guide, Rev. 1
NXP Semiconductors 13
Figure 5. LVD and HVD Implementation

MPC5746R Hardware Design Guide, Rev. 1
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NXP Semiconductors14
3.6.1 Behavior of LVD / HVD
The internal LVD circuits monitor the voltage on the corresponding supply. If the supply falls below
defined values, the LVD asserts either a reset or an interrupt. Figure 6 illustrates how the RESET behaves
with different LVD/HVD levels. The LVDs also support hysteresis for the falling and rising trip points.
Although there is an option to disable the LVDs and HVDs following reset, they are capable of being used
in a ‘monitor’ only mode and also capable of generating a safe/interrupt event. The LVDs/HVDs can also
be configured after device initialization, preventing a reset when a supply crosses the LVD threshold,
providing a higher voltage range. The customer application should monitor and verify that the device
voltage supply levels remain in the functional range.
NOTE
VDD_LV internal supply power on reset monitors (POR085_c and
POR098_c) cannot be disabled. These trip points are used during the
power-up phase and must ensure that an absolute lowest voltage threshold
for operation is never crossed. This is not a guarantee that the device will
function down to this level. It is rather a guarantee that the device will be
reset if this level is crossed.
Figure 6. Illustration of LVD/HVD behavior with RESET status
VDD_LV supply
RESET pin state
POR098_c(rising) POR098_c(falling)
VDD_HV_IO_MAIN, VDD_HV_PMC
LVD_I O, LVD_P MC (rising )
HVD_Core (if enabled, falling)
LVD_Core_Hot (rising=falling)
LVD_Core_Hot (rising)
HVD_Core (if enabled, rising)
LVD_IO, LVD_PMC (falling)

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MPC5746R Hardware Design Guide, Rev. 1
NXP Semiconductors 15
3.6.2 Power-on reset
The power management controller (PMC) controls the Power-On reset (POR) for the MCU. When the
critical power supplies are below minimum levels, the MCU is held in the POWER-UP phase of the reset
state machine (see the Reset and Boot chapter of the MPC5746R Reference Manual), until the power
supplies have reached their specified levels. Power sequencing is not necessary. When the required voltage
levels have been reached, the reset generation module (RGM) propagates the device through the next steps
of the boot process.
The PMC has three internal power-on reset circuits:
• 1.25 V input supply – This circuit monitors the VDD_LV pin and asserts a reset when the input
supply is below defined values.
— POR085_c monitors the voltage on the 1.25 V input supply on the VDD_LV pin. POR085_c
asserts a reset when the input supply is below defined values.
— POR098_c monitors the voltage on the 1.25 V input supply on the VDD_LV pin. POR098_c
asserts a reset when the input supply is below defined values. The POR098_c trip point makes
sure that the voltage is high enough for LV logic to initialize and recognize RESET assertion,
ensuring the correct logic state. At this point all the LVD circuits become functional.
• 5.0 V input supply – This circuit monitors the VDD_HV_PMC pin and ensures the PORST trip
point is high enough to make sure all the LVD circuits are functional.
— LVD_HV monitors the voltage on the 3.5 - 5.0 V input supply at the VDD_HV_PMC pin, the
actual PMC module supply. The POR trip point is high enough to make sure all the LVD
circuits are functional i.e. to ensure that the VDD_HV_PMC supply is in range to allow all
PMC internal circuits to operate reliably.
• The LVD_VFLASH monitors the flash input voltage and is used to control the power-up sequence,
ensuring the flash memory can be accessed prior to the reset phase 0 being completed.
POR085_c2 and POR098_c2 are used for redundancy. Minimum and maximum values and trigger
conditions for each LVD and HVD monitor can be found in the MPC5746R Data Sheet. See the Reset
chapter in the MPC5746R Reference Manual for PORST/RESET pin functionality.
3.6.3 Low-Voltage (LVD) and High-Voltage Detection (HVD)
• All LVDs and HVDs are capable of generating reset.
• All LVDs and HVDs configured for reset generation cause functional or destructive reset.
MC_RGM PHASE0 is not exited until all destructive reset conditions are cleared.
• The appropriate bits in the PMC registers are set by LVD and HVD events.
• LVD and HVD control is protected by the System-on-Chip (SoC) wide register protection scheme.
• There are user option bits available to allow degrade of configurable LVDs/HVDs from destructive
reset down to functional reset. This is a write once mechanism managed by System Status and
Configuration Module (SSCM) during device initialization.
• When the LVD or the HVD is enabled for destructive reset generation, and a trigger event is
detected, the external PORST pin is driven low.

MPC5746R Hardware Design Guide, Rev. 1
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NXP Semiconductors16
3.6.4 Analog module self-test and parameter monitoring
The ADC interface includes connections to the PMC internal voltages for diagnostic purposes. An analog
multiplexer and the buffer are inside the PMC. SAR ADC0 converts the selected voltage, which can then
be evaluated by the CPU. Voltages in the PMC module can be monitored with the ADC and the ADC does
not impact the PMC voltage levels. These signals are used for calibration, diagnostics during test or to
allow the application to actively monitor the signal levels. There is a dedicated ADC channel for these
monitoring purposes.
Table 11 lists all the internal test signals that can be monitored using SAR ADC0.
Table 11. ADC 0 Mux Interface
PMC_ADC_CS[ADC_CHSE] ADC Channel Output Typical Value
6’b000000 ADC Channel Off
6’b011110 por085_c sense value 1.25 V (CORE supply)
6’b011101 por085_c reference value 0.915 V
6’b011100 por098_c sense value 1.25 V (CORE supply)
6’b011011 por098_c reference value 1.01 V
6’b011010 por085_c2 sense value 1.25 V (CORE supply)
6’b011001 por085_c2 reference value 0.905 V
6’b011000 por098_c2sense value 1.25 V (CORE supply)
6’b010111 por098_c2 reference value 0.993 V
6’b010110 lvd_core_cold sense 1.25 V (CORE supply)
6’b010101 lvd_core_cold_reference 1.24 V
6’b010100 lvd_core_hot_sense 1.25 V (CORE supply)
6’b010011 lvd_core_hot_reference 1.21 V
6’b010010 hvd_core_sense 1.25 V (CORE supply)
6’b010001 hvd_core_reference 1.43 V
6’b010000 por260_c divider tap point 2.55 V
6’b001111 por260_c reference 1.2 V
6’b001110 por260_c2 divider tap point 2.55 V
6’b001101 por260_c2 reference 1.2 V
6’b001100 lvd_pmc divider tap point 1.98 V
6’b001011 lvd_pmc reference 1.2 V
6’b001010 hvd600 divider tap point 1.13 V
6’b001001 hvd600 reference 1.2 V
6’b001000 lvd_flash divider tap point 1.31 V
6’b000111 lvd_flash reference 1.2 V
6’b000110 hvd_flash divider tap point 1.13 V

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MPC5746R Hardware Design Guide, Rev. 1
NXP Semiconductors 17
3.7 Power sequence
The following section describes the power sequence and the relationship between the different supplies
during power-up and power-down.
The device is considered to be in a power sequence (or POWERUP state) when the power is not supplied
or is only partially powered. An internal power-on signal is used to identify the POWERUP state. This
signal is released high on exit of the power sequence. The power-on signal is a combination of certain
LVDs that are monitoring supplies:
6’b000101 hvd_flash reference 1.2 V
6’b000100 lvd_io divider tap point 1.97 V
6’b000011 lvd_io reference 1.2 V
6’b000010 Reserved —
6’b000001 Reserved —
6’b000000 Reserved —
6’b1111111 Reserved —
6’b111110 Reserved —
6’b111101 Reserved —
6’b111100 Reserved —
6’b111011 Reserved —
6’b111010 lvd_buddy reference 1.05 V
6’b111001 lvd_buddy sense 1.2 V (BD supply)
6’b111000 lvd_sar_adc divider tap point 2.25 V
6’b110111 lvd_sar_adc reference 1.2 V
6’b110110 hvd_sar_adc divider tap point 1.13 V
6’b110101 hvd_sar_adc reference 1.2 V
6’b110100 bandgap voltage with only curve
trimming
1.205 V
6’b110011 nwellbias regulator output 1.25 V
6’b110010 nwellbias regulator reference 1.25 V
6’b100100 ioseg3_sense VDD_HV_IO segment 3
6’b100011 ioseg2_sense VDD_HV_IO segment 2
6’b100010 vrefh_sd_adc 5 V
6’b100001 vrefh_sd_adc 5 V
6’b100000 vss_sd_adc 0 V
Table 11. ADC 0 Mux Interface
PMC_ADC_CS[ADC_CHSE] ADC Channel Output Typical Value

MPC5746R Hardware Design Guide, Rev. 1
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NXP Semiconductors18
Figure 7. Logical connection between power domains
The actual threshold used for each LVD depends on the configuration of the device. This is configurable
by hardware (flash option bit settings) or by software (LVD event configuration through a register
interface). Once the power-on signal has been asserted, the device configuration is reset to default
power-up configuration; during the initialization phase, the device defaults to a pre-determined state for
each of the LVDs, HVDs, and the internal regulators. As the flash memory becomes available, the
differential read process allows the trimmed data to be available for trimming the internal LVDs, HVDs,
and regulators.
3.7.1 Power-up sequence
In this section, the assumption is made that all supplies are low when entering the power-up sequence.
Brown-out and power down sequences are discussed in following sections.
At the beginning of power-up, the internal power-on signal remains low due to the parasitic diodes. As
soon as the minimum threshold is reached on VDD_LV, the power-on signal is forced low. It remains low
until the power-up LVDs reach their upper (not trimmed) threshold. During power-up, all functional pins
are maintained in a known state as described in Table 12.
The power-up sequence is as follows:
1. Digital reset is asserted, ensuring that all module registers are reset to their power-on value.
2. The POWERUP state is exited when both VDD_LV and VDD_HV are above threshold.
Table 12. Functional Terminal State - Power-Up and Reset
Pin Type POWERUP
Pad State
During RESET
Pad State
Out of RESET
Pad State
PORST strong pull-down weak pull-down weak pull-down
RESET strong pull-down weak pull-up weak pull-up
GPIO high impedance weak pull-up weak pull-up
ANALOG high impedance high impedance high impedance
ERROR high impedance high impedance high impedance
JCOMP high impedance weak pull-down weak pull-down
TCK high impedance weak pull-down weak pull-down
TMS high impedance weak pull-up weak pull-up
TDI high impedance weak pull-up weak pull-up
TDO high impedance high impedance high impedance
VDD_LV
VDD_HV_PMC
VDD_HV_IO_MAIN
VDD_HV_FLA
POWERUP

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MPC5746R Hardware Design Guide, Rev. 1
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3. After both LV, HV and temperature POWERUP exit conditions have been verified, the internal
power-on signal is released to all analog modules.
4. The internal RC oscillator module starts initialization and provides a clock to the system. The PMC
digital interface reset is released after two RC clock cycles.
5. The device proceeds with the reset sequence through RGM phase PHASE0, PHASE1[DEST],
PHASE2[DEST] and PHASE3[DEST].
6. Voltage detector (LVD/HVD) modules are trimmed at the beginning of PHASE3[DEST].
Trimming of the LVDs/HVDs is done by the SSCM at low voltage. After trimming is completed,
the SSCM waits for PMC acknowledge to proceed with the reset sequence.
7. The configurable LVD/HVD modules are optionally enabled at the beginning of PHASE3[DEST]
by programming the PMC_REE/PMC_RES DCF records. After trimming, the PMC interface
monitors all the HVD/LVD outputs that have been enabled by the flash user option bits. When all
enabled LVDs/HVDs are released and the analog temporization period has elapsed, LVDs/HVDs
are unmasked.
8. When the LVDs are masked, the device relies on the PORST signal to detect a voltage failure
during power-up. The device must wait for PORST to be released high before proceeding with
power-up sequence. This may increase the amount of time necessary to complete the reset
sequence.
9. After all LVDs/HVDs are unmasked the SSCM proceeds with the reset sequence, eventually
running full speed accesses to the extended flash option bits required to complete device
configuration.
10. The VDD_HV conditions to exit POWERUP are as follows:
— LVD_HV and LVD_IO upper threshold is crossed
— LVD_VFLASH is crossed
3.7.2 Power-down sequence
During power down, any time the VDD_HV or the VDD_LV supply crosses the respective LVD threshold,
the device enters the POWERUP state. The power-down sequence is entered as soon as the threshold of
one of the LVD_HV, LVD_IO, LVD_core_hot, LVD_VFLASH or POR98 is crossed. The device supplies
may then proceed to drop down to ground either through device leakage or external pull-down.
3.7.3 Brown-out management
During brown-out, the MPC57xx devices re-enter the POWERUP phase as soon as the LVD/HVD
threshold of either VDD_LV or VDD_HV is crossed.
3.7.4 Low voltage during crank
The device is able to continue operation at the minimum input voltage during cranking. In order to proceed
with execution during cranking and prevent device reset, it is important to correctly configure the high
voltage LVDs. Figure 8 illustrates a typical cranking voltage profile.

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NXP Semiconductors20
Figure 8. Example Cranking Voltage Profile
The above diagram shows the input voltage falling to 3.5 V at the battery terminals. Several options are
available to filter the supply sag.
• DC-DC converters to boost the supply
• Additional capacitance to filter the sag
• External power supply system asserts a reset
4 Clock Circuitry
MPC5746R can use either the internal RC oscillator, an external crystal or an external clock as the
reference clock. This reference is qualified by multiple methods before the Phase-Locked Loop (PLL) will
begin lock operation. The ‘pre’ Frequency-Modulated Phase-Locked Loop (FMPLL) circuitry consists of
an automatic level-controlled amplifier, a comparator, a loss of clock detector, and a pre-divider.
Care must be taken in the layout and design of the circuitry around the crystal and FMPLL power supplies.
Any noise in these circuits can affect the accuracy of the clock source to the FMPLL. The PLLs are
powered by VDD_LV. The oscillator (OSC) is powered by VDD_HV_IO_JTAG. Noise on either of these
supplies can affect the accuracy and jitter performance of the oscillator and PLLs.
In order to minimize any potential noise, connect the capacitors recommended in Table 6 to the VDD_LV
and VDD_HV_IO_JTAG supplies.
MPC5746R provides configurable internal load capacitors for the external crystal (Cx and Cy in Figure 9).
This feature is intended to simplify the hardware design and reduce the overall system cost by eliminating
external components and reducing the printed circuit board (PCB) footprint. If an 8 MHz–16 MHz crystal
is used, as shown in Figure 10 external load capacitance must be connected. If the external crystal is to be
started during power-up by hardware, the crystal frequency and the selected load capacitance must be
specified in the UTEST Miscellaneous DCF Client records field. See the MPC5746R Reference Manual
for details.
VBATT
Time
12 V
5.0 V
3.5 V
t1t2t3t4t5