NXP Semiconductors MC9S08LG32 User manual

HCS08
Microcontrollers
freescale.com
MC9S08LG32RM
Rev. 5
8/2009
MC9S08LG32
MC9S08LG16
Reference Manual
THIS DOCUMENT CONTAINS INFORMATION ON ANEW PRODUCT UNDER DEVELOPMENT. FREESCALE RESERVES THE RIGHT TO CHANGE OR
DISCONTINUE THIS PRODUCT WITHOUT NOTICE.

MC9S08LG32 Series Features
8-Bit HCS08 Central Processor Unit (CPU)
• Up to 40 MHz CPU at 5.5 V to 2.7 V across temperature
range of –40 °C to 85 °C and –40 °C to 105 °C
• HCS08 instruction set with added BGND instruction
• Support for up to 32 interrupt/reset sources
On-Chip Memory
• 32 KB or 18 KB dual array flash; read/program/erase
over full operating voltage and temperature
• 1984 byte random access memory (RAM)
• Security circuitry to prevent unauthorized access to
RAM and flash contents
Power-Saving Modes
• Two low-power stop modes (stop2 and stop3)
• Reduced-power wait mode
• Peripheral clock gating register can disable clocks to
unused modules, thereby reducing currents
• Low power on-chip crystal oscillator (XOSC) that can be
used in low-power modes to provide accurate clock
source to real time counter and LCD controller
• 100 μs typical wakeup time from stop3 mode
Clock Source Options
• Oscillator (XOSC) — Loop-control Pierce oscillator;
crystal or ceramic resonator range of 31.25 kHz to
38.4 kHz or 1 MHz to 16 MHz
• Internal Clock Source (ICS) — Internal clock source
module containing a frequency-locked-loop (FLL)
controlled by internal or external reference; precision
trimming of internal reference allows 0.2% resolution
and 2% deviation over temperature and voltage; supports
bus frequencies from 1 MHz to 20 MHz
System Protection
• COP reset with option to run from dedicated 1 kHz
internal clock or bus clock
• Low-voltage warning with interrupt
• Low-voltage detection with reset
• Illegal opcode detection with reset
• Illegal address detection with reset
• Flash and RAM protection
Development Support
• Single-wire background debug interface
• Breakpoint capability to allow single breakpoint setting
during in-circuit debugging (plus two more breakpoints
in on-chip debug module)
• On-chip in-circuit emulator (ICE) debug module
containing three comparators and nine trigger modes;
eight deep FIFO for storing change-of-flow addresses
and event-only data; debug module supports both tag and
force breakpoints
Peripherals
•LCD — Up to 4 x 41 or 8 x 37 LCD driver with internal
charge pump
•ADC — Up to 16-channel, 12-bit resolution; 2.5 μs
conversion time; automatic compare function;
temperature sensor; internal bandgap reference channel;
runs in stop3 and can wake up the system; fully
functional from 5.5 V to 2.7 V
•SCI — Full duplex non-return to zero (NRZ); LIN
master extended break generation; LIN slave extended
break detection; wakeup on active edge
•SPI— Full-duplex or single-wire bidirectional;
double-buffered transmit and receive; master or slave
mode; MSB-first or LSB-first shifting
•IIC — With up to 100 kbps with maximum bus loading;
multi-master operation; programmable slave address;
interrupt driven byte-by-byte data transfer; supports
broadcast mode and 10-bit addressing
•TPMx — One 6 channel and one 2 channel; selectable
input capture, output compare, or buffered edge or
center-aligned PWM on each channel
•MTIM — 8-bit counter with match register; four clock
sources with prescaler dividers; can be used for periodic
wakeup
•RTC — 8-bit modulus counter with binary or decimal
based prescaler; three clock sources including one
external source; can be used for time base, calendar, or
task scheduling functions
•KBI — One keyboard control module capable of
supporting 8x8 keyboard matrix
•IRQ — External pin for wakeup from low-power modes
Input/Output
• 39, 53, or 69 GPIOs
• 8 KBI and 1 IRQ interrupt with selectable polarity
• Hysteresis and configurable pullup device on all input
pins; configurable slew rate and drive strength on all
output pins
Package Options
• 48-pin LQFP, 64-pin LQFP, and 80-pin LQFP

MC9S08LG32 Reference Manual
Covers MC9S08LG32
MC9S08LG16
Related Documentation:
•MC9S08LG32PB (Product Brief)
Contains descriptive feature set, example application
information, and developer environment details
•MC9S08LG32 Data Sheet
Contains package information, pinouts,
electricals/characterization data, and mechanical
drawings
Find the most current versions of all documents at:
http://www.freescale.com
MC9S08LG32RM
Rev. 5
8/2009
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
© Freescale Semiconductor, Inc., 2009. All rights reserved.
THIS DOCUMENT CONTAINS INFORMATION ON ANEW PRODUCT UNDER DEVELOPMENT. FREESCALE RESERVES THE RIGHT TO CHANGE OR
DISCONTINUE THIS PRODUCT WITHOUT NOTICE.

MC9S08LG32 MCU Series, Rev. 5
6Freescale Semiconductor
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be
the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://www.freescale.com
The following revision history table summarizes changes contained in this document.
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
© Freescale Semiconductor, Inc., 2009. All rights reserved.
Revision
Number
Revision
Date Description of Changes
Rev. 1 9/2008 First Initial Release.
Rev. 2 9/2008 Second Initial Release.
Rev. 3 11/2008 Alpha Customer Release.
Rev. 4 2/2009 Launch Release.
Rev. 5 8/2009
•InChapter 3, “Modes of Operation,” added On-Chip Peripheral Modules in
Stop Modes section in Chapter 3.
•InTable 5-2, corrected addresses for vector number from 23 to 18.
•InTable 7-1, updated KBI pins order as per PINPS1 register.
• Changed TCLK, T1CH0, T1CH1, T2CH0, T2CH1, T2CH2, T2CH3, T2CH4,
T2CH5 to TPMCLK, TPM1CH0, TPM1CH1, TPM2CH0, TPM2CH1,
TPM2CH2, TPM2CH3, TPM2CH4, TPM2CH5.
• Changed ‘LCDCPEN” to “LCDPEN” and “LCDFWF” to “LCDWF.”
•InChapter 12, “Inter-Integrated Circuit (S08IICV2),” a note is added in the
introduction mentioning that MC9S08LG32 series of MCUs include only one
IIC module.

MC9S08LG32 MCU Series, Rev. 5
Freescale Semiconductor 7
List of Chapters
Chapter Title Page
Chapter 1 Device Overview ....................................................................................... 21
Chapter 2 Pins and Connections .............................................................................. 27
Chapter 3 Modes of Operation .................................................................................. 41
Chapter 4 Memory ...................................................................................................... 49
Chapter 5 Resets, Interrupts, and General System Control ................................... 73
Chapter 6 Parallel Input/Output Control................................................................... 97
Chapter 7 Keyboard Interrupt (S08KBIV2) ............................................................. 128
Chapter 8 Central Processor Unit (S08CPUV5) ..................................................... 135
Chapter 9 LCD Module (S08LCDLPV1)................................................................... 158
Chapter 10 Analog-to-Digital Converter (S08ADC12V1) ....................................... 200
Chapter 11 Internal Clock Source (S08ICSV3)....................................................... 226
Chapter 12 Inter-Integrated Circuit (S08IICV2) ...................................................... 241
Chapter 13 Serial Communications Interface (S08SCIV4).................................... 259
Chapter 14 Serial Peripheral Interface (S08SPIV4)................................................ 278
Chapter 15 Real-Time Counter (S08RTCV1) .......................................................... 297
Chapter 16 Timer/Pulse-Width Modulator (S08TPMV3) ........................................ 306
Chapter 17 Modulo Timer (S08MTIMV1) ................................................................. 327
Chapter 18 Development Support........................................................................... 337
Chapter 19 Debug Module (DBG) (64K).................................................................. 350

MC9S08LG32 MCU Series, Rev. 5
Freescale Semiconductor 9
Contents
Section Number Title Page
Chapter 1
Device Overview
1.1 Devices in the MC9S08LG32 Series ...............................................................................................21
1.2 MCU Block Diagram .......................................................................................................................22
1.3 System Clock Distribution ...............................................................................................................24
Chapter 2
Pins and Connections
2.1 Introduction ......................................................................................................................................27
2.2 Device Pin Assignment ....................................................................................................................27
2.3 Recommended System Connections ................................................................................................31
2.3.1 Power ................................................................................................................................33
2.3.2 Oscillator ...........................................................................................................................33
2.3.3 RESET ..............................................................................................................................34
2.3.4 Background / Mode Select (BKGD/MS) ..........................................................................34
2.3.5 IRQ ....................................................................................................................................35
2.3.6 LCD Pins ...........................................................................................................................35
2.3.7 General-Purpose I/O (GPIO) and Peripheral Ports ...........................................................36
Chapter 3
Modes of Operation
3.1 Introduction ......................................................................................................................................41
3.2 Features ............................................................................................................................................41
3.3 Run Mode.........................................................................................................................................41
3.4 Active Background Mode ................................................................................................................41
3.5 Wait Mode ........................................................................................................................................42
3.6 Stop Modes.......................................................................................................................................43
3.6.1 Stop2 Mode .......................................................................................................................43
3.6.2 Stop3 Mode .......................................................................................................................44
3.6.3 Active BDM Enabled in Stop Mode .................................................................................45
3.6.4 LVD Enabled in Stop Mode ..............................................................................................45
3.7 Mode Selection.................................................................................................................................45
3.7.1 On-Chip Peripheral Modules in Stop Modes ....................................................................48
Chapter 4
Memory
4.1 Introduction ......................................................................................................................................49

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10 Freescale Semiconductor
Section Number Title Page
4.2 MC9S08LG32 Series Memory Map ................................................................................................49
4.3 Reset and Interrupt Vector Assignments ..........................................................................................50
4.4 Register Addresses and Bit Assignments.........................................................................................52
4.4.1 Reserved Flash Locations .................................................................................................59
4.5 RAM.................................................................................................................................................60
4.6 Flash .................................................................................................................................................60
4.6.1 Features .............................................................................................................................61
4.6.2 Program and Erase Times .................................................................................................61
4.6.3 Program and Erase Command Execution .........................................................................62
4.6.4 Burst Program Execution ..................................................................................................63
4.6.5 Access Errors ....................................................................................................................65
4.6.6 Flash Block Protection ......................................................................................................65
4.6.7 Vector Redirection ............................................................................................................66
4.7 Security.............................................................................................................................................66
4.8 Flash Registers and Control Bits......................................................................................................67
4.8.1 Flash Clock Divider Register (FCDIV) ............................................................................68
4.8.2 Flash Options Register (FOPT and NVOPT) ....................................................................69
4.8.3 Flash Configuration Register (FCNFG) ...........................................................................70
4.8.4 Flash Protection Register (FPROT and NVPROT) ..........................................................70
4.8.5 Flash Status Register (FSTAT) ..........................................................................................71
4.8.6 Flash Command Register (FCMD) ...................................................................................72
Chapter 5
Resets, Interrupts, and General System Control
5.1 Introduction ......................................................................................................................................73
5.2 Features ............................................................................................................................................73
5.3 MCU Reset.......................................................................................................................................73
5.4 Computer Operating Properly (COP) Watchdog..............................................................................74
5.5 Interrupts ..........................................................................................................................................75
5.5.1 Interrupt Stack Frame .......................................................................................................76
5.5.2 External Interrupt Request (IRQ) Pin ...............................................................................76
5.5.3 Interrupt Vectors, Sources, and Local Masks ...................................................................77
5.6 Low-Voltage Detect (LVD) System .................................................................................................79
5.6.1 Power-On Reset Operation ...............................................................................................79
5.6.2 Low-Voltage Detection (LVD) Reset Operation ...............................................................79
5.6.3 Low-Voltage Warning (LVW) Interrupt Operation ...........................................................79
5.7 Peripheral Clock Gating ...................................................................................................................79
5.8 Reset, Interrupt, and System Control Registers and Control Bits....................................................80
5.8.1 Interrupt Pin Request Status and Control Register (IRQSC) ............................................80
5.8.2 System Reset Status Register (SRS) .................................................................................82
5.8.3 System Background Debug Force Reset Register (SBDFR) ............................................83
5.8.4 System Options Register 1 (SOPT1) ................................................................................84

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Section Number Title Page
5.8.5 System Options Register 2 (SOPT2) ................................................................................85
5.8.6 System Device Identification Register (SDIDH, SDIDL) ................................................86
5.8.7 System Power Management Status and Control 1 Register (SPMSC1) ...........................87
5.8.8 System Power Management Status and Control 2 Register (SPMSC2) ...........................88
5.8.9 System Clock Gating Control 1Register (SCGC1) ...........................................................90
5.8.10 System Clock Gating Control 2 Register (SCGC2) ..........................................................91
5.8.11 Pin Position Control Register (PINPS1) ...........................................................................92
5.8.12 Pin Position Control Register (PINPS2) ...........................................................................93
5.8.13 Pin Position Control Register (PINPS3) ...........................................................................94
5.8.14 Pin Position Control Register (PINPS4) ...........................................................................95
Chapter 6
Parallel Input/Output Control
6.1 Introduction ......................................................................................................................................97
6.2 Pins Shared with LCD......................................................................................................................97
6.3 Port Data and Data Direction ...........................................................................................................97
6.4 Pullup, Slew Rate, and Drive Strength.............................................................................................98
6.4.1 Port Internal Pullup Enable ...............................................................................................98
6.4.2 Port Slew Rate Enable ......................................................................................................99
6.4.3 Port Drive Strength Select ................................................................................................99
6.5 Open Drain Operation ......................................................................................................................99
6.6 Pin Behavior in Stop Modes.............................................................................................................99
6.7 Parallel I/O and Pin Control Registers ...........................................................................................100
6.7.1 Port A Registers ..............................................................................................................100
6.7.2 Port B Registers ..............................................................................................................104
6.7.3 Port C Registers ..............................................................................................................107
6.7.4 Port D Registers ..............................................................................................................110
6.7.5 Port E Registers ..............................................................................................................113
6.7.6 Port F Registers ...............................................................................................................116
6.7.7 Port G Registers ..............................................................................................................119
6.7.8 Port H Registers ..............................................................................................................122
6.7.9 Port I Registers ................................................................................................................125
Chapter 7
Keyboard Interrupt (S08KBIV2)
7.1 Introduction ....................................................................................................................................128
7.1.1 Module Configuration .....................................................................................................128
7.1.2 KBI Clock Gating ...........................................................................................................128
7.1.3 Features ...........................................................................................................................130
7.1.4 Modes of Operation ........................................................................................................130
7.1.5 Block Diagram ................................................................................................................130
7.2 External Signal Description ...........................................................................................................131

MC9S08LG32 MCU Series, Rev. 5
12 Freescale Semiconductor
Section Number Title Page
7.3 Register Definition .........................................................................................................................131
7.3.1 KBI Status and Control Register (KBISC) .....................................................................131
7.3.2 KBI Pin Enable Register (KBIPE) ..................................................................................132
7.3.3 KBI Edge Select Register (KBIES) ................................................................................132
7.4 Functional Description ...................................................................................................................133
7.4.1 Edge Only Sensitivity .....................................................................................................133
7.4.2 Edge and Level Sensitivity .............................................................................................133
7.4.3 KBI Pullup/Pulldown Resistors ......................................................................................134
7.4.4 KBI Initialization ............................................................................................................134
Chapter 8
Central Processor Unit (S08CPUV5)
8.1 Introduction ....................................................................................................................................135
8.1.1 Features ...........................................................................................................................135
8.2 Programmer’s Model and CPU Registers ......................................................................................136
8.2.1 Accumulator (A) .............................................................................................................136
8.2.2 Index Register (H:X) ......................................................................................................136
8.2.3 Stack Pointer (SP) ...........................................................................................................137
8.2.4 Program Counter (PC) ....................................................................................................137
8.2.5 Condition Code Register (CCR) .....................................................................................137
8.3 Addressing Modes..........................................................................................................................139
8.3.1 Inherent Addressing Mode (INH) ...................................................................................139
8.3.2 Relative Addressing Mode (REL) ..................................................................................139
8.3.3 Immediate Addressing Mode (IMM) ..............................................................................139
8.3.4 Direct Addressing Mode (DIR) ......................................................................................139
8.3.5 Extended Addressing Mode (EXT) ................................................................................140
8.3.6 Indexed Addressing Mode ..............................................................................................140
8.4 Special Operations..........................................................................................................................141
8.4.1 Reset Sequence ...............................................................................................................141
8.4.2 Interrupt Sequence ..........................................................................................................141
8.4.3 Wait Mode Operation ......................................................................................................142
8.4.4 Stop Mode Operation ......................................................................................................142
8.4.5 BGND Instruction ...........................................................................................................143
8.5 HCS08 Instruction Set Summary ...................................................................................................144
Chapter 9
LCD Module (S08LCDLPV1)
9.1 Introduction ....................................................................................................................................158
9.1.1 LCD Clock Sources ........................................................................................................158
9.1.2 LCD Modes of Operation ...............................................................................................158
9.1.3 LCD Status after Stop2 Wakeup .....................................................................................158
9.1.4 LCD Clock Gating ..........................................................................................................158

MC9S08LG32 MCU Series, Rev. 5
Freescale Semiconductor 13
Section Number Title Page
9.1.5 Features ...........................................................................................................................160
9.1.6 Modes of Operation ........................................................................................................161
9.1.7 Block Diagram ................................................................................................................161
9.2 External Signal Description ...........................................................................................................162
9.2.1 LCD[44:0] .......................................................................................................................163
9.2.2 VLL1, VLL2, VLL3 ...........................................................................................................163
9.2.3 Vcap1, Vcap2 .....................................................................................................................163
9.3 Register Definition .........................................................................................................................163
9.3.1 LCD Control Register 0 (LCDC0) ..................................................................................163
9.3.2 LCD Control Register 1 (LCDC1) ..................................................................................164
9.3.3 LCD Voltage Supply Register (LCDSUPPLY) ...............................................................165
9.3.4 LCD Regulated Voltage Control Register (LCDRVC) ...................................................166
9.3.5 LCD Blink Control Register (LCDBCTL) .....................................................................167
9.3.6 LCD Status Register (LCDS) ..........................................................................................168
9.3.7 LCD Pin Enable Registers 0–5 (LCDPEN0–LCDPEN5) ..............................................168
9.3.8 Backplane Enable Registers 0–5 (BPEN0–BPEN5) ......................................................169
9.3.9 LCD Waveform Registers (LCDWF[44:0]) ...................................................................170
9.4 Functional Description ...................................................................................................................174
9.4.1 LCD Driver Description .................................................................................................175
9.4.2 LCDWF Registers ...........................................................................................................183
9.4.3 LCD Display Modes .......................................................................................................183
9.4.4 LCD Charge Pump, Voltage Divider, and Power Supply Operation ..............................185
9.4.5 Resets ..............................................................................................................................188
9.4.6 Interrupts .........................................................................................................................189
9.5 Initialization Section ......................................................................................................................189
9.5.1 Initialization Sequence ....................................................................................................189
9.5.2 Initialization Examples ...................................................................................................190
9.6 Application Information.................................................................................................................194
9.6.1 LCD Seven Segment Example Description ....................................................................195
9.6.2 LCD Contrast Control .....................................................................................................198
9.6.3 Stop Mode Recovery .......................................................................................................199
Chapter 10
Analog-to-Digital Converter (S08ADC12V1)
10.1 Introduction ....................................................................................................................................200
10.1.1 ADC shared with LCD ...................................................................................................200
10.1.2 ADC Reference and Supply Voltage ...............................................................................200
10.1.3 ADC Clock Gating ..........................................................................................................200
10.1.4 Module Configurations ...................................................................................................201
10.1.5 Features ...........................................................................................................................204
10.1.6 ADC Module Block Diagram .........................................................................................204
10.2 External Signal Description ...........................................................................................................205

MC9S08LG32 MCU Series, Rev. 5
14 Freescale Semiconductor
Section Number Title Page
10.2.1 Analog Power (VDDA) ....................................................................................................206
10.2.2 Analog Ground (VSSA) ...................................................................................................206
10.2.3 Voltage Reference High (VREFH) ...................................................................................206
10.2.4 Voltage Reference Low (VREFL) ....................................................................................206
10.2.5 Analog Channel Inputs (ADx) ........................................................................................206
10.3 Register Definition .........................................................................................................................206
10.3.1 Status and Control Register 1 (ADCSC1) ......................................................................206
10.3.2 Status and Control Register 2 (ADCSC2) ......................................................................208
10.3.3 Data Result High Register (ADCRH) .............................................................................208
10.3.4 Data Result Low Register (ADCRL) ..............................................................................209
10.3.5 Compare Value High Register (ADCCVH) ....................................................................209
10.3.6 Compare Value Low Register (ADCCVL) .....................................................................210
10.3.7 Configuration Register (ADCCFG) ................................................................................210
10.3.8 Pin Control 1 Register (APCTL1) ..................................................................................211
10.3.9 Pin Control 2 Register (APCTL2) ..................................................................................212
10.3.10Pin Control 3 Register (APCTL3) ..................................................................................213
10.4 Functional Description ...................................................................................................................214
10.4.1 Clock Select and Divide Control ....................................................................................215
10.4.2 Input Select and Pin Control ...........................................................................................215
10.4.3 Hardware Trigger ............................................................................................................215
10.4.4 Conversion Control .........................................................................................................215
10.4.5 Automatic Compare Function .........................................................................................218
10.4.6 MCU Wait Mode Operation ............................................................................................218
10.4.7 MCU Stop3 Mode Operation ..........................................................................................219
10.4.8 MCU Stop2 Mode Operation ..........................................................................................219
10.5 Initialization Information ...............................................................................................................220
10.5.1 ADC Module Initialization Example ..............................................................................220
10.6 Application Information.................................................................................................................222
10.6.1 External Pins and Routing ..............................................................................................222
10.6.2 Sources of Error ..............................................................................................................223
Chapter 11
Internal Clock Source (S08ICSV3)
11.1 Introduction ....................................................................................................................................226
11.1.1 Features ...........................................................................................................................228
11.1.2 Block Diagram ................................................................................................................228
11.1.3 Modes of Operation ........................................................................................................229
11.2 External Signal Description ...........................................................................................................230
11.3 Register Definition .........................................................................................................................230
11.3.1 ICS Control Register 1 (ICSC1) .....................................................................................231
11.3.2 ICS Control Register 2 (ICSC2) .....................................................................................233
11.3.3 ICS Trim Register (ICSTRM) .........................................................................................233

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Freescale Semiconductor 15
Section Number Title Page
11.3.4 ICS Status and Control (ICSSC) .....................................................................................234
11.4 Functional Description ...................................................................................................................236
11.4.1 Operational Modes ..........................................................................................................236
11.4.2 Mode Switching ..............................................................................................................238
11.4.3 Bus Frequency Divider ...................................................................................................239
11.4.4 Low Power Bit Usage .....................................................................................................239
11.4.5 DCO Maximum Frequency with 32.768 kHz Oscillator ................................................239
11.4.6 Internal Reference Clock ................................................................................................239
11.4.7 External Reference Clock ...............................................................................................240
11.4.8 Fixed Frequency Clock ...................................................................................................240
11.4.9 Local Clock .....................................................................................................................240
Chapter 12
Inter-Integrated Circuit (S08IICV2)
12.1 Introduction ....................................................................................................................................241
12.1.1 Module Configuration .....................................................................................................241
12.1.2 IIC Clock Gating .............................................................................................................241
12.1.3 Features ...........................................................................................................................243
12.1.4 Modes of Operation ........................................................................................................243
12.1.5 Block Diagram ................................................................................................................243
12.2 External Signal Description ...........................................................................................................244
12.2.1 SCL — Serial Clock Line ...............................................................................................244
12.2.2 SDA — Serial Data Line ................................................................................................244
12.3 Register Definition .........................................................................................................................244
12.3.1 IIC Address Register (IICxA) .........................................................................................245
12.3.2 IIC Frequency Divider Register (IICxF) ........................................................................245
12.3.3 IIC Control Register (IICxC1) ........................................................................................248
12.3.4 IIC Status Register (IICxS) .............................................................................................248
12.3.5 IIC Data I/O Register (IICxD) ........................................................................................249
12.3.6 IIC Control Register 2 (IICxC2) .....................................................................................250
12.4 Functional Description ...................................................................................................................251
12.4.1 IIC Protocol .....................................................................................................................251
12.4.2 10-bit Address .................................................................................................................254
12.4.3 General Call Address ......................................................................................................255
12.5 Resets .............................................................................................................................................255
12.6 Interrupts ........................................................................................................................................255
12.6.1 Byte Transfer Interrupt ....................................................................................................255
12.6.2 Address Detect Interrupt .................................................................................................256
12.6.3 Arbitration Lost Interrupt ................................................................................................256
12.7 Initialization/Application Information ...........................................................................................257

MC9S08LG32 MCU Series, Rev. 5
16 Freescale Semiconductor
Section Number Title Page
Chapter 13
Serial Communications Interface (S08SCIV4)
13.1 Introduction ....................................................................................................................................259
13.1.1 Module Instances ............................................................................................................259
13.1.2 Module Configuration .....................................................................................................259
13.1.3 SCI Clock Gating ............................................................................................................259
13.1.4 Features ...........................................................................................................................261
13.1.5 Modes of Operation ........................................................................................................261
13.1.6 Block Diagram ................................................................................................................262
13.2 Register Definition .........................................................................................................................264
13.2.1 SCI Baud Rate Registers (SCIxBDH, SCIxBDL) ..........................................................264
13.2.2 SCI Control Register 1 (SCIxC1) ...................................................................................265
13.2.3 SCI Control Register 2 (SCIxC2) ...................................................................................266
13.2.4 SCI Status Register 1 (SCIxS1) ......................................................................................267
13.2.5 SCI Status Register 2 (SCIxS2) ......................................................................................269
13.2.6 SCI Control Register 3 (SCIxC3) ...................................................................................270
13.2.7 SCI Data Register (SCIxD) .............................................................................................271
13.3 Functional Description ...................................................................................................................271
13.3.1 Baud Rate Generation .....................................................................................................271
13.3.2 Transmitter Functional Description ................................................................................272
13.3.3 Receiver Functional Description ....................................................................................273
13.3.4 Interrupts and Status Flags ..............................................................................................275
13.3.5 Additional SCI Functions ...............................................................................................276
Chapter 14
Serial Peripheral Interface (S08SPIV4)
14.1 Introduction ....................................................................................................................................278
14.1.1 Module Configuration .....................................................................................................278
14.1.2 SPI Clock Gating ............................................................................................................278
14.1.3 Features ...........................................................................................................................280
14.1.4 Block Diagrams ..............................................................................................................280
14.1.5 SPI Baud Rate Generation ..............................................................................................282
14.2 External Signal Description ...........................................................................................................283
14.2.1 SPSCK — SPI Serial Clock ............................................................................................283
14.2.2 MOSI — Master Data Out, Slave Data In ......................................................................283
14.2.3 MISO — Master Data In, Slave Data Out ......................................................................283
14.2.4 SS — Slave Select ..........................................................................................................283
14.3 Modes of Operation........................................................................................................................284
14.3.1 SPI in Stop Modes ..........................................................................................................284
14.4 Register Definition .........................................................................................................................284
14.4.1 SPI Control Register 1 (SPIxC1) ....................................................................................284
14.4.2 SPI Control Register 2 (SPIxC2) ....................................................................................285

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Section Number Title Page
14.4.3 SPI Baud Rate Register (SPIxBR) ..................................................................................286
14.4.4 SPI Status Register (SPIxS) ............................................................................................287
14.4.5 SPI Data Register (SPIxD) .............................................................................................288
14.5 Functional Description ...................................................................................................................289
14.5.1 Master Mode ...................................................................................................................289
14.5.2 Slave Mode .....................................................................................................................290
14.5.3 SPI Clock Formats ..........................................................................................................291
14.5.4 Special Features ..............................................................................................................293
14.5.5 SPI Interrupts ..................................................................................................................295
14.5.6 Mode Fault Detection .....................................................................................................295
Chapter 15
Real-Time Counter (S08RTCV1)
15.1 Introduction ....................................................................................................................................297
15.1.1 RTC Clock Gating ..........................................................................................................297
15.1.2 Features ...........................................................................................................................299
15.1.3 Modes of Operation ........................................................................................................299
15.1.4 Block Diagram ................................................................................................................300
15.2 External Signal Description ...........................................................................................................300
15.3 Register Definition .........................................................................................................................300
15.3.1 RTC Status and Control Register (RTCSC) ....................................................................301
15.3.2 RTC Counter Register (RTCCNT) ..................................................................................302
15.3.3 RTC Modulo Register (RTCMOD) ................................................................................302
15.4 Functional Description ...................................................................................................................302
15.4.1 RTC Operation Example .................................................................................................303
15.5 Initialization/Application Information ...........................................................................................304
Chapter 16
Timer/Pulse-Width Modulator (S08TPMV3)
16.1 Introduction ....................................................................................................................................306
16.1.1 TPM External Clock .......................................................................................................306
16.1.2 Module Instances ............................................................................................................306
16.1.3 Module Configuration .....................................................................................................306
16.1.4 TPM Clock Gating ..........................................................................................................307
16.1.5 Features ...........................................................................................................................308
16.1.6 Modes of Operation ........................................................................................................308
16.1.7 Block Diagram ................................................................................................................309
16.2 Signal Description ..........................................................................................................................311
16.2.1 Detailed Signal Descriptions ..........................................................................................311
16.3 Register Definition .........................................................................................................................314
16.3.1 TPM Status and Control Register (TPMxSC) ................................................................314
16.3.2 TPM-Counter Registers (TPMxCNTH:TPMxCNTL) ....................................................315

MC9S08LG32 MCU Series, Rev. 5
18 Freescale Semiconductor
Section Number Title Page
16.3.3 TPM Counter Modulo Registers (TPMxMODH:TPMxMODL) ....................................316
16.3.4 TPM Channel n Status and Control Register (TPMxCnSC) ..........................................317
16.3.5 TPM Channel Value Registers (TPMxCnVH:TPMxCnVL) ..........................................318
16.4 Functional Description ...................................................................................................................319
16.4.1 Counter ............................................................................................................................320
16.4.2 Channel Mode Selection .................................................................................................321
16.5 Reset Overview ..............................................................................................................................324
16.5.1 General ............................................................................................................................324
16.5.2 Description of Reset Operation .......................................................................................324
16.6 Interrupts ........................................................................................................................................324
16.6.1 General ............................................................................................................................324
16.6.2 Description of Interrupt Operation .................................................................................325
Chapter 17
Modulo Timer (S08MTIMV1)
17.1 Introduction ....................................................................................................................................327
17.1.1 MTIM Clock Gating .......................................................................................................327
17.1.2 Features ...........................................................................................................................329
17.1.3 Modes of Operation ........................................................................................................329
17.1.4 Block Diagram ................................................................................................................330
17.2 External Signal Description ...........................................................................................................330
17.3 Memory Map and Register Definition ...........................................................................................331
17.3.1 Memory Map (Register Summary) .................................................................................331
17.3.2 Register Descriptions ......................................................................................................331
17.4 Functional Description ...................................................................................................................335
17.4.1 MTIM Operation Example .............................................................................................336
Chapter 18
Development Support
18.1 Introduction ....................................................................................................................................337
18.1.1 Forcing Active Background ............................................................................................337
18.1.2 Module Configuration .....................................................................................................337
18.1.3 Features ...........................................................................................................................338
18.2 Background Debug Controller (BDC) ...........................................................................................338
18.2.1 BKGD Pin Description ...................................................................................................339
18.2.2 Communication Details ..................................................................................................339
18.2.3 BDC Commands .............................................................................................................343
18.2.4 BDC Hardware Breakpoint .............................................................................................345
18.3 Register Definition .........................................................................................................................345
18.3.1 BDC Registers and Control Bits .....................................................................................346
18.3.2 System Background Debug Force Reset Register (SBDFR) ..........................................348

MC9S08LG32 MCU Series, Rev. 5
Freescale Semiconductor 19
Section Number Title Page
Chapter 19
Debug Module (DBG) (64K)
19.1 Introduction ....................................................................................................................................350
19.1.1 Features ...........................................................................................................................350
19.1.2 Modes of Operation ........................................................................................................351
19.1.3 Block Diagram ................................................................................................................351
19.2 Signal Description ..........................................................................................................................352
19.3 Memory Map and Registers ...........................................................................................................352
19.3.1 Module Memory Map .....................................................................................................352
19.3.2 Register Descriptions ......................................................................................................354
19.4 Functional Description ...................................................................................................................365
19.4.1 Comparator .....................................................................................................................365
19.4.2 Breakpoints .....................................................................................................................365
19.4.3 Trigger Selection .............................................................................................................366
19.4.4 Trigger Break Control (TBC) .........................................................................................366
19.4.5 FIFO ................................................................................................................................370
19.4.6 Interrupt Priority .............................................................................................................371
19.5 Resets .............................................................................................................................................371
19.6 Interrupts ........................................................................................................................................371