NXP Semiconductors K53 Series User manual

K53 Sub-Family Reference Manual
Supports: MK53DN512ZCLQ10, MK53DN512ZCMD10,
MK53DX256ZCLQ10, MK53DX256ZCMD10
Document Number: K53P144M100SF2RM
Rev. 6, Nov 2011

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Contents
Section Number Title Page
Chapter 1
About This Document
1.1 Overview.......................................................................................................................................................................59
1.1.1 Purpose.........................................................................................................................................................59
1.1.2 Audience......................................................................................................................................................59
1.2 Conventions..................................................................................................................................................................59
1.2.1 Numbering systems......................................................................................................................................59
1.2.2 Typographic notation...................................................................................................................................60
1.2.3 Special terms................................................................................................................................................60
Chapter 2
Introduction
2.1 Overview.......................................................................................................................................................................61
2.2 K50 Family Introduction...............................................................................................................................................61
2.3 Module Functional Categories......................................................................................................................................61
2.3.1 ARM Cortex-M4 Core Modules..................................................................................................................63
2.3.2 System Modules...........................................................................................................................................63
2.3.3 Memories and Memory Interfaces...............................................................................................................64
2.3.4 Clocks...........................................................................................................................................................65
2.3.5 Security and Integrity modules....................................................................................................................66
2.3.6 Analog modules...........................................................................................................................................66
2.3.7 Timer modules.............................................................................................................................................66
2.3.8 Communication interfaces...........................................................................................................................68
2.3.9 Human-machine interfaces..........................................................................................................................68
2.4 Orderable part numbers.................................................................................................................................................69
Chapter 3
Chip Configuration
3.1 Introduction...................................................................................................................................................................71
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Section Number Title Page
3.2 Core modules................................................................................................................................................................71
3.2.1 ARM Cortex-M4 Core Configuration..........................................................................................................71
3.2.2 Nested Vectored Interrupt Controller (NVIC) Configuration......................................................................74
3.2.3 Asynchronous Wake-up Interrupt Controller (AWIC) Configuration.........................................................80
3.2.4 JTAG Controller Configuration...................................................................................................................81
3.3 System modules............................................................................................................................................................82
3.3.1 SIM Configuration.......................................................................................................................................82
3.3.2 Mode Controller Configuration...................................................................................................................83
3.3.3 PMC Configuration......................................................................................................................................83
3.3.4 Low-Leakage Wake-up Unit (LLWU) Configuration.................................................................................84
3.3.5 MCM Configuration....................................................................................................................................86
3.3.6 Crossbar Switch Configuration....................................................................................................................86
3.3.7 Memory Protection Unit (MPU) Configuration...........................................................................................89
3.3.8 Peripheral Bridge Configuration..................................................................................................................91
3.3.9 DMA request multiplexer configuration......................................................................................................93
3.3.10 DMA Controller Configuration...................................................................................................................96
3.3.11 External Watchdog Monitor (EWM) Configuration....................................................................................97
3.3.12 Watchdog Configuration..............................................................................................................................98
3.4 Clock Modules..............................................................................................................................................................99
3.4.1 MCG Configuration.....................................................................................................................................99
3.4.2 OSC Configuration......................................................................................................................................100
3.4.3 RTC OSC configuration...............................................................................................................................101
3.5 Memories and Memory Interfaces................................................................................................................................101
3.5.1 Flash Memory Configuration.......................................................................................................................101
3.5.2 Flash Memory Controller Configuration.....................................................................................................105
3.5.3 SRAM Configuration...................................................................................................................................106
3.5.4 SRAM Controller Configuration.................................................................................................................110
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Section Number Title Page
3.5.5 System Register File Configuration.............................................................................................................110
3.5.6 VBAT Register File Configuration..............................................................................................................111
3.5.7 EzPort Configuration...................................................................................................................................112
3.5.8 FlexBus Configuration.................................................................................................................................113
3.6 Security.........................................................................................................................................................................116
3.6.1 CRC Configuration......................................................................................................................................116
3.6.2 MMCAU Configuration...............................................................................................................................117
3.6.3 RNG Configuration......................................................................................................................................118
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Section Number Title Page
3.7 Analog...........................................................................................................................................................................118
3.7.1 16-bit SAR ADC with PGA Configuration.................................................................................................118
3.7.2 CMP Configuration......................................................................................................................................126
3.7.3 12-bit DAC Configuration...........................................................................................................................128
3.7.4 Op-amp Configuration.................................................................................................................................129
3.7.5 TRIAMP Configuration...............................................................................................................................131
3.7.6 VREF Configuration....................................................................................................................................132
3.8 Timers...........................................................................................................................................................................133
3.8.1 PDB Configuration......................................................................................................................................133
3.8.2 FlexTimer Configuration.............................................................................................................................137
3.8.3 PIT Configuration........................................................................................................................................140
3.8.4 Low-power timer configuration...................................................................................................................141
3.8.5 CMT Configuration......................................................................................................................................143
3.8.6 RTC configuration.......................................................................................................................................144
3.9 Communication interfaces............................................................................................................................................145
3.9.1 Ethernet Configuration.................................................................................................................................145
3.9.2 Universal Serial Bus (USB) Subsystem.......................................................................................................147
3.9.3 SPI configuration.........................................................................................................................................153
3.9.4 I2C Configuration........................................................................................................................................156
3.9.5 UART Configuration...................................................................................................................................157
3.9.6 SDHC Configuration....................................................................................................................................159
3.9.7 I2S configuration..........................................................................................................................................160
3.10 Human-machine interfaces (HMI)................................................................................................................................162
3.10.1 GPIO configuration......................................................................................................................................162
3.10.2 TSI Configuration........................................................................................................................................163
3.10.3 Segment LCD Configuration.......................................................................................................................166
Chapter 4
Memory Map
4.1 Introduction...................................................................................................................................................................169
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Section Number Title Page
4.2 System memory map.....................................................................................................................................................169
4.2.1 Aliased bit-band regions..............................................................................................................................170
4.3 Flash Memory Map.......................................................................................................................................................171
4.3.1 Alternate Non-Volatile IRC User Trim Description....................................................................................172
4.4 SRAM memory map.....................................................................................................................................................173
4.5 Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory maps...................................................................................173
4.5.1 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map........................................................................................173
4.5.2 Peripheral Bridge 1 (AIPS-Lite 1) Memory Map........................................................................................177
4.6 Private Peripheral Bus (PPB) memory map..................................................................................................................182
Chapter 5
Clock Distribution
5.1 Introduction...................................................................................................................................................................183
5.2 Programming model......................................................................................................................................................183
5.3 High-Level device clocking diagram............................................................................................................................183
5.4 Clock definitions...........................................................................................................................................................184
5.4.1 Device clock summary.................................................................................................................................185
5.5 Internal clocking requirements.....................................................................................................................................187
5.5.1 Clock divider values after reset....................................................................................................................188
5.5.2 VLPR mode clocking...................................................................................................................................188
5.6 Clock Gating.................................................................................................................................................................189
5.7 Module clocks...............................................................................................................................................................189
5.7.1 PMC 1-kHz LPO clock................................................................................................................................191
5.7.2 WDOG clocking..........................................................................................................................................191
5.7.3 Debug trace clock.........................................................................................................................................191
5.7.4 PORT digital filter clocking.........................................................................................................................192
5.7.5 LPTMR clocking..........................................................................................................................................192
5.7.6 Ethernet Clocking........................................................................................................................................193
5.7.7 USB FS OTG Controller clocking...............................................................................................................193
5.7.8 UART clocking............................................................................................................................................194
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Section Number Title Page
5.7.9 SDHC clocking............................................................................................................................................194
5.7.10 I2S clocking.................................................................................................................................................195
5.7.11 TSI clocking.................................................................................................................................................195
Chapter 6
Reset and Boot
6.1 Introduction...................................................................................................................................................................197
6.2 Reset..............................................................................................................................................................................197
6.2.1 Power-on reset (POR)..................................................................................................................................198
6.2.2 System resets................................................................................................................................................198
6.2.3 Debug resets.................................................................................................................................................201
6.3 Boot...............................................................................................................................................................................203
6.3.1 Boot sources.................................................................................................................................................203
6.3.2 Boot options.................................................................................................................................................203
6.3.3 FOPT boot options.......................................................................................................................................203
6.3.4 Boot sequence..............................................................................................................................................204
Chapter 7
Power Management
7.1 Introduction...................................................................................................................................................................207
7.2 Power modes.................................................................................................................................................................207
7.3 Entering and exiting power modes...............................................................................................................................209
7.4 Power mode transitions.................................................................................................................................................210
7.5 Power modes shutdown sequencing.............................................................................................................................211
7.6 Module Operation in Low Power Modes......................................................................................................................211
7.7 Clock Gating.................................................................................................................................................................214
Chapter 8
Security
8.1 Introduction...................................................................................................................................................................215
8.2 Flash Security...............................................................................................................................................................215
8.3 Security Interactions with other Modules.....................................................................................................................216
8.3.1 Security interactions with FlexBus..............................................................................................................216
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Section Number Title Page
8.3.2 Security Interactions with EzPort................................................................................................................216
8.3.3 Security Interactions with Debug.................................................................................................................216
Chapter 9
Debug
9.1 Introduction...................................................................................................................................................................219
9.1.1 References....................................................................................................................................................221
9.2 The Debug Port.............................................................................................................................................................221
9.2.1 JTAG-to-SWD change sequence.................................................................................................................222
9.2.2 JTAG-to-cJTAG change sequence...............................................................................................................222
9.3 Debug Port Pin Descriptions.........................................................................................................................................223
9.4 System TAP connection................................................................................................................................................223
9.4.1 IR Codes.......................................................................................................................................................223
9.5 JTAG status and control registers.................................................................................................................................224
9.5.1 MDM-AP Control Register..........................................................................................................................225
9.5.2 MDM-AP Status Register............................................................................................................................227
9.6 Debug Resets................................................................................................................................................................228
9.7 AHB-AP........................................................................................................................................................................229
9.8 ITM...............................................................................................................................................................................230
9.9 Core Trace Connectivity...............................................................................................................................................230
9.10 Embedded Trace Macrocell v3.5 (ETM)......................................................................................................................230
9.11 Coresight Embedded Trace Buffer (ETB)....................................................................................................................231
9.11.1 Performance Profiling with the ETB...........................................................................................................231
9.11.2 ETB Counter Control...................................................................................................................................232
9.12 TPIU..............................................................................................................................................................................232
9.13 DWT.............................................................................................................................................................................232
9.14 Debug in Low Power Modes........................................................................................................................................233
9.14.1 Debug Module State in Low Power Modes.................................................................................................234
9.15 Debug & Security.........................................................................................................................................................234
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Section Number Title Page
Chapter 10
Signal Multiplexing and Signal Descriptions
10.1 Introduction...................................................................................................................................................................235
10.2 Signal Multiplexing Integration....................................................................................................................................235
10.2.1 Port control and interrupt module features..................................................................................................236
10.2.2 Clock gating.................................................................................................................................................236
10.2.3 Signal multiplexing constraints....................................................................................................................236
10.3 Pinout............................................................................................................................................................................237
10.3.1 K53 Signal Multiplexing and Pin Assignments...........................................................................................237
10.3.2 K53 Pinouts..................................................................................................................................................243
10.4 Module Signal Description Tables................................................................................................................................245
10.4.1 Core Modules...............................................................................................................................................245
10.4.2 System Modules...........................................................................................................................................246
10.4.3 Clock Modules.............................................................................................................................................247
10.4.4 Memories and Memory Interfaces...............................................................................................................247
10.4.5 Analog..........................................................................................................................................................248
10.4.6 Communication Interfaces...........................................................................................................................250
10.4.7 Human-Machine Interfaces (HMI)..............................................................................................................257
Chapter 11
Port control and interrupts (PORT)
11.1 Introduction...................................................................................................................................................................259
11.1.1 Overview......................................................................................................................................................259
11.1.2 Features........................................................................................................................................................259
11.1.3 Modes of operation......................................................................................................................................260
11.2 External signal description............................................................................................................................................261
11.3 Detailed signal descriptions..........................................................................................................................................261
11.4 Memory map and register definition.............................................................................................................................261
11.4.1 Pin Control Register n (PORTx_PCRn).......................................................................................................268
11.4.2 Global Pin Control Low Register (PORTx_GPCLR)..................................................................................270
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