NXP Semiconductors LPC18xx series User manual

UM10430
LPC18xx ARM Cortex-M3 microcontroller
Rev. 3.0 — 26 July 2017 User manual
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Keywords LPC18xx, LPC1850, LPC1830, LPC1820, LPC1810, LPC185x, LPC183x,
LPC182x, LPC181x, LPC18Sxx, LPC18S50, LPC18S30, LPC18S20,
LPC18S10, LPC18S5x, LPC18S3x, LPC18S2x, LPC18S1x, ARM Cortex-M3,
SPIFI, SCT, USB, Ethernet, LPC1800, LPC1800 User manual
Abstract LPC18xx user manual

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User manual Rev. 3.0 — 26 July 2017 2 of 1284
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Revision history
Rev Date Description
3.0 20170726 LPC18xx user manual
Modifications: •Updated Section 12.2.1.1 “Changing the BASE_M3_CLK after power-up, reset, or deep power-down
mode”. Added list item 4.
•Updated Section 12.2.1.2 “Changing the BASE_M3_CLK after waking up from deep-sleep or
power-down modes”. Added list item 3.
•Updated Table 114 “PLL0USB control register (PLL0USB_CTRL, address 0x4005 0020) bit
description”. Added table note to AUTOBLOCK, bit 11.
•Updated Table 118 “PLL0AUDIO control register (PLL0AUDIO_CTRL, address 0x4005 0030) bit
description”. Added table note to AUTOBLOCK, bit 11.
•Updated Table 123 “PLL1_CTRL register (PLL1_CTRL, address 0x4005 0044) bit description”.
Added table note to AUTOBLOCK, bit 11.
2.9 20170118 LPC18xx user manual
Modifications: •Fixed formatting issues.
•Updated Table 19 “QSPI devices supported by the boot code and the SPIFI API”:
•Deleted Table: QSPI devices not supported by the boot code.
2.8 20151210 LPC18xx user manual
Modifications: •Fixed formatting issues.
•Added CREG1 register. See Table 90 “CREG1 register (CREG1, address 0x4004 3008) bit
description”.
•Updated text in Section 12.2.1 “Configuring the BASE_M3_CLK for high operating frequencies”: To
ramp up the clock frequency to an operating frequency above 110 MHz configure the core clock
BASE_M4_CLK as described in Section 12.2.1.1.
•Updated description for USB0 (Event 9) and USB1(Event 10) peripheral in Table 75 “Event router
inputs”; USB0: Wake-up request signal. Not active in power-down and deep power-down mode. Use
for wake-up from sleep and deep-sleep mode; USB1: USB1 AHB_NEED_CLK signal. Not active in
power-down and deep power-down mode. Use for wake up from sleep and deep-sleep mode.
•Updated Table 170 “LPC1850/30/20/10 Pin description (flashless parts)”: Fixed PD_3 to be "SCT
Output 6"; was SCT Output 7.

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2.7 20151104 LPC18xx user manual
Modifications: •Added S parts to Table 1 “Ordering information”, Table 2 “Ordering options (flashless parts)”, Table 3
“Ordering information (parts with on-chip flash)”, and Table 4 “Ordering options (parts with on-chip
flash)”.
•Added 16 kB EEPROM in Section 1.2 “Features”.
•Added the line to the remark in Section 10.4.10 “USB0 frame length adjust register” and
Section 10.4.11 “USB1 frame length adjust register”: This register should be read before the
initialization of USB0 and USB1.
•Fixed typographical error in Section 6.2 “Features”: Cipher-Block chaining.
•Added the paragraph: The Motor control PWM is not available on LPC1810FET100,
LPC1820FET100, and LPC1830FET100 parts to Section 31.1 “How to read this chapter”.
•Added 0x10 to all the offsets for exception numbers 53 and above ending with 0x110 for the QEI
vector. See Table 72 “Connection of interrupt sources to the NVIC”.
•Added device and hex coding information for S parts to Table 40 “LPC18xx part identification
numbers”.
•Fixed CBC to read Cipher Block Chaining instead of Cipher Book Chaining in Section 8.2 “Features”.
•Updated Section 28.6 “Register description”text. Was REGMODEn = 1: Registers operate as match
and reload registers. REGMODEn = 0: Registers operate as capture and capture control registers. 0
and 1 reversed to read, REGMODEn = 0: Registers operate as match and reload registers.
REGMODEn = 1: Registers operate as capture and capture control registers.
•Updated Section 29.3 “Register description” text. Was REGMODEn = 1: Registers operate as match
and reload registers. REGMODEn = 0: Registers operate as capture and capture control registers. 0
and 1 reversed to read, REGMODEn = 0: Registers operate as match and reload registers.
REGMODEn = 1: Registers operate as capture and capture control registers.
•Fixed references to LPC18xx in List item 5 on page 97 and Section 7.3.4 “CMAC”: For LPC18xx the
chosen CMAC parameters are: encryption key K = User Key (AES key1, same as used for
decryption) and tag length l = 64.
•Updated Table 18 “Boot image header description”: Reserved bits: 15:8 instead of 15:14.
•Updated Table 69 “Boot image header description”: AES_CONTROL bits: 15:8. added a remark
before the table.
•In Table 103 “Power-down modes register (PD0_SLEEP0_MODE - address 0x4004 201C) bit
description” “Power-down modes register (PD0_SLEEP0_MODE - address 0x4004 201C) bit
description”, the value of Deep power down mode is changed to 0x0033 FF7F.
•In Table 14 “OTP function allocation”, updated otp_ProgUSBID: otp_ProgUSBID will program prod_id
and vend_id in word 1 of bank 3: 3; word 1.
•Re-named Part ID register to CHIP ID register: Table 88 “Register overview: Configuration registers
(base address 0x4004 3000)” and Table 97 “Chip ID register (CHIPID, address 0x4004 3200) bit
description”. Added CHIP ID for Flash devices Rev A: CHIP ID is 0x7906 002B to Table 97.
•Added SBUSCFG register. See Table 384 “System bus interface configuration register (SBUSCFG -
address 0x4000 6090) bit description”. Added a remark in Section 23.6.10 “Burst Size register
(BURSTSIZE)”.
•Updated Figure 21 “IAP parameter passing”.
•Changed the IAP command array size to 5: See Section 5.8 “IAP commands”.
Define data structure or pointers to pass the IAP command table and result table to the IAP function:
unsigned long command[5]; unsigned long result[5];
Revision history …continued
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Modifications: •Updated Table 48 “IAP Copy RAM to Flash command”.
•Added a bullet to Section 5.2 “Basic configuration”. If the application uses the IAP interface, it must
reserve the SRAM space used by IAP as outlined in Section 5.4.5.8 “RAM used by IAP command
handler”.
•Updated Section 5.4.5.8 “RAM used by IAP command handler”. Added text: 16 B of RAM from
0x10089FF0 to 0x10089FFF. Applications making use of IAP calls must reserve this RAM block.
•Updated Section 5.4.5.7 “RAM used by ISP”; removed command handler from the title and updated
text.
•Updated Figure 27 “Boot flow for encrypted images (flashless parts)”.
•Updated Figure 32 “AES endianness”.
2.6 20150210 LPC18xx user manual
Modifications: •Table 700 “SCT configuration example” corrected.
•Number of EMC_CS and EMC_DYCS pins corrected for the LQFP208 pin package in Table 343
“EMC pinout for different packages”.
•Section 38.7.5.1 “USART clock in synchronous mode” added.
•Bit 12 changed to 1 for EMC address mapping 256 Mb, 512 Mb, 1 Gb. See Table 367 “Address
mapping”.
•Bit description of bits TSEG1 and TSEG2 corrected in Table 976 “CAN bit timing register (BT,
address 0x400E 200C (C_CAN0) and 0x400A 400C (C_CAN1)) bit description” and Figure 172 “Bit
timing” updated for clarification.
•Parts MX1635E, W25Q16DV, W25Q32FV added to Table 19 “QSPI devices supported by the boot
code and the SPIFI API”.
•Use of IAP calls clarified: IAP commands are not supported for flash-less parts. See Section 5.8 “IAP
commands”.
•For flashless parts only: Unique part ID is stored in OTP bank 0, word 2 and readable at memory
location 0x4004 5008. See Section 3.1 and Table 9 “OTP memory description (OTP base address
0x4004 5000)”.
•For secure parts only: Chapter 7 “LPC18xx Boot ROM for secure parts” added.
•For secure parts only: AES DMA request lines added. See Table 92, Table 252, and Table 272.
•Boot ROM chapter split into two chapters for secure and non-secure parts. See Chapter 4 “LPC18xx
Boot ROM” and Chapter 7 “LPC18xx Boot ROM for secure parts”.
•Description of USB0_DM and USB1_DM pins corrected: These pins do not contain an internal
pull-up. See Table 381 and Table 443.
•Section 4.1.1 “Determine the boot code version” added.
Revision history …continued
Rev Date Description

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Modifications: •Signal polarity of signals EMC_CKEOUT and EMC_DQMOUT corrected in Table 346 “EMC pin
description”. Both signals are active HIGH.
•Corrected remark for bits MODE3, RFCLK, and FBCLK in Table 335 “SPIFI control register (CTRL,
address 0x4000 3000) bit description”: MODE3, RFCLK, and FBCLK should not all be 1, because in
this case there is no final falling edge on SCK on which to sample the last data bit of the frame.
•Bit 4 changed from Reserved to SEE (System Error Enable) in register USBINTR_D and
USBINTR_H . See Table 395 and Table 396.
•Bit 4 changed from Reserved to SEI in register USBSTS_D and USBSTS_H. See Table 393 and
Table 394.
•Bit 4 changed from Reserved to SEE (System Error Enable) register USBINTR_D and USBINTR_H.
See Table 456 and Table 457.
•Bit 4 changed from Reserved to SEI register USBSTS_D and USBSTS_H. See Table 454 and
Table 455.
•Added Section 23.11, System error.
•Removed BUS_RST from Table 153.
•Added a remark on how to read the FLADJ register in Section 10.4.10 and Section 10.4.11.
•Added text: The USART3 boot mode is not supported for LPC18Sxx parts. See Section 4.1, Table 15,
Table 16, and Section 7.1
Revision history …continued
Rev Date Description

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User manual Rev. 3.0 — 26 July 2017 6 of 1284
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2.5 20140127 LPC18xx user manual
Modifications: •C_CAN CLKDIV register description corrected and clock divider values updated. See Table 1011.
•Priorities of the EMC SDRAM ports added. See Section 21.4.
•Table 14 “OTP function allocation” updated.
•Condition for the CAN PCLK added: PCLK < 50 MHz. See Section 42.2.
•VBUS connection requirement for self-powered USB0 added to Section 22.5.1 “Requirements for
connecting the USB0_VBUS/USB1_VBUS signal”.
•Section 35.7.1 “Register read procedure” updated for reading the RTC registers after wake-up.
•RTC_ALARM pin description corrected (Table 802 “RTC pin description”). This pin is not a 1.8 V pin.
•Read-only status bits for EMC clock divider register configuration register added. See Table 146
“CCU1 branch clock configuration register (CLK_M3_EMCDIV_CFG, addresses 0x4005 1478) bit
description”.
•Description of the WAKEUP bits expanded in the CCU branch clock configuration and status
registers. See Section 12.5.3 “CCU1/2 branch clock configuration registers” and Section 12.5.4
“CCU1/2 branch clock status registers”.
•Bit RUN_N added to CCU branch clock status registers. See Section 12.5.4 “CCU1/2 branch clock
status registers”.
•ARM Cortex-M3 core version added. See Section 1.2 “Features”.
•Statement added: Only write to the RTC registers when the 32 kHz oscillator is running. See
Section 35.2. Same for Alarm timer. See Section 33.2.
•MII availability clarified: Ethernet MII not available on LQFP144 and TFBGA100 parts. See
Section 25.1 “How to read this chapter”.
•Timer input and output connections clarified in Section 29.2 and Figure 35 “Connections between
GIMA and peripherals”.
•Section 42.7.5.1.1 “Calculating the C_CAN bit rate” added.
2.4 20131017 LPC18xx user manual
Modifications: •AES ROM driver function table offsets corrected. See Table 68 “Security API calls”.
•Part MX25L8006EM2L-12G, MX25L8035E, MX25L1633E, MX25L3235E, MX25L6435E,
MX25L12835F, MX25L25635Fadded to list of parts that can boot from SPIFI. See Table 19.
•Figure 11 “Boot process for parts without flash” updated.
•Reset values of EEPROM registers RWSTATE and WSTATE corrected. See Table 1032.
2.3 20130926 LPC18xx user manual
Modifications: •BASE_APLL_CLK renamed to BASE_AUDIO_CLK in Chapter 9 “LPC18xx Configuration Registers
(CREG)”, Chapter 11 “LPC18xx Clock Generation Unit (CGU)”, Chapter 12 “LPC18xx Clock Control
Unit (CCU)”, and Chapter 40 “LPC18xx I2S interface”.
•AES speed corrected. See Section 6.2.
•Bit description of register CREG5 corrected. Bits 10:0 changed to reserved. Use bits 11 for disabling
JTAG. See Section 9.4.3 “CREG5 control register”.
•Part IDs updated for all LPC1850/30/20/10 parts. See Table 39 and LPC1850/30/20/10 errata.
•Description of the RESET pin updated in Table 166 and Table 167.
Revision history …continued
Rev Date Description

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Modifications: •Description of the SDIS bit updated in for USB0 stream mode in Table 410/Table 411 and for USB1
stream mode in Table 471/Table 472.
•Updated description of access types to the USB descriptors. See Table 421 “Endpoint capabilities
and characteristics” and Table 425 “dTD token”.
•Use of EMC_CLK pins clarified for SDRAM devices. See Section 21.2.
•Pin description of pins SD_VOLT[2:0] updated in Table 274.
•Add bits 20 (BOD reset) and 21 (reset after wake-up from deep power-down) to the event router
registers. See Table 72, Table 75 to Table 83, and Section 13.5.1 “Determine the cause of a core
reset”.
•Table 183 “SD/MMC delay register (SDDELAY, address 0x4008 6D80) bit description” added.
•USB driver code listing corrected. See Section 24.5 “USB API”.
•Register RESET_EXT_STAT4 removed. See Table 152.
•SDRAM address mappings added in Table 364.
•Device MX25L6435EM2I-10G added to Table 18 “QSPI devices supported by the boot code and the
SPIFI API”.
•Table 4 “Ordering options (parts with on-chip flash)” corrected. ULPI not available on 144-pin and
100-pin packages.
•Editorial updates to Section 4.3.5 “Boot image creation” and Figure 13 “Image encryption flow”
added.
•Editorial edits to Chapter 6 “LPC18xx Security API”. Section “CMAC using AES hardware
acceleration” removed.
•Section 11.2.1 “Configuring the BASE_M3_CLK for high operating frequencies” corrected to ensure
safe operation of the clock ramping procedure.
•Figures and tables in Section 40.7.2 “I2S operating modes” corrected.
•Table 39 “LPC18xx part identification numbers” description of word1 corrected.
•Part LPC1850FBD208 removed.
•OTP memory size available for general-purpose use corrected. See Section 1.2 and Table 7.
•Details about encryption of the image header added in Section 4.3.4 “Boot image header format”.
•Figure 11 “Boot process for parts without flash” corrected. SPI(SSP) boot requires image header.
•Bit description of Table 300 “Debounce Count Register (DEBNCE, address 0x4000 4064) bit
description” updated. Host clock is the SD_CLK clock.
•Security features updates. FIPS compliancy added. See Section 6.2.
•Section 28.4.3 “SCT Example” updated.
•Figure 103 “Repetitive Interrupt Timer (RIT) block diagram” corrected.
•ISP mode added to Figure 11 “Boot process for parts without flash”.
•Chapter “LPC18xx API General error codes” added.
2.2 20130125 LPC18xx user manual.
Modifications: •GPIO group interrupt wake-up from power-down modes corrected in Section 16.3.2. Only wake-up
from sleep mode supported.
•Section 4.3.5.4.1 “Supported QSPI devices” moved to Chapter 4 “LPC18xx Boot ROM”.
•SPIFI register map and register descriptions added in Chapter 19 “LPC18xx SPI Flash Interface
(SPIFI)”.
•Bit description of Table 924 “CAN error counter (EC, address 0x400E 2008 (C_CAN0) and 0x400A
4008 (C_CAN1)) bit description” corrected.
•Bit clock calculation and bit description corrected in Section 41.6.1.4 “CAN bit timing register”.
Revision history …continued
Rev Date Description

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2.1 20121203 LPC18xx user manual.
•Description of ADC pins on digital/analog input pins changed. Each input to the ADC is connected to
ADC0 and ADC1. See Table 117, Table 118, Table 959, and Section 14.1.
•Description of extra status bits added to Table 498 “DMA Status register (DMA_STAT, address
0x4001 1014) bit description”.
•Use of lower SPIFI memory clarified. See Table 280 “SPIFI flash memory map”.
•Description of DAC DMA_ENA bit clarified in Table 973 “D/A Control register (CTRL - address
0x400E 1004) bit description”.
•Pseudo-code for PLL registers updated by code snippets from LPC18xx sample code in Chapter 10.
•Reset delay clock cycles explained in Section 12.4.1 “RGU reset control register”.
•Section 19.6 “Supported QSPI devices” updated.
•Part S25FL129P0XNFI01 added to the list of devices supported by the SPIFI boot ROM driver.
2 20121012 LPC18xx user manual.
Modifications: •Statement about the connection between sampling pin P2_7 and the watchdog timer overflow bit is
incorrect and was removed in Section 44.4.1 “Sampling of pin P2_7” and Figure 164.
•IRC accuracy corrected for flash-based parts in Section 1.2.
•Description of the I2C mask registers clarified in Section 40.7.10.
•Description of the I2C slave address updated in Section 40.7.8.
•Flash-based parts LPC183x, LPC182x, LPC181x added.
•SCT alias register locations corrected in Table 578.
•SCT with dither engine added for flash-based parts. See Chapter 27 “LPC18xx State Configurable
Timer (SCT) with dither engine”.
•UART1 TER register location and bit description corrected. See Section 37.6.17.
•Section 24.6.2 “MAC Frame filter register” updated to include hash filter option.
•Section 24.7.1 “Hash filter” with examples added.
•Polarity of the DMACSYNC bit in the GPDMA SYNC register corrected (see Table 215).
•OTP API function table corrected. Location 0x1C is reserved. See Table 11.
•SPIFI data rate and maximum clock corrected to SPIFI_CLK = 104 MHz and 52 MB/s.
•The following changes were made on the TFBGA180 pinout in Table 117:
–P1_13 moved from ball D6 to L8.
–P7_5 moved from ball C7 to A7.
–PF_4 moved from ball L8 to D6.
–RESET moved from ball B7 to C7.
–RTCX2 moved from ball A7 to B7.
–Ball G10 changed from VSS to VDDIO.
•EMC Configuration register, bit 8 changed to reserved. See “EMC Configuration register (CONFIG -
address 0x4000 5008) bit description”.
Revision history …continued
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Modifications: •DMA mux control register bit descriptions corrected. See Table 39.
•ETM time stamping feature not implemented. See Chapter 46 “LPC18xx JTAG, Serial Wire Debug
(SWD), and trace functions”.
•Bit 0 in the RGU RESET_STATUS0 (Table 105) register changed to reserved. Section 12.5.1
“Determine the cause of a core reset” added.
•Micron part N25Q256 removed from the list of devices supported by the SPIFI boot ROM driver. See
Table 282 “Supported QSPI devices”.
•Section 20.6.5 “Dynamic Memory Refresh Timer register” register description updated.
•Description of the Motor control PWM INVDC bit updated in Table 664 “MCPWM Control read
address (CON - 0x400A 0000) bit description”.
•Description of the Alarm timer PRESETVAL bit updated in Table 729 “Preset value register (PRESET
- 0x4004 0004) bit description”.
1.6 20120903 LPC18xx user manual.
Modifications: •CLKMODE3 feature removed from SCT. Bit value CLKMODE = 0x3 changed to reserved in
Table 577 “SCT configuration register (CONFIG - address 0x4000 0000) bit description”.
•SSP0 boot pin functions corrected in Table 12 and Table 13. Pin P3_3 = SSP0_SCK, pin P3_6 =
SSP0_SSEL, pin P3_7 = SSP0_MISO, pin P3_8 = SSP0_MOSI.
•Details for GIMA clock synchronization added in Section 15.3.2.
•RESET_EXT_STATUS0 register removed in Chapter 12.
•Reset value of BASE_SAFE_CLK register changed to R (read-only) in Table 74.
•Reset delay values corrected in Figure 30 “RGU Reset structure”.
•POR reset value of the event router STATUS register corrected. See Table 24 and Table 30.
•USB boot mode updated: 12 MHz external crystal required. See Section 4.3.5.5.
•Reset priorities for POR and CORE_RST updated in Chapter 12 “LPC18xx Reset Generation Unit
(RGU)”.
•Reset values updated in Table 102 “Register overview: RGU (base address: 0x4005 3000)”.
•IAP invoke call entry pointer clarified in Section 43.8 “IAP commands”.
•EMC memory data and control lines clarified for the LQFP208 package in Table 283.
•Figure 10 updated to include boot process for AES capable parts.
•Editorial updates.
1.5 20120710 LPC18xx user manual.
Modifications: •Description of USB CDC device class updated in Table 449 “USBD_CDC_API class structure” and
Table 450 “USBD_CDC_INIT_PARAM class structure”.
•AES only available for LPC18Sxx parts.
•Table 14 “Boot image header use” added.
•Section 21.11 “USB power optimization” updated.
•Section 22.7.1 “Susp_CTRL module for USB1” added for USB1.
•Bank, Row, Column SDRAM addressing added in Table 307.
Revision history …continued
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User manual Rev. 3.0 — 26 July 2017 10 of 1284
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1.4 20120607 LPC18xx user manual.
Modifications: •Description of CCU auto mode updated (see Section 11.5.3).
•Parameter tbupdated in Table 16.
•Examples updated for ISP “Copy RAM to flash” and ISP “Go” commands in Table 948 and Table 952.
•Syncflash removed from Chapter 20.
•Parts LPC1837/33 added.
•Maximum power consumption in the USB Suspended state corrected according to USB 2.0 ECN
specification (Section 21.11.1).
•Programming procedure for the SDRAM mode register added in Section 20.7.5.
•Clock ramp-up procedures for core clock added in Section 10.2.1.
•Parameters for ISP/IAP command “Copy RAM to flash” updated (Table 951 and Table 964).
•Flash accelerator register waitstate values added (see Table 40 and Table 41).
•Description of ISP/IAP read part id command updated (see Table 955 and Table 967).
•Description of the event router outputs updated (see Section 7.3).
•LQFP100 package removed.
•Part IDs corrected in Table 956; also see Errata note ES_LPC18X0_A.
1.3 20120502 LPC18xx user manual.
Modifications: •Part IDs corrected in Table 955.
•OTP memory bank 0 changed to reserved.
•Support for AES encryption added (see Table 16; parts LPC18Sxx only).
•Hardware IP checksum feature removed from ethernet block.
•USB frame length adjust register added (see Table 44 and Table 45); for parts with on-chip flash
only).
•Flash accelerator control registers added (see Table 39 and Table 40).
•Support for SAMPLE pin added to the CREG0 register (Table 35).
•Read option removed from EEPROM CMD register (Table 985).
•Add definition of page size in Section 43.5.
•Corrected SRAM address for ISP use in Section 43.4.5.7.
•Update description of bit 0 in the USBSTS_D and bit 5:0 in ENDPTCOMPLETE registers of USB0/1.
•Update procedure Section 21.10.8.1.2 “Setup packet handling using the trip wire mechanism”.
•TFBGA package pinout added in Chapter 13.
•Timer/SCT cross-connections updated for CTOUT_1, CTOUT_4, CTOUT_5, CTOUT_9, CTOUT_10,
CTOUT_12, and CTOUT_13 in Chapter 13, Table 574, and Section 27.5.
•Polarity of bit OUTSEL in the SCT EVCTRL register swapped (see Table 600).
•Description of STOP_l/H bits in the SCT CTRL register updated (see Table 577).
•Description of BOD wake-up corrected in Table 21.
Revision history …continued
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User manual Rev. 3.0 — 26 July 2017 11 of 1284
Contact information
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1.2 20120329 LPC18xx user manual.
Modifications: •Chapter 18 updated.
•EEPROM memory location corrected in Figure 5.
•EEPROM memory access explained (Section 2.3.4).
•SDRAM low-power mode removed in Chapter 20.
•Motorcontrol PWM hardware noise filtering removed.
•Description of the QEI register VEL corrected.
•ISP commands for flash parts updated in Chapter 43.
•Chapter 38 updated.
•Appendix describing parts LPC18xx Rev ‘-’ removed.
•References to parts LPC18xx Rev ‘-’ removed throughout the document.
•Remove condition RTC_ALARM = LOW on reset for entering debug mode.
•Ethernet chapter updated: PPS and auxiliary timestamp features removed.
•Chapter 34 added.
•Reset value of bit ETB in the ETBCFG register changed to one (see Table 41).
•Connection of USB0_VBUS/USB1_VBUS signals added (Section 21.5.1).
•Description of ADC GDR register updated (Section 41.6.2).
•UART1 FIFOLVL register removed.
•Pin reset states updated in Table 113 and Table 114.
•SCT register map updated in Table 570.
•Changed maximum clock frequency for SWD and ETB access to 120 MHz in Chapter 45.
•Reduced and normal power modes removed in Chapter 9.
1.1 20111212 Preliminary LPC18xx user manual.
Modifications: •SPIFI boot pins added to Table 12 and Table 13.
•Description of SPIFI boot mode added (Section 4.3.5.4).
•Chapter 19 added.
•PMUCON register removed in Chapter 8.
•Ethernet time stamp registers added (see Table 455).
•Reset value corrected for WWDT and CREG resets in Table 100.
•Maximum operating frequency corrected.
•Editorial updates.
•Use of SPIFI memory areas explained in Table 275.
1 20111202 Preliminary LPC18xx user manual.
Revision history …continued
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User manual Rev. 3.0 — 26 July 2017 12 of 1284
1.1 Introduction
The LPC18xx are ARM Cortex-M3 based microcontrollers for embedded applications.
The ARM Cortex-M3 is a next generation core that offers system enhancements such as
low power consumption, enhanced debug features, and a high level of support block
integration.
The LPC18xx operate at CPU frequencies of up to 180 MHz. The ARM Cortex-M3 CPU
incorporates a 3-stage pipeline and uses a Harvard architecture with separate local
instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3
CPU also includes an internal prefetch unit that supports speculative branching.
The LPC18xx include up to 200 kB of on-chip SRAM data memory (flashless parts) or up
to 136 kB of on-chip SRAM and up to 1 MB of flash (parts with on-chip flash), 16 kB
EEPROM, a quad SPI Flash Interface (SPIFI), a State Configurable Timer (SCT)
subsystem, two High-speed USB controllers, Ethernet, LCD, an external memory
controller, and multiple digital and analog peripherals.
Remark: This user manual describes parts LPC1850/30/20/10 (flashless parts) and the
flash-based LPC18xx parts.
See Section 49.2 “References” for additional documentation.
1.2 Features
•Processor core
–ARM Cortex-M3 processor (core version r2p1), running at frequencies of up to
180 MHz.
–ARM Cortex-M3 built-in Memory Protection Unit (MPU) supporting eight regions.
–ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
–Non-maskable Interrupt (NMI) input.
–JTAG and Serial Wire Debug, serial trace, eight breakpoints, and four watch points.
–ETM and ETB support.
–System tick timer.
•On-chip memory (flashless parts LPC1850/30/20/10)
–Up to 200 kB SRAM total for code and data use.
–Two 32 kB SRAM blocks with separate bus access. Both SRAM blocks can be
powered down individually.
–64 kB ROM containing boot code and on-chip software drivers.
–64 bit+ 256 bit One-Time Programmable (OTP) memory for general-purpose
customer use. For secure parts, 256 bit OTP memory is used for key storage.
•On-chip memory (parts with on-chip flash)
–Up to 1 MB total dual bank flash memory with flash accelerator.
UM10430
Chapter 1: LPC18xx Introductory information
Rev. 3.0 — 26 July 2017 User manual

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Chapter 1: LPC18xx Introductory information
–In-System Programming (ISP) and In-Application Programming (IAP) via on-chip
boot loader software.
–Up to 136 kB SRAM for code and data use.
–Two 32 kB SRAM blocks with separate bus access. Both SRAM blocks can be
powered down individually.
–64 kB ROM containing boot code and on-chip software drivers.
–32 bit One-Time Programmable (OTP) memory for general-purpose customer use.
–16 kB EEPROM.
•Clock generation unit
–Crystal oscillator with an operating range of 1 MHz to 25 MHz.
–12 MHz internal RC oscillator trimmed to 1 % (flashless parts) or 2 % (flash-based
parts) accuracy.
–Ultra-low power RTC crystal oscillator.
–Three PLLs allow CPU operation up to the maximum CPU rate without the need for
a high-frequency crystal. The second PLL is dedicated to the High-speed USB, the
third PLL can be used as audio PLL.
–Clock output.
•Serial interfaces:
–Quad SPI Flash Interface (SPIFI) with 1-, 2-, or 4-bit data at rates up to 52 MB per
second.
–10/100T Ethernet MAC with RMII and MII interfaces and DMA support for high
throughput at low CPU load. Support for IEEE 1588 time stamping/advanced time
stamping (IEEE 1588-2008 v2).
–One High-speed USB 2.0 Host/Device/OTG interface with DMA support and
on-chip PHY.
–One High-speed USB 2.0 Host/Device interface with DMA support, on-chip
full-speed PHY and ULPI interface to external high-speed PHY.
–USB interface electrical test software included in ROM USB stack.
–Four 550 UARTs with DMA support: one UART with full modem interface; one
UART with IrDA interface; three USARTs support synchronous mode and a smart
card interface conforming to ISO7816 specification.
–Two C_CAN 2.0B controllers with one channel each.
–Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMA
support.
–One Fast-mode Plus I2C-bus interface with monitor mode and with open-drain I/O
pins conforming to the full I2C-bus specification. Supports data rates of up to
1 Mbit/s.
–One standard I2C-bus interface with monitor mode and standard I/O pins.
–Two I2S interfaces with DMA support, each with one input and one output.
•Digital peripherals:
–External Memory Controller (EMC) supporting external SRAM, ROM, NOR flash,
and SDRAM devices.

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Chapter 1: LPC18xx Introductory information
–LCD controller with DMA support and a programmable display resolution of up to
1024H 768V. Supports monochrome and color STN panels and TFT color
panels; supports 1/2/4/8 bpp CLUT and 16/24-bit direct pixel mapping.
–SD/MMC card interface.
–Eight-channel General-Purpose DMA (GPDMA) controller can access all
memories on the AHB and all DMA-capable AHB slaves.
–Up to 164 General-Purpose Input/Output (GPIO) pins with configurable
pull-up/pull-down resistors and open-drain modes.
–GPIO registers are located on the AHB for fast access. GPIO ports have DMA
support.
–State Configurable Timer (SCT) subsystem on AHB.
–Four general-purpose timer/counters with capture and match capabilities.
–One motor control PWM for three-phase motor control.
–One Quadrature Encoder Interface (QEI).
–Repetitive Interrupt timer (RI timer).
–Windowed watchdog timer.
–Ultra-low power Real-Time Clock (RTC) on separate power domain with 256 bytes
of battery powered backup registers.
–Event recorder with 3 inputs to record event identification and event time; can be
battery powered. The event recorder is available on parts with on-chip flash only.
–Alarm timer; can be battery powered.
•Digital peripherals available on flash-based parts LPC18xx only:
–Event monitor in the RTC power domain.
•Analog peripherals:
–One 10-bit DAC with DMA support and a data conversion rate of 400 kSamples/s.
–Two 10-bit ADCs with DMA support and a data conversion rate of 400 kSamples/s.
•Security (LPC18Sxx parts only):
–Hardware-based AES security engine programmable through an on-chip API.
–Two 128 bit secure OTP memories for AES key storage and customer use.
–Random number generator (RNG) accessible through AES API.
•Unique ID for each device.
•Power:
–Single 3.3 V (2.2 V to 3.6 V) power supply with on-chip internal voltage regulator
for the core supply and the RTC power domain.
–RTC power domain can be powered separately by a 3 V battery supply.
–Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep
power-down.
–Processor wake-up from Sleep mode via wake-up interrupts from various
peripherals.

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Chapter 1: LPC18xx Introductory information
–Wake-up from Deep-sleep, Power-down, and Deep power-down modes via
external interrupts and interrupts generated by battery powered blocks in the RTC
power domain.
–Brownout detect with four separate thresholds for interrupt and forced reset.
–Power-On Reset (POR).
•Available as 144-pin and 208-pin LQFP packages and as 100-pin, 180-pin, and
256-pin LBGA packages.
1.3 Ordering information (flashless parts LPC1850/30/20/10)
Table 1. Ordering information
Type number Package
Name Description Version
LPC1850FET256 LBGA256 Plastic low profile ball grid array package; 256 balls; body 17 17 1 mm SOT740-2
LPC1850FET180 TFBGA180 Thin fine-pitch ball grid array package; 180 balls SOT570-3
LPC18S50FET256 LBGA256 Plastic low profile ball grid array package; 256 balls; body 17 17 1 mm SOT740-2
LPC18S50FET180 TFBGA180 Thin fine-pitch ball grid array package; 180 balls SOT570-3
LPC1830FET256 LBGA256 Plastic low profile ball grid array package; 256 balls; body 17 17 1 mm SOT740-2
LPC1830FET180 TFBGA180 Thin fine-pitch ball grid array package; 180 balls SOT570-3
LPC1830FET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9 9 0.7 mm SOT926-1
LPC1830FBD144 LQFP144 Plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm SOT486-1
LPC18S30FET256 LBGA256 Plastic low profile ball grid array package; 256 balls; body 17 17 1 mm SOT740-2
LPC18S30FET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9 9 0.7 mm SOT926-1
LPC18S30FBD144 LQFP144 Plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm SOT486-1
LPC1820FET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9 9 0.7 mm SOT926-1
LPC1820FBD144 LQFP144 Plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm SOT486-1
LPC1810FET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9 9 0.7 mm SOT926-1
LPC1810FBD144 LQFP144 Plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm SOT486-1
LPC18S10FET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9 9 0.7 mm SOT926-1
LPC18S10FBD144 LQFP144 Plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm SOT486-1
Table 2. Ordering options (flashless parts)
Type number Total
SRAM LCD Ethernet USB0 (Host,
Device,
OTG)
USB1
(Host,
Device)/
ULPI
interface
ADC
channels PWM QEI GPIO Package
LPC1850FET256 200 kB yes yes yes yes/yes 8 yes yes 164 LBGA256
LPC1850FET180 200 kB yes yes yes yes/yes 8 yes yes 118 TFBGA180
LPC18S50FET256 200 kB yes yes yes yes/yes 8 yes yes 164 LBGA256
LPC18S50FET180 200 kB yes yes yes yes/yes 8 yes yes 118 TFBGA180
LPC1830FET256 200 kB no yes yes yes/yes 8 yes yes 164 LBGA256
LPC1830FET180 200 kB no yes yes yes/yes 8 yes yes 118 TFBGA180
LPC1830FET100 200 kB no yes yes yes/no 4 no no 49 TFBGA100

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Chapter 1: LPC18xx Introductory information
1.4 Ordering information (parts with on-chip flash)
LPC1830FBD144 200 kB no yes yes yes/no 8 yes no 83 LQFP144
LPC18S30FET256 200 kB no yes yes yes/yes 8 yes yes 164 LBGA256
LPC18S30FET100 200 kB no yes yes yes/no 4 no no 49 TFBGA100
LPC18S30FBD144 200 kB no yes yes yes/no 8 yes no 83 LQFP144
LPC1820FET100 168 kB no no yes no 4 no no 49 TFBGA100
LPC1820FBD144 168 kB no no yes no 8 yes no 83 LQFP144
LPC1810FET100 136 kB no no no no 4 no no 49 TFBGA100
LPC1810FBD144 136 kB no no no no 8 yes no 83 LQFP144
LPC18S10FET100 136 kB no no no no 4 no no 49 TFBGA100
LPC18S10FBD144 136 kB no no no no 8 yes no 83 LQFP144
Table 2. Ordering options (flashless parts)
Type number Total
SRAM LCD Ethernet USB0 (Host,
Device,
OTG)
USB1
(Host,
Device)/
ULPI
interface
ADC
channels PWM QEI GPIO Package
Table 3. Ordering information (parts with on-chip flash)
Type number Package
Name Description Version
LPC1857FET256 LBGA256 Plastic low profile ball grid array package; 256 balls; body 17 17 1 mm SOT740-2
LPC1857JET256 LBGA256 Plastic low profile ball grid array package; 256 balls; body 17 17 1 mm SOT740-2
LPC1857JBD208 LQFP208 Plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm SOT459-1
LPC18S57JET256 LBGA256 Plastic low profile ball grid array package; 256 balls; body 17 17 1 mm SOT740-2
LPC18S57JBD208 LQFP208 Plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm SOT459-1
LPC1853FET256 LBGA256 Plastic low profile ball grid array package; 256 balls; body 17 17 1 mm SOT740-2
LPC1853JET256 LBGA256 Plastic low profile ball grid array package; 256 balls; body 17 17 1 mm SOT740-2
LPC1853JBD208 LQFP208 Plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm SOT459-1
LPC1837FET256 LBGA256 Plastic low profile ball grid array package; 256 balls; body 17 17 1 mm SOT740-2
LPC1837JET256 LBGA256 Plastic low profile ball grid array package; 256 balls; body 17 17 1 mm SOT740-2
LPC1837JBD144 LQFP144 Plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm SOT486-1
LPC1837JET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9 9 0.7 mm SOT926-1
LPC18S37JBD144 LQFP144 Plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm SOT486-1
LPC18S37JET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9 9 0.7 mm SOT926-1
LPC1833FET256 LBGA256 Plastic low profile ball grid array package; 256 balls; body 17 17 1 mm SOT740-2
LPC1833JET256 LBGA256 Plastic low profile ball grid array package; 256 balls; body 17 17 1 mm SOT740-2
LPC1833JBD144 LQFP144 Plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm SOT486-1
LPC1833JET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9 9 0.7 mm SOT926-1
LPC1827JBD144 LQFP144 Plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm SOT486-1
LPC1827JET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9 9 0.7 mm SOT926-1
LPC1825JBD144 LQFP144 Plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm SOT486-1
LPC1825JET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9 9 0.7 mm SOT926-1

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NXP Semiconductors UM10430
Chapter 1: LPC18xx Introductory information
LPC1823JBD144 LQFP144 Plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm SOT486-1
LPC1823JET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9 9 0.7 mm SOT926-1
LPC1822JBD144 LQFP144 Plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm SOT486-1
LPC1822JET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9 9 0.7 mm SOT926-1
LPC1817JBD144 LQFP144 Plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm SOT486-1
LPC1817JET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9 9 0.7 mm SOT926-1
LPC1815JBD144 LQFP144 Plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm SOT486-1
LPC1815JET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9 9 0.7 mm SOT926-1
LPC1813JBD144 LQFP144 Plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm SOT486-1
LPC1813JET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9 9 0.7 mm SOT926-1
LPC1812JBD144 LQFP144 Plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm SOT486-1
LPC1812JET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9 9 0.7 mm SOT926-1
Table 3. Ordering information (parts with on-chip flash)
Type number Package
Name Description Version
Table 4. Ordering options (parts with on-chip flash)
Type number Flash total Flash bank A Flash bank B Total SRAM LCD Ethernet USB0 (Host, Device, OTG) USB1 (Host, Device)/ ULPI interface PWM QEI ADC channels Temperature range[1] GPIO
LPC1857FET256 1 MB 512 kB 512 kB 136 kB yes yes yes yes/yes yes yes 8 F 164
LPC1857JET256 1 MB 512 kB 512 kB 136 kB yes yes yes yes/yes yes yes 8 J 164
LPC1857JBD208 1 MB 512 kB 512 kB 136 kB yes yes yes yes/yes yes yes 8 J 142
LPC18S57JET256 1 MB 512 kB 512 kB 136 kB yes yes yes yes/yes yes yes 8 J 164
LPC18S57JBD208 1 MB 512 kB 512 kB 136 kB yes yes yes yes/yes yes yes 8 J 142
LPC1853FET256 512 kB 256 kB 256 kB 136 kB yes yes yes yes/yes yes yes 8 F 164
LPC1853JET256 512 kB 256 kB 256 kB 136 kB yes yes yes yes/yes yes yes 8 J 164
LPC1853JBD208 512 kB 256 kB 256 kB 136 kB yes yes yes yes/yes yes yes 8 J 142
LPC1837FET256 1 MB 512 kB 512 kB 136 kB no yes yes yes/yes yes yes 8 F 164
LPC1837JET256 1 MB 512 kB 512 kB 136 kB no yes yes yes/yes yes yes 8 J 164
LPC1837JBD144 1 MB 512 kB 512 kB 136 kB no yes yes yes/no yes no 8 J 83
LPC1837JET100 1 MB 512 kB 512 kB 136 kB no yes yes yes/no no no 4 J 49
LPC18S37JBD144 1 MB 512 kB 512 kB 136 kB no yes yes yes/no yes no 8 J 83
LPC18S37JET100 1 MB 512 kB 512 kB 136 kB no yes yes yes/no no no 4 J 49
LPC1833FET256 512 kB 256 kB 256 kB 136 kB no yes yes yes/yes yes yes 8 F 164
LPC1833JET256 512 kB 256 kB 256 kB 136 kB no yes yes yes/yes yes yes 8 J 164
LPC1833JBD144 512 kB 256 kB 256 kB 136 kB no yes yes yes/no yes no 8 J 83
LPC1833JET100 512 kB 256 kB 256 kB 136 kB no yes yes yes/no no no 4 J 49

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Chapter 1: LPC18xx Introductory information
[1] J = - 40 °C to +105 °C; F = - 40 °C to +85 °C.
LPC1827JBD144 1 MB 512 kB 512 kB 136 kB no no yes no/no yes no 8 J 83
LPC1827JET100 1 MB 512 kB 512 kB 136 kB no no yes no/no no no 4 J 49
LPC1825JBD144 768 kB 384 kB 384 kB 136 kB no no yes no/no yes no 8 J 83
LPC1825JET100 768 kB 384 kB 384 kB 136 kB no no yes no/no no no 4 J 49
LPC1823JBD144 512 kB 256 kB 256 kB 104 kB no no yes no/no yes no 8 J 83
LPC1823JET100 512 kB 256 kB 256 kB 104 kB no no yes no/no no no 4 J 49
LPC1822JBD144 512 kB 512 kB 0 kB 104 kB no no yes no/no yes no 8 J 83
LPC1822JET100 512 kB 512 kB 0 kB 104 kB no no yes no/no no no 4 J 49
LPC1817JBD144 1 MB 512 kB 512 kB 136 kB no no no no/no yes no 8 J 83
LPC1817JET100 1 MB 512 kB 512 kB 136 kB no no no no/no no no 4 J 49
LPC1815JBD144 768 kB 384 kB 384 kB 136 kB no no no no/no yes no 8 J 83
LPC1815JET100 768 kB 384 kB 384 kB 136 kB no no no no/no no no 4 J 49
LPC1813JBD144 512 kB 256 kB 256 kB 104 kB no no no no/no yes no 8 J 83
LPC1813JET100 512 kB 256 kB 256 kB 104 kB no no no no/no no no 4 J 49
LPC1812JBD144 512 kB 512 kB 0 kB 104 kB no no no no/no yes no 8 J 83
LPC1812JET100 512 kB 512 kB 0 kB 104 kB no no no no/no no no 4 J 49
Table 4. Ordering options (parts with on-chip flash)
Type number Flash total Flash bank A Flash bank B Total SRAM LCD Ethernet USB0 (Host, Device, OTG) USB1 (Host, Device)/ ULPI interface PWM QEI ADC channels Temperature range[1] GPIO

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Chapter 1: LPC18xx Introductory information
1.5 Block diagram (flashless parts LPC1850/30/20/10)
AES available on LPC18Sxx parts only.
Fig 1. LPC18xx Block diagram (flashless parts)
ARM
CORTEX-M3
TEST/DEBUG
INTERFACE
I-code bus D-code bus system bus
SWD/TRACE PORT/JTAG
DMA
ETHERNET(1)
10/100
MAC
IEEE 1588
USB1(1)
HOST/
DEVICE
HIGH-
SPEED
USB0(1)
HOST/
DEVICE/
OTG
LCD(1) SD/
MMC
EMC
HIGH-SPEED PHY
16/32 kB AHB SRAM
16 kB +
16 kB AHB SRAM(1)
SPIFI
AES
HS GPIO
SCT
64 kB ROM
AHB MULTILAYER MATRIX
LPC1850/30/20/10
64/96 kB LOCAL SRAM
40 kB LOCAL SRAM
002aaf218
slaves
masters
WWDT
USART0
UART1
SSP0
I2C0
C_CAN1
I2S0
I2S1
MOTOR
CONTROL
PWM(1)
TIMER3
TIMER2
USART2
USART3
SSP1
RI TIMER
QEI(1)
GIMA
BRIDGE 0 BRIDGE 1 BRIDGE 2 BRIDGE 3 BRIDGE
10-bit ADC0
10-bit ADC1
C_CAN0
I2C1
10-bit DAC
BRIDGE
RGU
CCU2
CGU
CCU1
ALARM TIMER
CONFIGURATION
REGISTERS
OTP MEMORY
EVENT ROUTER
POWER MODE CONTROL
12 MHz IRC
RTC POWER DOMAIN
BACKUP REGISTERS
RTC OSC
RTC
slaves
= connected to DMA
TIMER0
TIMER1
SCU
GPIO
interrupts
GPIO GROUP0
interrupt
GPIO GROUP1
interrupt

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Chapter 1: LPC18xx Introductory information
1.6 Block diagram (parts with on-chip flash)
AES available on LPC18Sxx parts only.
(1) Not available on all parts (see Ta b l e 4 ).
Fig 2. LPC185x/3x block diagram (parts with on-chip flash)
ARM
CORTEX-M3
TEST/DEBUG
INTERFACE
I-code bus D-code bus system bus
SWD/TRACE PORT/JTAG
GPDMA
ETHERNET(1)
10/100
MAC
IEEE 1588
USB1(1)
HOST/
DEVICE
HIGH-
SPEED
USB0(1)
HOST/
DEVICE/
OTG
LCD(1) SD/
MMC
EMC
HIGH-SPEED PHY
32 kB AHB SRAM
16 kB +
16 kB AHB SRAM
SPIFI
AES
HS GPIO
SCT
64 kB ROM
AHB MULTILAYER MATRIX
LPC185x/3x
32 kB LOCAL SRAM
40 kB LOCAL SRAM
slaves
masters
WWDT
USART0
UART1
SSP0
I2C0
C_CAN1
I2S0
I2S1
MOTOR
CONTROL
PWM(1)
TIMER3
TIMER2
USART2
USART3
SSP1
RI TIMER
QEI(1)
GIMA
BRIDGE 0 BRIDGE 1 BRIDGE 2 BRIDGE 3 BRIDGE
10-bit ADC0
10-bit ADC1
C_CAN0
I2C1
10-bit DAC
BRIDGE
RGU
CCU2
CGU
CCU1
ALARM TIMER
CONFIGURATION
REGISTERS
OTP MEMORY
EVENT ROUTER
POWER MODE CONTROL
12 MHz IRC
EVENT RECORDER
RTC POWER DOMAIN
BACKUP REGISTERS
RTC OSC
RTC
slaves
= connected to DMA
TIMER0
TIMER1
SCU
GPIO PIN
INTERRUPTS
GPIO GROUP0
INTERRUPT
GPIO GROUP1
INTERRUPT
512/256 kB FLASH A(1)
512/256 kB FLASH B(1)
EEPROM