NXP Semiconductors PTN38007-EVM User manual

UM11595
PTN38007-EVM/PTN38003A-EVM evaluation board
Rev. 1.0 — 28 June 2021 User manual
Document information
Information Content
Keywords PTN38007, PTN38003A, PTN5110, USB Type-C, CC Logic, Orientation
Detection, USB3.1 Gen2, USB3.2, USB4.0, SuperSpeed, DisplayPort, Linear
Redriver
Abstract The PTN38007-EVM/PTN38003A-EVM is capable of interfacing a USB
Type-C port with various alternate mode devices. The evaluation board is
intended for use as an evaluation and customer demonstration tool, as well as
a reference design.

NXP Semiconductors UM11595
PTN38007-EVM/PTN38003A-EVM evaluation board
Rev Date Description
v.1.0 20210628 Initial version
Revision history
UM11595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.
User manual Rev. 1.0 — 28 June 2021
2 / 26

NXP Semiconductors UM11595
PTN38007-EVM/PTN38003A-EVM evaluation board
Important notice
NXP provides the enclosed product(s) under the following conditions:
This evaluation kit is intended for use of ENGINEERING DEVELOPMENT OR
EVALUATION PURPOSES ONLY. It is provided as a sample IC pre-soldered to a
printed circuit board to make it easier to access inputs, outputs, and supply terminals.
This evaluation board may be used with any development system or other source of
I/O signals by simply connecting it to the host MCU or computer board via off-the-
shelf cables. This evaluation board is not a Reference Design and is not intended to
represent a final design recommendation for any particular application. Final device in
an application will be heavily dependent on proper printed circuit board layout and heat
sinking design as well as attention to supply filtering, transient suppression, and I/O
signal quality.
The goods provided may not be complete in terms of required design, marketing, and
or manufacturing related protective considerations, including product safety measures
typically found in the end product incorporating the goods. Due to the open construction
of the product, it is the user's responsibility to take any and all appropriate precautions
with regard to electrostatic discharge. In order to minimize risks associated with the
customers applications, adequate design and operating safeguards must be provided
by the customer to minimize inherent or procedural hazards. For any safety concerns,
contact NXP sales and technical support services.
UM11595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.
User manual Rev. 1.0 — 28 June 2021
3 / 26

NXP Semiconductors UM11595
PTN38007-EVM/PTN38003A-EVM evaluation board
1 Introduction
PTN38007 and PTN38003A (PTN38007/3A) are a Type-C USB3.2/ DP1.4 combo
redriver optimized for USB3 and DisplayPort applications on either the Downstream
Facing Port (DFP) or Upstream Facing Port (UFP) by following the four high-speed
differential data flow to extend the signal reach.
This document explains in detail how to connect the PTN38007/3A-EVM evaluation
board in a system using external PD controller in a stand-alone mode, and how to
configure the on-board multiplexers for each operation mode. The document also
illustrates the LPCUSBSIO module operation and configuration with the PTN38007/3A-
EVM evaluation board.
2 Finding kit resources and information on the NXP web site
NXP Semiconductors provides online resources for this evaluation board and its
supported device(s) on http://www.nxp.com.
The information page for PTN38007-EVM evaluation board is at http://www.nxp.com/
PTN38007-EVM, and the information page for PTN38003A-EVM evaluation board is
at http://www.nxp.com/PTN38003A-EVM. The information page provides overview
information, documentation, software and tools, parametrics, ordering information and
a Getting Started tab. The Getting Started tab provides quick-reference information
applicable to using the PTN38007/3A-EVM evaluation board, including the downloadable
assets referenced in this document.
2.1 Collaborate in the NXP community
The NXP community is for sharing ideas and tips, ask and answer technical questions,
and receive input on just about any embedded design topic.
The NXP community is at http://community.nxp.com.
3 Getting ready
Working with the PTN38007/3A-EVM evaluation board requires the kit contents,
additional hardware and a Windows PC workstation with installed software.
3.1 Kit contents
•Assembled and tested evaluation board in an anti-static bag
•Quick Start Guide
3.2 Additional hardware
In addition to the kit contents, the following hardware is necessary or beneficial when
working with this kit.
•One PC/Notebook with USB-C supporting USB3.2 Gen1/2, DisplayPort, Thunderbolt
3 (PTN38007 only), or USB4 (PTN38007 only). A USB-A connector is also needed to
configure EVM via micro-USB cable
•Corresponding device for evaluation: USB3.2 Gen1/2, DisplayPort monitor, Thunderbolt
3 (PTN38007 only), or USB4 (PTN38007 only)
UM11595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.
User manual Rev. 1.0 — 28 June 2021
4 / 26

NXP Semiconductors UM11595
PTN38007-EVM/PTN38003A-EVM evaluation board
•One Type-C cable to connect between EVM and device
•One micro-USB cable to connect EVM to a PC
3.3 Windows PC workstation
This evaluation board requires a Windows PC workstation. Meeting these minimum
specifications should produce great results when working with this evaluation board.
•USB-enabled computer with Windows 7 or Windows 10
3.4 Software
Installing software is necessary to work with this evaluation board. All listed software is
available on the evaluation board's information page at http://www.nxp.com/PTN38007-
EVM or http://www.nxp.com/PTN38003A-EVM.
4 Getting to know the hardware
The stand-alone board is intended to evaluate PTN38007/3A on an existing USB Type-
C port that supports USB3.1/3.2, DisplayPort, Thunderbolt 3 and USB4. When using
the DFP board (“H2” is marked on the top side of the board), the user connects the
upstream port (J101) of this evaluation board directly to a Type-C port of a computer or
phone without any Type-C cable, and downstream port (J102) is connected to a device
or docking station through either a standard Type-C cable, or tethered cable from the
device/dock.
When using the UFP board (“D2” is marked on the top side of the board), user connects
the downstream port (J201) of this evaluation board directly to a Type-C port of a device
or a docking station without any Type-C cable, and upstream port (J202) is connected to
a computer or a phone through a standard Type-C cable.
While this board is powered through a USB micro-B cable (5 V input) on J105,
PTN38007/3A, on-board AUX/LS multiplexers, and PCA9570 GPIO expanders are
powered up, and the user can use an I2C tool such as LPCUSBSIO (built-in function in
LPCUSBSIO module) to configure PTN38007/3A into different operating modes, using
the GPIO expander’s output to configure plug orientation and multiplexer selection (tri-
stated or DisplayPort AUX Enabled). A GUI interface is also available to configure the
above configurations.
UM11595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.
User manual Rev. 1.0 — 28 June 2021
5 / 26

NXP Semiconductors UM11595
PTN38007-EVM/PTN38003A-EVM evaluation board
4.1 Block diagram
aaa-042332
T
Y
P
E
-
C
R
E
C
E
P
T
A
C
L
E
T
Y
P
E
-
C
P
L
U
G
P
T
N
3
8
0
0
7
/
P
T
N
3
8
0
0
3
A
R
X
2
T
X
2
T
X
1
R
X
1
C
C
2
R
X
2
T
X
2
T
X
1
R
X
1
C
C
1
S
B
U
2
S
B
U
1
T
o
p
U
S
B
_
D
±
B
o
t
t
o
m
U
S
B
_
D
±
C
C
2
C
C
1
D
2
±
D
1
±
S
B
U
2
S
B
U
1
V
B
U
S
V
B
U
S
C
C
2
C
C
1
D
2
±
D
1
±
S
B
U
2
S
B
U
1
V
B
U
S
A
U
X
P
A
U
X
N
S
D
A
/
M
2
S
C
L
/
M
1
A
D
D
R
L
C
T
R
L
1
R
C
T
R
L
3
R
C
T
R
L
2
R
C
T
R
L
1
L
C
T
R
L
3
L
C
T
R
L
2
L
S
R
X
L
S
T
X
P
C
A
9
5
7
0
(
G
P
I
O
)
J
1
0
4
J
1
0
5
(
µ
U
S
B
)
J
1
0
3
M
I
C
5
3
5
7
5
V
3
V
3
1
V
8
Figure 1. Block diagram
4.2 PCB photo
Figure 2. PTN38007/3A-EVM evaluation board front side
Figure 3. PTN38007/3A-EVM evaluation board back side
UM11595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.
User manual Rev. 1.0 — 28 June 2021
6 / 26

NXP Semiconductors UM11595
PTN38007-EVM/PTN38003A-EVM evaluation board
4.3 PTN38007/3A-EVM evaluation board schematics
4.3.1 Type-C connector and PTN38007/3A (DFP)
aaa-042396
H
P
1
_
C
C
1
_
1
H
P1_B
D
N
1
H
P
0
_
R
X
2
N
1
VBu
s
_P0
VBu
s
_
P
0
G
N
D
1
H
P
0
_
T
X
1
P
1
H
P
1
_
T
D
N
1
J
1
0
1
D
X
07P
0
2
4
A
J
1
R
1
5
0
0
G
N
D
1
A
1
S
S
T
X
P
1
A
2
S
S
T
X
N
1
A
3
V
B
U
S
1
A
4
C
C
1
A
5
D
P
1
A
6
D
N
1
A
7
S
B
U
1
A
8
V
B
U
S
2
A
9
S
S
R
X
N
2
A
1
0
S
S
R
X
P
2
A
1
1
G
N
D
2
A
1
2
G
N
D
3
B
1
S
S
T
X
P
2
B
2
S
S
T
X
N
2
B
3
V
B
U
S
3
B
4
C
C
2
B
5
S
B
U
2
B
8
V
B
U
S
4
B
9
S
S
R
X
N
1
B
1
0
S
S
R
X
P
1
B
1
1
G
N
D
4
B
1
2
G
1
G
1
G
2
G
2
G
4
G
4
G
5
G
5
D
P
B
6
D
N
B
7
G
3
G
3
G
6
G
6
H
P
1
_
R
X
1
P
H
P
0
_
T
X
2
N
1
H
P
1
_
B
D
N
1
H
P
1
_
T
X
2
N
H
P
1
_
R
X
2
P
H
P
1
_
T
X
1
N
H
P1_
T
D
N
1
H
P
1
_
R
X
2
N
H
P
1
_
C
C
1
_
1
H
P
0
_
T
X
1
N
1
G
N
D
1
H
P
1
_
T
D
P
1
VBu
s
_P0
H
P
1
_
S
B
U
1
_
1
H
P
0
_
R
X
1
N
1
H
P
1
_
S
B
U
2
_
1
H
P
1
_
C
C
2
_
1
H
P
1
_
C
C
2
_
1
H
P
1
_
T
X
1
P
H
P
1
_
T
D
P
1
H
P
1
_
S
B
U
2
_
1
H
P1_B
D
P
1
H
P
0
_
R
X
2
P
1
H
P
1
_
S
B
U
1
_
1
VBu
s
_
P
0
G
N
D
1
H
P
0
_
R
X
1
P
1
J
1
0
2
U
S
B
T
y
p
e
C
R
e
c
e
p
t
a
c
l
e
G
N
D
1
A
1
T
X
1
+
A
2
T
X
1
-
A
3
V
B
U
S
1
A
4
C
C
1
A
5
D
1
+
A
6
D
1
-
A
7
S
B
U
1
A
8
V
B
U
S
2
A
9
R
X
2
-
A
1
0
R
X
2
+
A
1
1
G
N
D
2
A
1
2
G
N
D
3
B
1
T
X
2
+
B
2
T
X
2
-
B
3
V
B
U
S
B
4
C
C
2
B
5
D
+
B
6
D
-
B
7
S
B
U
2
B
8
V
B
U
S
3
B
9
R
X
1
-
B
1
0
R
X
1
+
B
1
1
G
N
D
B
1
2
S
H
1
1
S
H
2
2
S
H
3
3
S
H
4
4
S
H
5
5
S
H
6
6
G
N
D
1
H
P
1
_
R
X
1
N
H
P
1
_
B
D
P
1
H
P
0
_
T
X
2
P
1
H
P
1
_
T
X
2
P
Figure 4. Schematic of Type-C connector and PTN38007/3A (DFP)
The connection between PTN38007/3A and upstream/downstream Type-C receptacles
are according to the datasheet’s pin assignment.
When PTN38007/3A is used in DFP configuration, the board is marked with ‘H2’ as
“connecting to Host side”. J101 is used as a UFP port that plugs into a computer, and
J102 is used as a DFP port that plugs into a device or dock. CC1/CC2/VBUS/SBU1/
SUB2/USB2_D± signals pass through from the plug side to receptacle side.
Figure 5. Schematic of DFP board
On the DFP board, PTN38007/3’s 7-bit I2C address is set to 0110 000 by connecting
ADDR/ORIENT pin to GND directly. This address is being used by GUI to distinguish if
a DFP or a UFP board is being used. The AUTO_ORIENTATION_EN pin is pulled up by
default, thus the AUTO ORIENTATION DETECTION function is enabled. However, this
will not impact the normal operation. GUI scripts will always override this function, and
correct orientation is always programmed.
UM11595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.
User manual Rev. 1.0 — 28 June 2021
7 / 26

NXP Semiconductors UM11595
PTN38007-EVM/PTN38003A-EVM evaluation board
4.3.2 Type-C connector and PTN38007/3A (UFP)
aaa-042397
D
KP1_B
D
N
D
K
P
0
_
R
X
1
P
D
KP1_
T
X
1
P
D
K
P
1
_
T
D
P
D
KP1_
C
C
2
D
K
P
0
_
T
X
2
P
G
N
D
2
D
KP1_
R
X
2
N
G
N
D
2
D
K
P
1
_
B
D
N
D
KP1_
T
D
P
D
K
P
0
_
T
X
1
N
D
K
P
1
_
T
D
N
D
KP1_SB
U
1
D
K
P
0
_
R
X
2
P
G
N
D
2
D
KP1_
R
X
1
N
D
K
P
1
_
B
D
P
D
KP1_SB
U
2
VBu
s
_P1
D
K
P
0
_
T
X
1
P
J
2
0
1
U
S
B
T
y
p
e
C
R
e
c
e
p
t
a
c
l
e
G
N
D
1
A
1
T
X
1
+
A
2
T
X
1
-
A
3
V
B
U
S
1
A
4
C
C
1
A
5
D
1
+
A
6
D
1
-
A
7
S
B
U
1
A
8
V
B
U
S
2
A
9
R
X
2
-
A
1
0
R
X
2
+
A
1
1
G
N
D
2
A
1
2
G
N
D
3
B
1
T
X
2
+
B
2
T
X
2
-
B
3
V
B
U
S
B
4
C
C
2
B
5
D
+
B
6
D
-
B
7
S
B
U
2
B
8
V
B
U
S
3
B
9
R
X
1
-
B
1
0
R
X
1
+
B
1
1
G
N
D
B
1
2
S
H
1
1
S
H
2
2
S
H
3
3
S
H
4
4
S
H
5
5
S
H
6
6
D
KP1_
T
X
2
P
D
K
P
1
_
S
B
U
1
D
KP1_B
D
P
D
K
P
0
_
R
X
2
N
VBu
s
_P1
J
2
0
2
D
X
0
7
P0
2
4
AJ
1
R
1
5
0
0
G
N
D
1
A
1
S
S
T
X
P1
A
2
S
S
T
X
N
1
A
3
V
B
U
S
1
A
4
C
C
1
A
5
D
P
1
A
6
D
N
1
A
7
S
B
U
1
A
8
V
B
U
S
2
A
9
S
S
R
X
N
2
A
1
0
S
S
R
X
P
2
A
1
1
G
N
D
2
A
1
2
G
N
D
3
B
1
S
S
T
X
P
2
B
2
SS
T
X
N
2
B
3
V
B
U
S
3
B
4
C
C
2
B
5
S
BU
2
B
8
V
B
U
S
4
B
9
S
S
R
X
N
1
B
1
0
S
SR
X
P
1
B
1
1
G
N
D
4
B
1
2
G
1
G
1
G
2
G
2
G
4
G
4
G
5
G
5
D
P
B
6
D
N
B
7
G
3
G
3
G
6
G
6
D
KP1_
R
X
1
P
D
K
P
1
_
C
C
2
D
KP1_
C
C
1
VBu
s
_P1
D
KP1_
T
X
2
N
D
KP1_
T
D
N
D
K
P
0
_
R
X
1
N
VBu
s
_P1
D
KP1_
T
X
1
N
D
K
P
1
_
C
C
1
D
K
P
0
_
T
X
2
N
G
N
D
2
D
KP1_
R
X
2
P
D
K
P
1
_
S
B
U
2
Figure 6. Schematic of Type-C Connector and PTN38007/3A (UFP)
The connection between PTN38007/3A and upstream/downstream Type-C receptacles
are according to the datasheet’s pin assignment.
When PTN38007/3A is used in UFP configuration, the board is marked with ‘D2’ as
“connecting to Device side”. J201 is used as a UFP port that plugs into a computer, and
J202 is used as a DFP port that plugs into a device or dock. CC1/CC2/VBUS/SBU1/
SUB2/USB2_D± signals pass through from the plug side to receptacle side.
Figure 7. Schematic of UFP board
On the UFP board, PTN38007/3A’s 7-bit I2C address is set to 0110 011 by connecting
ADDR/ORIENT pin to VDD directly. This address is being used by GUI to distinguish if
a DFP or a UFP board is being used. The AUTO_ORIENTATION_EN pin is pulled up by
default, thus the AUTO ORIENTATION DETECTION function is enabled. However, this
will not impact the normal operation. GUI scripts will always override this function, and
correct orientation is always programmed.
UM11595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.
User manual Rev. 1.0 — 28 June 2021
8 / 26

NXP Semiconductors UM11595
PTN38007-EVM/PTN38003A-EVM evaluation board
4.3.3 Low-speed switches
There are two layers of low-speed switches using NX3DV221 multiplexers; they are used
to sort out the correct polarity of the SBU signals, and then route to PTN38007/3A for
snooping purposes.
U104 is implemented as a crossbar switch to orient SBU1 and SBU2 signals as AUXP/
AUXN or AUXN/AUXP according to the MUX_ORIENTATION signal. U103 routes the
corresponding SBU1/2 signals to PTN38007/3A’s AUX and LS snooping pins, depending
on whether the interface is in DP alternate mode or Thunderbolt/USB4 mode.
Thunderbolt/USB4 mode and LS signal snooping is only available in PTN38007/3A, and
should be ignored in PTN38003A. In a design, these muxes are not needed since the
AUX snooping polarity can be changed through PTN38003A’s register 0x04 bit [3].
aaa-042398
D
P
_
T
B
T
_OEn1
A
U
X
N
_
L
S
R
X
1
H
P
1
_
S
B
U
2
_
1
A
U
X
N
1
G
N
D
1
C
1
2
3
0
.
1
u
F
V
D
D
3
V
3
_
1
M
U
X
_
O
R
I
E
N
T
A
T
I
O
N
1
V
D
D
3
V
3
_
1
A
U
X
P
1
L
S
R
X
1
C
1
2
4
0
.
1
u
F
D
P
_
T
B
T
_SE
L
1
L
S
T
X
1
G
N
D
1
H
P
1
_
S
B
U
1
_
1
U
1
0
4
N
X
3
D
V
2
2
1
G
M
D
+
8
D
-
7
G
N
D
5
1
D
-
2
1
D
+
1
2
D
-
4
2
D
+
3
O
E
6
V
C
C
1
0
S
9
U
1
0
3
N
X
3
D
V
2
21GM
D
+
8
D
-
7
G
N
D
5
1
D
-
2
1
D
+
1
2
D
-
4
2
D
+
3
O
E
6
V
C
C
1
0
S
9
A
U
X
P_LS
T
X
1
Figure 8. Schematic of low-speed switches
4.3.4 GPIO expanders
Low-speed switch controls are configured through the GPIO expanders. The GUI user
interface also incorporates these controls.
aaa-042399
C
1
2
2
0
.
1
u
F
D
P
_
T
B
T
_OEn1
S
C
L
1
D
P
_
T
B
T
_SEL1
7
-
B
i
t
A
d
d
r
e
s
s
0
1
0
-
0
1
0
0
=
0
x
2
4
U
1
0
2
P
C
A95
7
0
G
M
H
P
0
1
P
1
2
P
2
3
VSS
4
P
3
5
S
C
L
6
S
D
A
7
V
D
D
8
S
D
A
1
V
D
D
3
V
3
_
1
G
N
D
1
M
U
X
_
O
R
I
E
N
T
A
T
I
O
N
1
Figure 9. Schematic of GPIO expanders
The following table summarizes the GPIO expander’s control signal assignment; its 7-bit
I2C slave address is 010 0100.
Bit Signal Name Comment
0 DP_TBT_SEL Select DisplayPort or Thunderbolt mode
0 = DisplayPort Alternate Mode
1 = Thunderbolt Alternate Mode
1 MUX_ORIENTATION Select CC line orientation
0 = Normal orientation
1 = Reversed orientation
Table 1. Control signal assignment for GPIO expander
UM11595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.
User manual Rev. 1.0 — 28 June 2021
9 / 26

NXP Semiconductors UM11595
PTN38007-EVM/PTN38003A-EVM evaluation board
Bit Signal Name Comment
2 DP_TBT_OEn Enable/Disable low-speed switch outputs
0 = Enabled
1 = Disabled
3 Output Not Used Data bit is used to further distinguish different operating modes
with the same byte programming.
Table 1. Control signal assignment for GPIO expander...continued
In each device operating mode, each bit should be configured as shown in Table 2 and
Table 3. Therefore, a predefined byte can be programmed to the GPIO expander’s output
while transitioning into different modes.
DFP configuration Mode 0
Safe State
Mode 1
USB3 Only
Mode 2
USB3+DP2Lane
Mode 3
DP4Lane
Mode 4
Thunderbolt
Mode 5
USB4.0
0 DP_TBT_SEL 1 1 0 0 0 0
1 MUX_ORIENTATION 0/1 0/1 0/1 0/1 0/1 0/1
2 DP_TBT_OEn 0 0 0 0 1 1
3 Not Used 0 1 0 1 0 1
Byte Programming 0x04/0x06 0x0c/0x0e 0x00/0x02 0x08/0x0a 0x01/0x03 0x09/0x0b
Table 2. DFP configuration
UFP configuration Mode 0
Safe State
Mode 1
USB3 Only
Mode 2
USB3+DP2Lane
Mode 3
DP4Lane
Mode 4
Thunderbolt
Mode 5
USB4.0
0 DP_TBT_SEL 1 1 0 0 0 0
1 MUX_ORIENTATION 0/1 0/1 0/1 0/1 0/1 0/1
2 DP_TBT_OEn 0 0 1 1 0 0
3 Not Used 0 1 0 1 0 1
Byte Programming 0x04/0x06 0x0c/0x0e 0x01/0x03 0x09/0x0b 0x00/0x02 0x08/0x0a
Table 3. UFP configuration
4.3.5 Board headers
aaa-042400
H
P
1
_
C
C
1
_
1
S
C
L
1
V
D
D
3
V
3
_
1
VBu
s
_P0
J
1
0
3
F
T
S
H
-
1
0
5
-
0
3
-
L
-
D
V
1
2
3
4
5
6
7
8
9
1
0
S
D
A
1
V
D
D
3
V
3
_
1
VBu
s
_P0
G
N
D
1
J
1
0
4
F
T
S
H
-
1
0
5
-
0
3
-
L
-
D
V
1
2
3
4
5
6
7
8
9
1
0
G
N
D
1
V
D
D
1
V
8
_
1
H
P
1
_
C
C
2
_
1
G
N
D
1
Figure 10. Schematic of board headers
There are two 10-pin 50-mil spacing headers (J103 and J104) providing signal
connection to the PTN5110 PD baseboard (or LPCUSBSIO module) when the PD
baseboard is used. While using PTN38007/3A-EVM evaluation board by itself, J104 can
also connect to Aardvark I2C/SPI Host Adapter or Promira Serial Platform with a 100 mil
spacing to 50 mil spacing adapter (Digikey Part# 1471-1373-ND).
UM11595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.
User manual Rev. 1.0 — 28 June 2021
10 / 26

NXP Semiconductors UM11595
PTN38007-EVM/PTN38003A-EVM evaluation board
Figure 11. Connection of board headers
4.3.6 1.8 V and 3.3 V power supplies
The board is supplied with one 5 V power supply source through J105 (micro-USB
connector) when in stand-alone mode (without LPCUSBSIO module). There is an LDO
power supply that converts 5 V to 3.3 V and 1.8 V. The 1.8 V power supply is used by
PTN38007/3A, and the 3.3 V power supply is used by the GPIO expander.
aaa-042402
V
D
D
3
V
3
_
1
V
D
D
1
V
8
_
1
J
1
0
5
U
S
B
M
i
c
r
o
B
V
B
U
S
1
D
-
2
D
+
3
I
D
4
G
N
D
5
T
1
6
T
2
7
U
1
0
5
M
I
C
5
3
57-
S
G
Y
M
M
E
V
I
N
1
G
N
D
2
B
Y
P
3
E
N
2
4
E
N
1
5
N
C
6
V
O
U
T
2
(
1
V
8
)
7
V
O
U
T
1
(
3
V
3
)
8
e
P
A
D
9
C
1
2
6
2
.
2
u
F
C
1
2
8
0
.
1
u
F
G
N
D
1
C
1
2
5
2
.
2
u
F
C
1
2
7
2
.
2
u
F
G
N
D
1
V
D
D
5
V
0
_
I
N
_
1
G
N
D
1
Figure 12. Schematic of 1.8 V and 3.3 V power supplies
If the PTN38007/3A-EVM evaluation board is used with an LPCUSBSIO module, USB2
connection to the PTN5110 Sniffer Board (or LPCUSBSIO module) also provides 5 V to
the system. There are two switching power supplies on the PTN5110 Sniffer Board (or
LPCUSBSIO module) converting 5 V to 1.8 V and 3.3 V; these two power rails are fed
into J103 pin 4 (3.3 V), pin 6 (3.3 V), and pin 8 (1.8 V). PTN38007/3A-EVM evaluation
board can directly consume power from these pins, and it is not necessary to provide
additional power to J105 in this configuration.
Using the LPCUSBSIO module is recommended, and by default, U105 and J105 are not
installed.
5 I2C programming guide
By default, the following 7-bit I2C addresses are used:
•GPIO Expander: 010 0100
•PTN38007/3: 0110 000 (DFP – H2 board) or 0110 011 (UFP – D2 board)
In this section, the following conventions indicate writing to respective device’s internal
register addresses:
•GPIO[] = 0xrr: Set GPIO expander’s port data to value of 0xrr (there is only one register
in this GPIO expander, and there is no need to indicate the address in this context).
This is equivalent to GPIO[0xrr] = 0xrr
UM11595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.
User manual Rev. 1.0 — 28 June 2021
11 / 26

NXP Semiconductors UM11595
PTN38007-EVM/PTN38003A-EVM evaluation board
•Reg[0xnn] = 0xrr: Set PTN38007/3’s register @ address 0xnn to value of 0xrr
5.1 Power-on initialization
// Initialize GPIO Expander
GPIO[] = 0x04 // In Safe State
// PTN38007/3A Initialization for Safe State
// USB3 Initialization
Reg[0x0f] = 0x00 // Enable LOS Detector
Reg[0x10] = 0x0e // Downstream RCTL[2:1] = 10dB, should adapt to
different PCB design if necessary
Reg[0x12] = 0x0e // Upstream LCTL[2:1] = 10dB, should adapt to
different PCB design if necessary
Reg[0x11] = 0x03 // Upstream RCTL[3] = 950mVppd, should adapt to
different PCB design if necessary
Reg[0x13] = 0x03 // Downstream LCTL[3] = 950mVppd, should adapt
to different PCB design if necessary
// DisplayPort Initialization
Reg[0x07] = 0x0e // Lane 0 LCTL[2:1] = 8.3dB, should adapt to
different PCB design if necessary
Reg[0x09] = 0x0e // Lane 1 LCTL[2:1] = 8.3dB, should adapt to
different PCB design if necessary
Reg[0x0b] = 0x0e // Lane 2 LCTL[2:1] = 8.3dB, should adapt to
different PCB design if necessary
Reg[0x0d] = 0x0e // Lane 3 LCTL[2:1] = 8.3dB, should adapt to
different PCB design if necessary
Reg[0x08] = 0x03 // Lane 0 LCTL[3] = 950mVppd, should adapt to
different PCB design if necessary
Reg[0x0a] = 0x03 // Lane 1 LCTL[3] = 950mVppd, should adapt to
different PCB design if necessary
Reg[0x0c] = 0x03 // Lane 2 LCTL[3] = 950mVppd, should adapt to
different PCB design if necessary
Reg[0x0e] = 0x03 // Lane 3 LCTL[3] = 950mVppd, should adapt to
different PCB design if necessary
// Thunderbolt Initialization
Reg[0x15] = 0x09 // Downstream RCTL[2:1] = 12.7dB, should adapt
to different PCB design if necessary
Reg[0x17] = 0x09 // Upstream LCTL[2:1] = 12.7dB, should adapt to
different PCB design if necessary
Reg[0x16] = 0x03 // Upstream RCTL[3] = 950mVppd, should adapt to
different PCB design if necessary
UM11595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.
User manual Rev. 1.0 — 28 June 2021
12 / 26

NXP Semiconductors UM11595
PTN38007-EVM/PTN38003A-EVM evaluation board
Reg[0x18] = 0x03 // Downstream LCTL[3] = 950mVppd, should adapt
to different PCB design if necessary
// DFP SafeState Initialization
Reg[0x04] = 0x00 // Default Safe State, With Normal Orientation
5.2 Operating mode programming
Depending on the operating mode negotiated between the DFP and UFP sides, the
following registers should be programmed accordingly.
5.2.1 DFP board programming
If the evaluation board is not used, GPIO programming steps are not necessary, and only
PTN38007/3A programming steps are required.
Orientation
DFP Modes
Normal Orientation Reversed Orientation
Safe State (Mode = 0) GPIO[] = 0x04
Reg[0x04] = 0x00
GPIO[] = 0x06
Reg[0x04] = 0x10
USB3 Only (Mode = 1) GPIO[] = 0x0c
Reg[0x04] = 0x01
GPIO[] = 0x0e
Reg[0x04] = 0x11
USB3+DP2Lane (Mode = 2) GPIO[] = 0x00
Reg[0x04] = 0x02
GPIO[] = 0x02
Reg[0x04] = 0x12
DP4Lane (Mode = 3) GPIO[] = 0x08
Reg[0x04] = 0x03
GPIO[] = 0x0a
Reg[0x04] = 0x13
Thunderbolt (Mode = 4) GPIO[] = 0x01
Reg[0x04] = 0x04
GPIO[] = 0x03
Reg[0x04] = 0x14
USB4 (Mode = 5) GPIO[] = 0x09
Reg[0x04] = 0x05
GPIO[] = 0x0b
Reg[0x04] = 0x15
Table 4. DFP modes orientation
5.2.2 UFP board programming
If the evaluation board is not used, GPIO programming steps are not necessary, and only
PTN38007/3A programming steps are required.
Orientation
UFP Modes
Normal Orientation Reversed Orientation
Safe State (Mode = 0) GPIO[] = 0x04
Reg[0x04] = 0x20
GPIO[] = 0x06
Reg[0x04] = 0x30
USB3 Only (Mode = 1) GPIO[] = 0x0c
Reg[0x04] = 0x21
GPIO[] = 0x0e
Reg[0x04] = 0x31
USB3+DP2Lane (Mode = 2) GPIO[] = 0x01
Reg[0x04] = 0x22
GPIO[] = 0x03
Reg[0x04] = 0x32
DP4Lane (Mode = 3) GPIO[] = 0x09
Reg[0x04] = 0x23
GPIO[] = 0x0b
Reg[0x04] = 0x33
Table 5. UFP modes orientation
UM11595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.
User manual Rev. 1.0 — 28 June 2021
13 / 26

NXP Semiconductors UM11595
PTN38007-EVM/PTN38003A-EVM evaluation board
Orientation
UFP Modes
Normal Orientation Reversed Orientation
Thunderbolt (Mode = 4) GPIO[] = 0x00
Reg[0x04] = 0x24
GPIO[] = 0x02
Reg[0x04] = 0x34
USB4 (Mode = 5) GPIO[] = 0x08
Reg[0x04] = 0x25
GPIO[] = 0x0a
Reg[0x04] = 0x35
Table 5. UFP modes orientation...continued
6 LPCUSBSIO module
The LPCUSBSIO module can be used with PTN38007/3A-EVM evaluation board
together to demonstrate programmability of PTN38007/3A through only I2C-bus interface.
This module includes a PTN5110 PD PHY and a LPC11U35 microcontroller, and can
sniff or monitor CC line traffic to detect if a different alternate mode is negotiated between
host and device, and program PTN38007/3A to enter the respective alternate mode
accordingly.
If PTN38007/3A-EVM evaluation board is plugged onto a PTN5110 PD baseboard, a PD
CC line sniffer and a microcontroller on the baseboard monitors the plug-in orientation,
the CC line communications between the upstream port and downstream port are
decoded, and the on-board microcontroller configures PTN38007/3A and multiplexers
according to the CC communication.
A user can still use the GUI interface and LPCUSBSIO (built-in function in LPCUSBSIO
module) to monitor and/or further configure the board if necessary. A separate GUI is
also available to communicate between the on-board LPC microcontroller and host PC
using USB2.0 interface. By default, the PD sniffer function is not used, and only the
USB-2-I2C bridge (LPCUSBSIO) is implemented in the firmware flashed to the module.
UM11595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.
User manual Rev. 1.0 — 28 June 2021
14 / 26

NXP Semiconductors UM11595
PTN38007-EVM/PTN38003A-EVM evaluation board
6.1 Block diagram
aaa-042414
T
Y
P
E
-
C
R
E
C
E
P
T
A
C
L
E
T
Y
P
E
-
C
R
E
C
E
P
T
A
C
L
E
T
Y
P
E
-
C
P
L
U
G
P
T
N
3
8
0
0
7
/
P
T
N
3
8
0
0
3
A
R
X
2
T
X
2
T
X
1
R
X
1
C
C
2
R
X
2
T
X
2
T
X
1
R
X
1
C
C
1
S
B
U
2
S
B
U
1
T
o
p
U
S
B
_
D
±
B
o
t
t
o
m
U
S
B
_
D
±
C
C
2
C
C
1
D
2
±
D
1
±
S
B
U
2
S
B
U
1
V
B
U
S
V
B
U
S
C
C
2
C
C
1
D
2
±
D
1
±
S
B
U
2
S
B
U
1
V
B
U
S
A
U
X
P
A
U
X
N
S
D
A
/
M
2
S
C
L
/
M
1
A
D
D
R
L
C
T
R
L
1
R
C
T
R
L
3
R
C
T
R
L
2
R
C
T
R
L
1
L
C
T
R
L
3
L
C
T
R
L
2
L
S
R
X
L
S
T
X
P
C
A
9
5
7
0
(
G
P
I
O
)
J
1
0
4
J
1
0
5
(
µ
U
S
B
)
J
1
0
3
M
I
C
5
3
5
7
5
V
3
V
3
1
V
8
T
Y
P
E
-
C
P
L
U
G
C
C
2
C
C
1
S
B
U
2
S
B
U
1
T
o
p
U
S
B
_
D
±
B
o
t
t
o
m
U
S
B
_
D
±
C
C
2
C
C
1
D
2
±
D
1
±
S
B
U
2
S
B
U
1
V
B
U
S
V
B
U
S
C
C
2
C
C
1
D
2
±
D
1
±
S
B
U
2
S
B
U
1
V
B
U
S
R
X
2
T
X
2
T
X
1
R
X
1
J
3
0
6
J
3
0
7
L
P
C
1
1
U
3
5
F
E
T
4
8
U
A
R
T
S
P
I
I
2
C
P
T
N
5
1
1
0
I
2
C
R
a
J
3
0
(
µ
U
S
B
)
U
S
B
_
D
±
J
3
0
2
(
S
W
D
)
J
3
0
3
(
U
A
R
T
/
S
P
I
/
I
2
C
)
X
C
L
2
2
1
B
1
8
1
X
C
L
2
2
2
B
3
3
1
F
B
V
B
U
S
5
V
0
Figure 13. Block diagram
6.2 PCB photo
Figure 14. PTN5110 sniffer board; front side
UM11595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.
User manual Rev. 1.0 — 28 June 2021
15 / 26

NXP Semiconductors UM11595
PTN38007-EVM/PTN38003A-EVM evaluation board
Figure 15. PTN5110 sniffer board; back side
6.3 Connection
PTN38007/3A-EVM evaluation board and LPCUSBSIO module should be sandwiched
together such that J103 is mated with J307, and J104 is mated with J306. There is
no Type-C plug installed on the LPCUSBSIO module by default, and J305 (Type-C
receptacle) on the LPCUSBSIO module should not be used. This forces the user to use
only J101 to connect to host side, and J102 to connect to device side.
A micro-USB cable should be connected to J301 on the LPCUSBSIO module to provide
power to the entire setup. This USB cable allows the use of NXP’s LPCUSBSIO USB-2-
I2C bridge to communicate with PTN38007/3’s I2C via USB2 interface. The Aardvark I2C/
SPI host adapter can be connected to the setup using a 50 mil spacing 10-pin cable on
LPCUSBSIO module’s J303.
Figure 16. Connection of PTN38007/3A-EVM evaluation board and LPCUSBSIO module
6.4 Firmware update
From time to time, NXP provides the latest firmware update for the EVM to fix issues
found in the code. Follow these steps to perform the firmware upgrade:
1. Connect a micro-USB cable to J301 first, without plugging into the PC.
UM11595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.
User manual Rev. 1.0 — 28 June 2021
16 / 26

NXP Semiconductors UM11595
PTN38007-EVM/PTN38003A-EVM evaluation board
2. Locate SW302 ISP switch on the sniffer board, and hold it down while plugging in the
micro-USB cable to the PC.
3. Release SW302 switch, and on your PC, you will see a disk drive “CRP DISABLD”
show up under “computer.”
4. Right click “firmware.bin” in the “CRP DISABLD” driver, and select Delete. Select
“Yes” when a pop up window asks to confirm deleting the file.
UM11595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.
User manual Rev. 1.0 — 28 June 2021
17 / 26

NXP Semiconductors UM11595
PTN38007-EVM/PTN38003A-EVM evaluation board
5. Locate the new firmware on your hard drive (with .bin extension), and drag the file into
“CRP DISABLD” folder.
6. The new binary file should appear in the “CRP DISABLD” drive. The firmware update
is completed. Remove and then reinsert the micro-USB cable from your computer to
emulate power on reset condition.
7. The new firmware is now running on the LPCUSBSIO module.
7 GUI introduction
The I2C GUI control interface can be used to monitor and change the PTN38007/3A
registers, as well as configure the GPIO expander. This tool can be used in stand-alone
mode, or concurrently with LPCUSBSIO module plug in.
7.1 List of files
The GUI zip file contains the following:
Drake.exe GUI executable. Click on this file to run the GUI.
liblpcusbsio.dll LPCUSBSIO library
Script_File.txt A list of default script files to be loaded when GUI is open.
User may edit this file to change default scripts to be loaded.
PTN38007/3.txt
PTN38003A.txt
Default product script file(s). If the file exists, for each
matched product type that is found during I2C address
search, the corresponding product script is executed once.
These script files are useful to set up default equalizer
settings.
Table 6. GUI zip file contents
UM11595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.
User manual Rev. 1.0 — 28 June 2021
18 / 26

NXP Semiconductors UM11595
PTN38007-EVM/PTN38003A-EVM evaluation board
P2R_DFP_USB_2DP_
Normal.txt
P2R_DFP_USB_2DP_
Reversed.txt
P2R_DFP_4DP_Normal.txt
P2R_DFP_4DP_Reversed.txt
P2R_DFP_TBT_Normal.txt
P2R_DFP_TBT_Reversed.txt
P2R_DFP_USB4_Normal.txt
P2R_DFP_USB4_Reversed.txt
Script files for PTN38007/3/PTN38003A DFP Board
P2R_DFP_TBT_Normal/Reversed.txt and P2R_DFP_USB4_
Normal/Reversed.txt are only applicable to PTN38007/3
P2R_UFP_USB_2DP_
Normal.txt
P2R_UFP_USB_2DP_
Reversed.txt
P2R_UFP_4DP_Normal.txt
P2R_UFP_4DP_Reversed.txt
P2R_UFP_TBT_Normal.txt
P2R_UFP_TBT_Reversed.txt
P2R_UFP_USB4_Normal.txt
P2R_UFP_USB4_Reversed.txt
Script files for PTN38007/3/PTN38003A UFP Board
P2R_UFP_TBT_Normal/Reversed.txt and P2R_UFP_USB4_
Normal/Reversed.txt are only applicable to PTN38007/3
Table 6. GUI zip file contents...continued
7.1.1 Editing Script_File.txt
The Script_File.txt can be edited to load up to eight script files in the GUI. The list in the
GUI is refreshed when the GUI is first executed, or when I2C Reset is clicked. Note that
the following rules should be applied when editing the file:
•One entry per line.
•A blank line is counted as an entry without any file name loaded.
•Only the first eight lines/entries will be loaded; entries after line eight are discarded.
•When populating entries, it is the user’s responsibility to check if these script file entries
exist in the current directory. The GUI checks if the entry is valid when clicking the
script file name.
UM11595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.
User manual Rev. 1.0 — 28 June 2021
19 / 26

NXP Semiconductors UM11595
PTN38007-EVM/PTN38003A-EVM evaluation board
7.2 GUI fields
Figure 17. GUI fields
7.2.1 Interface
Connect /
Disconnect
When the LPCUSBSIO module is disconnected from the PC (in the event
of power cycle the evaluation board, or remove USB2 cable from the
module), user should first click on Disconnect then Connect to reinitialize
the LPCUSBSIO module.
I2C Reset When clicked, all possible I2C addresses in this product family are
rescanned, evaluation board type is determined, the default product script
(if present) is executed, and respective register values are updated on the
screen.
Clock Freq I2C-bus interface clock frequency. Default is set to 400 kHz. The interface
frequency can be changed by the user at any time, as long as the clock
speed is supported.
Device Address This field shows the evaluation board type and/or a list of product I2C
addresses found in the current setup.
•0x30 P2R_DFP – I2C Address = 0x30
•0x33 P2R_UFP – I2C Address = 0x33
Table 7. Interface
UM11595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.
User manual Rev. 1.0 — 28 June 2021
20 / 26