Model 53661 Getting Started Guide Page 7
Rev. 2.2
Before You Begin: Consider the Product’s Options
Timing and Synchronization
The following timing and synchronization options are available for the Model 71661
XMC module’s A/D converters (all input/output signals are the same as defined for
the standard Model 71660):
• Onboard VCXO and clock synthesizer: An onboard voltage controlled crystal
oscillator (VCXO) and internal FPGA registers provide onboard sources for all sync,
gate, and clock signals.
• External clock: The front panel has one SSMC coaxial connector, labeled CLK, for
input of an external sample clock. The external clock signal must be a sine wave or
square wave of +0 dBm to +10 dBm, with a frequency range from 10 to 500 MHz. The
external clock input can be used as the sample clock for the A/D converters. This
input is enabled using Sync Bus Control Register 1 (see the Model 71660 Operating
Manual). The clock source selected by these bits is input to a CDC7005 Clock
Synthesizer that generates separate output clocks, each programmable as sub−
multiples of the input frequency. One of the CDC7005 output clocks (Y0) provides
ADC timing.
NOTE: Ensure that the ADC clock never exceeds the ADS5485 rated clock speed
during any change of frequency with the input clock signal.
• Trigger input: The front panel has one SSMC coaxial connector, labeled TRIG, for
input of an external trigger. The external trigger signal must be an LVTTL signal. The
trigger input can be used as a gate or trigger for A/D signal processing. This input is
enabled using Sync Bus Control Register 2 TTL SRC bits (see the Model 71660
Operating Manual).
NOTE: The front panel TTL Gate and Sync signals are 5V tolerant but they must
not have any negative voltage applied. They are terminated with a 392−
ohm resistor to 3.3V and a 392−ohm resistor to ground.
•26−pin sync bus front panel connector: This connector (labeled SYNC/GATE)
provides clock, sync, and gate input/output pins for the Low−Voltage Positive Emit−
ter−Coupled Logic (LVPECL) Sync Bus. It allows multiple modules to be
synchronized. When the Model 71661 is a bus Master, these pins output LVPECL
Sync Bus signals to other slave units. When the 71661 is a bus Slave, these pins input
LVPECL signals from a bus Master. This connector also accepts two Low−Voltage
TTL (LVTTL) Gate/ Sync inputs. For a description of the SYNC/GATE connector pin
configuration, refer to the Model 53661 Installation Manual.
NOTE: When connecting LVPECL Sync Bus pins to additional Model 71661
modules, the LVPECL pins on the LAST unit must be terminated. Pentek
includes a terminating board, part # 002.71504, with your shipment for
this purpose.
