Pentek 6470 User manual

OPERATING MANUAL
MODEL 6470
10 Bit 70 MHz
A/D CONVERTER
Pentek, Inc.
One Park Way
Upper Saddle River, NJ 07458
[phone]
Copyright ©1994
Manual Part No: 800.64700 Rev: Prelim

WARRANTY
Pentek warrants that all products manufactured by Pentek conform to published Pentek specifica-
tions and are free from defects in materials and workmanship for a period of one year from the
date of delivery when used under normal operating conditions and within the service condi-
tions for which they were furnished.
The obligation of Pentek arising from a warranty claim shall be limited to repairing or at its
option, replacing without charge, any product which in Pentek’s sole opinion proves to be
defective within the scope of the warranty.
Pentek must be notified in writing of the defect or nonconformity within the warranty period and
the affected product returned to Pentek within thirty days after discovery of such defect or non-
conformity.
Buyer shall prepay shipping charges, taxes, duties and insurance for products returned to Pentek
for warranty service. Pentek shall pay for the return of products to buyer except for products
returned from another country.
Pentek shall have no responsibility for any defect or damage caused by improper installation,
unauthorized modification, misuse, neglect, inadequate maintenance, accident or for any product
which has been repaired or altered by anyone other than Pentek or its authorized representatives.
The warranty described above is buyer’s sole and exclusive remedy and no other warranty,
whether written or oral, is expressed or implied. Pentek specifically disclaims fitness for a
particular purpose. Under no circumstances shall Pentek be liable for any direct, indirect, spe-
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Printed in the United States of America. All rights reserved. Contents of this publication may
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Pentek Model 6470 10-Bit 70 MHz A/D Converter
APPLICATIONS
-HF Communications Receivers
-Instrumentation Receivers
-Spread Spectrum Signal Processors
-Wideband Data Acquisition
-Signal Processor Front End
TECHNICAL DESCRIPTION
Analog HF signals are input through a front
panel mounted BNC connector to a preampli-
fier that terminates the input in a 50 Ohm load
andprovidesoverloadprotectionforsubsequent
stages. The output of the preamplifier is pro-
cessed by a two stage preselector with inter-
spersedvariablegainamplifiers.Thepreselector
is configured as a set of second order lowpass
filters followed by a similar set of highpass fil-
tersthat allow the user to construct a set of fairly
broad bandpass filters to control out-of-band
interference that would otherwise diminish dy-
namic range. The variable gain amplifiers pro-
vide up to 80 dB of gain variation to support
high level signals from other systems or for di-
rect connection to an antenna. The output of the
second variable gain amplifier is processed by
a 32 MHz sharp cutoff antialiasing filter. A ten
bit analog to digital converter is used to digi-
tize the conditioned HF signal at a sample rate
of70Megasamplespersecondusinganonboard
crystal oscillator or an external source. The user
may also add one or two additional oscillators
to provide selectable sample rates.
INTRODUCTION
The Model 6470 is a single 6U VME board that
implements the front end signal conditioning
andvariablegainamplifiersinadditiontoahigh
speed analog to digital converter operating at a
sample rate of 70 MHz. The Model 6470 fea-
tures an analog RF preselector to reject out of
bandinterference that would otherwise consume
dynamic range. Two variable gain amplifier
stages provide up to 80 db of gain control, al-
lowing the board to acquire low level signals or
signals that have been processed by other sig-
nal conditioning systems. An onboard
antialiasing filter restricts the input bandwidth
to approximately 32 MHz. The analog to digi-
tal converter has resolution of twelve bits that
are available as differential ECL signals on the
front panel. The user has the option of selecting
eithersingle ended or differential dataandclock.
The VME bus backplane is used only for con-
trol.
The Model 6470 is intended to be used with a
wideband digital filter, digital tuner, or other
high speed digital signal processor as part of a
multiple board DSP system. Custom versions
of the Model 6470 are available with different
sample rates and filter cutoff frequencies. For
systemapplications where external bandlimiting
is provided, the onboard antialiasing filter can
bebypassed. The user may also choose between
AC and DC input signal coupling or input dis-
connection.

PRELIMINARYSPECIFICATIONS
INPUT CHARACTERISTICS
Impedance: 50 Ohms, Single Ended
Coupling: DC or AC (100 Hz Cutoff)
Sensitivity: 2 mV to 3 V p-p
PRESELECTOR LOWPASS SELECTIONS
2 MHz
5 MHz
12 MHz
Bypass
PRESELECTOR HIGHPASS SELECTIONS
2 MHz
4 MHz
7 MHz
Bypass
ANTIALIAS FILTER
32 MHz Equiripple Lowpass
Bypass
A/D CONVERTER PERFORMANCE
Resolution: 10 Bits
Conversion Speed: 70 MSPS
or User Supplied Internal or
External Source
Analog Bandwidth: 175 MHz
Harmonic Distortion: < 59 dBc
Intermodulation Distortion: < 70 dBc
Signal to Noise Ratio: >55 dB
OUTPUT CHARACTERISTICS
Data: 12 bit Differential ECL,
Two’s Complement
Clock: Differential ECL
SIGNAL PROCESSING BANDWIDTH
35 MHz
PHYSICAL CHARACTERISTICS
Single Height 6U VME Form Factor
▲
▲ ▲
▲ ▲▲
Filter, Amplifier, and Clock Control Registers
(VMEbus Slave Interface)
▲
Variable
Gain Amp
Variable
Gain Amp
Preselect
High Pass
V
M
E
b
u
s
Model 6470
A/D Converter
Block Diagram
▲
▲
Preselect
Low Pass
▲ ▲
Preamp
▲ ▲
10-bit
70 MHz
A/D
Output
Buffers
Antialias
Low Pass
▲
Clock
Generator
Signal
Input
Clock
Input
▲
▲
▲
Front
Panel
Connector

Pentek Model 6470 Technical Description
Preselector Lowpass Filter
Forapplicationswheretheentiresignalprocess-
ing bandwidth of the digitizer is not required,
the user can select one of three different second
order lowpass filter sections to reject out-of-
band interference and improve the dynamic
range of the system. Currently the user can
choose 2 MHz, 5 MHz, 12 MHz or no filtering
under software control.
Preselector Highpass Filter
As in the case of the lowpass selections de-
scribed above, the user can choose one of three
different second order highpass filter sections
under software control to reject out-of-band in-
terference. Standard cutoff frequencies are 3
MHz, 8 MHz, 18 MHz, or no filtering.
Programmable Gain Amplifier
The Model 6470 includes a two stage amplifier
with software programmable gain and offset
trim. Each stage follows one of the preselector
sections and provides 40 dB of gain variation.
Normally, it is advantageous to achieve most
ofthetotalgainneededinthefirststagetomaxi-
mize the signal-to-noise ratio. The gain of the
second stage is then set to fully utilize the dy-
namic range of the analog to digital converter.
Voltagecontrolled amplifiers are employed that
are driven by D/A converters. In addition, D/A
converters are provided to remove offset volt-
ages.
Technical Overview
The Pentek Model 6470 is a complete 6U VME
wideband data acquisition front end designed
primarily for high frequency digital receiver
applications.TheModel6470includesapream-
plifier, preselector, programmable gain ampli-
fiers, antialias filter, and a 10 bit 70 MSPS ana-
log to digital converter. All of these functions
are controlled from the VME bus. The digital
data output from the AID converter is available
on the front panel in a number of different for-
mats through the use of one of several mezza-
nineboards that provide electrical and mechani-
calcompatibility with other system components.
The current interface mezzanine boards are de-
signed to provide compatibility with the Pentek
Model 4271 Digital Drop Receiver. Pentek also
offers a similar product, the Model 6425, that
will operate at up to 25 MSPS at 12 bit resolu-
tion. The Model 6425 is be compatible with the
Model 6470 for applications that require lower
bandwidth and can increased dynamic range.
Preamplifier
Thepreamplifier terminates theinputin 50 ohms
andprovides selectable AC or DC coupling with
a fixed gain of two. In addition, the preampli-
fier can be disconnected from the input connec-
tor under software control while maintaining a
50 ohm termination of the input connector. This
feature is useful during automatic setup of gain
and amplifier offsets.

Antialias Filter
A passive equiripple lowpass filter is included
to reject frequencies above half the nominal
sample rate of 70 MSPS. The standard cutoff
frequency for this filter is 30.0 MHz. However,
the Model 6470 may be ordered with a custom
filter as needed for special applications. It is
practical to specify filters with cutoff frequen-
cies as high as 32.0 MHz although the rejection
ofaliased energy may be reduced. The user may
also bypass this filter under software control if
the application includes an external filter or if it
is known that there are no signal components
that span the Nyquist frequency of the analog
to digital converter.
Analog to Digital Converter
The Model 6470 employs the Analog Devices
AD9060hybrid analog to digital converter mod-
ule.This device iscapableof operating atsample
rates of up to 75.0 MHz with 10 bit resolution.
The standard Model 6470 operates at a sample
rate of 70.0 MHz. The analog bandwidth of the
AD9060 is 175 MHz. Harmonic and
intermodulation distortion are at least 59dB be-
low a full scale carrier. The signal-to-noise ra-
tio is specified to be at least 55 dB.
Sample Clock
The Model 6470 includes a 70.0 MHz crystal
oscillator as the standard sample clock. In addi-
tion, sockets are provided for two additional
oscillators that may be installed by the user or
orderedthrough Pentek. When installed,theuser
may select any of these oscillators or an exter-
nal source under software control.
Output Drivers
The Model 6470 includes a mezzanine board
thatconvertsthesingle-endedECLsignalsfrom
the analog to digital converter to single-ended
TTL (only for reduced speed operation) or dif-
ferential ECL depending on the requirements
of the application. Outputs are provided on a
68 pin high density front panel connector. The
current configuration is designed to match the
Pentek Model 4271 digital drop receiver. Other
configurationscanbesupplied to match the spe-
cific physical and mechanical requirements of
a specific application.
VME Control Interface
TheModel 6470 includes a control interface that
allowsthe user to select data paths throughvari-
ous filters, choose amplifier gains and offsets,
and select the sample clock source. This inter-
face uses 16 address lines and 8 data lines. The
user controls the Model 6470 by writing to six
control registers. Each of these registers may
also be read from software to verify correct pro-
gramming. The Model 6470 occupies a block
of 16 bytes that may be positioned on any 16
byte block address within the 64 KByte space
reserved for small peripheral devices.

The Model 6470 Digitizer is configured by in-
stalling jumpers on four sets of jumper termi-
nals. Jumper JP1 contains a single row of five
pins that are used to select the polarity of the
clock output. To select normal clock polarity,
jumpers are installed between pins 1 and 2 and
between pins 3 and 4. To select inverted clock
polarity, jumpers are installed between pins 2
and 3 and between pins 4 and 5.
The Model 6470 decodes a block of 16 bytes
within the 64K VME short address space.
Jumper block JP3 is used to decode the address
modifier codes and to select the type of data
transfer. Since the Model 6470 uses short (16
bit)addressing, the address modifier code should
be2D for supervisorymodeand 29 fornon-privi-
leged mode.
Code 2D is selected by installing jumpers be-
tween pins 3 and 4, and between pins 9 and 10.
Code 29 is selected by installing jumpers be-
tween pins 3 and 4, between pins 7 and 8, and
between pins 9 and 10. Pins 13 And 14 are used
to identify interrupt acknowledge cycles and
should be left open. Pins 15 and 16 are used to
identify long word transfers. Since the Model
6470 uses byte addressing, these pins are also
left open. Jumper block JP4 is used to select
address bits A15 through A08 of the base ad-
dress. A zero is programmed by installing a
jumper while the absence of a jumper programs
a one. Jumper block JP5 is used to select ad-
dress bits A07 through A04. Note that the lower
four bits of this block are not used for base ad-
dress decoding but require the installation of
jumpers.
SIGNAL PINS CODE 2D CODE 29
AMS 1-2 OPEN OPEN
AM4 3-4 SHORT SHORT
AM3 5-6 OPEN OPEN
AM2 7-8 OPEN SHORT
AM 1 9-10 SHORT SHORT
AMO 11-12 OPEN OPEN
IACK* 13-14 OPEN OPEN
IWORD* 15-16 OPEN OPEN
JUMPE BI. K JP ADD M DEFI PRO
RAMMIN
JP4 JP5 SIGNAL PINS SIGNAL PINS
A15 1-2 A07 1-2
A14 3-4 A06 3-4
AI3 5-6 A05 5-6
A12 7-8 A04 7-8
All 9-10 SHORT 9-10
A10 11-12 SHORT 11-12
A09 13-14 SHORT 13-14
A08 15-16 SHORT 15-16 A
Once the user has selected a base address on a
16 byte boundary, onboard registers are ac-
cessed by reading or writing to add byte ad-
dresses. Data values are between 0 and 255. All
control registers are read/write,
allowing user software to verify setup values.
Note that accessing even addresses will result
in a bus error. The following control registers
are defined.
BYTE ADDRESS FUNCTION
XXX 1 FIRST STAGE AMPLIFIER GAIN
XXX3 FIRST STAGE AMPLIFIER OFFSET

XXXS SECOND STAGE AMPLIFIER GAIN
XXX7 SECOND STAGE AMPLIFIER OFF-
SET
XXX9 DATA PATH CONFIGURATION
XXXB CLOCK SOURCE SELECTION
Each of the variable gain amplifiers can be pro-
grammed to provide from 10 dB of attenuation
to 30 dB of gain. Minimum gain is selected by
writing a value of zero to the appropriate con-
trol register. Maximum gain
is selected by writing a value of 255 to the reg-
ister. Amplifier offset voltages can be adjusted
by writing to the amplifier offset registers. A
value of 128 results in no amplifier offset cor-
rection.
The data path configuration register contains
four fields of two bits each. The following
tables describe the data routing options avail-
able for each field.
Dl DO INPUT COUPLING
0 0 DISCONNECT
0 DISCONNECT
1 0 AC COUPLED
DC COUPLED
D3 D2 PRESELECTOR LOWPASS SELECT
0 0 BYPASS
0 1 1 MHz
1 0 3 MHz
1 1 5 MHz PRESELECTOR LOWPASS FIL-
TER ELECTION D
DS D4 PRESELECTOR HIGHPASS SE-
LECT
0 0 BYPASS
0 1 2 MHz
1 0 4 MHz
1 1 7 MHz
PR LECT R HI HPASS FILTER ELE Tl N C
DE
D7 D6 AID CONVERTER INPUT
0 0 DISCONNECT
0 1 DISCONNECT
1 0 ANTIALIAS FILTER SELECTED
1 1 ANTIALIAS FILTER BYPASSS A D
ONVERTER INPU ELECTION D