Pentek 6210 User manual

Pentek Model 6210 Operating Manual Page 1
Manual Part #: 800.62100 Rev.: C − April 5, 2001
Pentek, Inc.
One Park ay
Upper Saddle River, NJ 07458
(201) 818−5900
http://www.pentek.com/
Copyright © 1998 − 2001
OPERATING MANUAL
PENTEK MODEL 6210
Dual A/D Converter and Digital Receiver
VIM Module for Pente VIM Motherboards

Page 2 Pentek Model 6210 Operating Manual
Pentek Model 6210 Operating Manual − Revi ion Hi tory
WARRANTY
Pentek warrants that all products manufactured by Pentek conform to published Pentek specifications and are free from defects in
materials and workmanship for a period of one year from the date of delivery when used under normal operating conditions and
within the service conditions for which they were furnished.
The obligation of Pentek arising from a warranty claim shall be limited to repairing or at its option, replacing without charge, any
product which in Pentek’s sole opinion proves to be defective within the scope of the warranty.
Pentek must be notified in writing of the defect or nonconformity within the warranty period and the affected product returned
to Pentek within thirty days after discovery of such defect or nonconformity.
Buyer shall prepay shipping charges, taxes, duties and insurance for products returned to Pentek for warranty service. Pentek shall
pay for the return of products to buyer except for products returned from another country.
Pentek shall have no responsibility for any defect or damage caused by improper installation, unauthorized modification, misuse,
neglect, inadequate maintenance, accident or for any product which has been repaired or altered by anyone other than Pentek or its
authorized representatives.
The warranty described above is buyer’s sole and exclusive remedy and no other warranty, whether written or oral, is expressed or
implied. Pentek specifically disclaims fitness for a particular purpose. Under no circumstances shall Pentek be liable for any direct,
indirect, special, incidental or consequential damages, expenses, losses or delays (including loss of profits) based on contract, tort, or
any other legal theory.
COPYRIGHT INFORMATION
ith the exception of those items listed below, the entire contents of this publication are copyright © 1998−2001 Pentek, Inc., Upper Saddle River, NJ.
Appendix A, HSP50214B Data Sheet, is the copyrighted property of Intersil Corp., Palm Bay, FL, and is used with their kind permission.
Appendices B & C, AD6640 and AD603 Data Sheets, are the copyrighted property of Analog Devices, Inc., Norwood MA, and are used with their kind permission.
Appendix D, LTC1451 Data Sheet, is the copyrighted property of Linear Technology Corp., Milpitas, CA, and is used with their kind permission.
Date Rev Applicable Serial #’ Comment
08/14/98 Preliminary 9841001 − Forward Initial release.
11/16/98 Preliminary 9841001 − Forward Added bit D04 to the Control Register. Added Table 2−4 to explain PRCLK source and freq.
when the 6210 is a master. Added Figure 2−4 to show Sync and Clock signal sources.
2/18/99 Preliminary 9841001 − Forward Added table 3−12 on loading DAC. Added Section 3.8.1 explaining Gain Amplifier. Added
EEPROM format (Appendix A). Added sample code in Appendix B.
3/24/99 Preliminary 9841001 − Forward Replaced installation instructions, they now reflect the currently shipping product.
Replaced the Front Panel with the currently shipping product. Added Table 3−13 about full
scale values.
6/24/99 Preliminary 9841001 − Forward Corrected Figure 2−4, the sync lines were connected to the wrong place. Added note to Fig−
ure 2−4 about which Harris Chip is connected to which DSP on the Model 4290/4291. Cor−
rected figure 2−1, the Front Panel labeling changed slightly. Corrected option 102 (gain),
which was called option 101 throughout the manual. Added option 101 to the specs.
Replaced Harris addendum with current version.
3/6/00 A 9841001 − Forward Complete re−format − many tables removed & replaced w/ text. All references to 4290/91
changed to VIM motherboard, and non−address specific references to ‘C6x changed to VIM
motherboard processor. Updated & corrected Block Diagram. Sec. 1.7. Corrected supply
currents. Internal Oscillator is 64 MHz, not 65. Further corrections to Fig. 2−4. Note that
Gain values given in Table 3−6 for PGA do not account for filter insertion loss. Add Table 3−
9 describing format/packing of output data. Improved description of signal levels/limits
for EXT CLK IN. Improved description of control interface to HSP50214. Re−arrange
Appendices − Move EEPROM format to Appendix D; Replace Harris’s Data Sheet for
HSP50214 with Intersil’s & make it Appendix A; Add AD603 Data Sheet as Appendix B;
LTC1451 Data Sheet is Appendix C; Add bandwidth / sample rate calculation Application
Note as Appendix E; Old Appendix B (Programming Example) now covered in ReadyFlow
Manual for 6210 (Pentek part # 801.62100)
3/9/00 A.1 9841001 − Forward Add Options 020, 021, 030 & 101 to Specifications. Add AD6640 Data Sheet as Appendix B.
Bump all following Appendix names up 1 letter. Correct DDR part # in Fig. F.1 & TOC list−
ing for the figure. Also corrected another typo in Appendix F.
3/17/00 B 98041001 − Forward Copy Table 2−4 (PRCLK Divider) into Sec. 3.4.1, where the divider bit is discussed, as Table
3−3. Added Table 3−11 (A/D Output Data Coding) in Sec. 3.8.2. Other Table #’s changed
appropriately.
3/21/00 B.1 98041001 − Forward Logic was reversed for BIFO_Disable bit, D3 in Control Reg. Corrected in Table 3−2 and Sec.
3.4.2.
10/24/00 B.2 98041001 − Forward Sect 1.2 and 1.7, clarified the descriptions of Options 030 and 102.
4/5/01 C 98041001 − Forward Sec. 1.3 − Changed Option 101 in NOTE to Option 020. Sec. 2.3.1 − recommend that Ext.
Clock In be 2V p−p in amplitude. Add Sec. 2.3.1.1, on Duty Cycle Sensitivity. Sec. 2.4 − add
part #’s for Sync Bus − Serial I/O mating connector. Sec 2.4.1 − mention that Sync Bus can
support 8 units, & Model 9190 can sync up to 80 units. Also correct NOTE below Fig. 2−5 −
DDR2 is controlled by Proc. B or D. Add Sec. 2.4.1.6, on Sync Bus Compatibility. Sec. 2.4.2 −
Better description of how Serial Port signals are passed from Motherboard to FP connector,
less text in subsections. Sec. 2.4.3 − TTL−SYNC pulse must be at least 2 sample clocks wide.
Printed in the United States of America. All Rights Reserved. Contents of this publication may not be reproduced in any form without written permission.

Pentek Model 6210 Operating Manual Page 3
Page
Table of Contents
Rev.: C
Chapter 1: Overview
1.1 General Description..............................................................................................................................7
1.2 Input Section ...................................................................................................................................7
1.3 A/D Converters....................................................................................................................................8
1.4 Digital Drop Receivers.........................................................................................................................8
1.5 Connection to VIM Motherboard.......................................................................................................8
1.6 Simplified Block Diagram ...................................................................................................................9
Figure 1−1: Simplified Block Diagram...........................................................................................9
1.7 Specifications.......................................................................................................................................10
Chapter 2: Installation and Connections
2.1 Inspection.............................................................................................................................................13
2.2 Jumper Blocks......................................................................................................................................13
Table 2−1: Factory Jumper Setting ...............................................................................................13
Figure 2−1: Model 6210 PC Board, Showing Jumper Block & Mounting Hole ................14
2.2.1 External Clock Function Select Jumper ..........................................................................13
Table 2−2: External Clock ..............................................................................................13
2.3 Model 6210 Front Panel Features .....................................................................................................15
Figure 2−2: Model 6210 Front Panel..............................................................................................15
2.3.1 External Clock Input − EXT CLK ....................................................................................15
Figure 2−3: External Clock Input Circuit ....................................................................16
2.3.1.1 Duty Cycle Sensitivity...................................................................................15
2.3.2 Analog Inputs − CH1 IN, CH2 IN....................................................................................17
2.3.3 Indicator LEDs ...................................................................................................................17
2.3.3.1 Sync Bus Master LED − MAS .......................................................................18
2.3.3.2 Sync Bus Terminator LED − TRM ...............................................................18
2.3.3.3 Motherboard LEDs − 0, 1, 2 & 3..................................................................18
2.4 Sync Bus − Serial I/O Connector .....................................................................................................19
Figure 2−4: Front Panel Sync Bu − Serial I/O Connector Pin Numbering..........................19
2.4.1 Signals for Synchronizing Multiple Boards ...................................................................19
Table 2−3: Sync Bu − Serial I/O Pinout ...................................................................19
Figure 2−5: Block Diagram of Clock and Sync Signal Source ..............................20
2.4.1.1 MCLK, MCLK.................................................................................................21
2.4.1.2 PRCLK, PRCLK..............................................................................................21
Table 2−4: Ma ter PRCLK Signal Source & Frequency........................22
2.4.1.3 MSYNC, MSYNC ...........................................................................................22
2.4.1.4 SYNC1, SYNC1...............................................................................................22
2.4.1.5 SYNC2, SYNC2...............................................................................................23
2.4.1.6 Compatibility with Other Products’ Sync Buses ......................................23

Page 4 Pentek Model 6210 Operating Manual
Page
Table of Contents
Rev.: C
Chapter 2: Installation and Connections (continued)
2.4 Sync Bus − Serial I/O Connector (continued)
2.4.2 Serial Port Signals.............................................................................................................. 24
2.4.2.1 P0−CLKR1, P1−CLKR1................................................................................. 24
2.4.2.2 P0−FSR1, P1−FSR1 ........................................................................................ 24
2.4.2.3 P0−CLKS1, P1−CLKS1.................................................................................. 24
2.4.2.4 P0−DR1, P1−DR1........................................................................................... 24
2.4.2.5 P0−CLKX1, P1−CLKX1................................................................................. 25
2.4.2.6 P0−FSX1, P1−FSX1 ........................................................................................ 25
2.4.2.7 P0−DX1, P1−DX1........................................................................................... 25
2.4.3 TTL−SYNC......................................................................................................................... 25
2.5 Installing the Model 6210 on a VIM Motherboard........................................................................ 26
2.5.1 Preparing the VIM Module for Installation................................................................... 26
Figure 2−6: VIM Module Counter unk Screw ........................................................ 26
Figure 2−7: VIM Module Nylon Spacer...................................................................... 27
2.5.2 Installing the VIM Module on the VIM Motherboard................................................. 28
Figure 2−8: Model 4290 VIM Motherboard − Connector & Mounting Hole ... 29
Chapter 3: Memory Map and egister Descriptions
3.1 Overview ............................................................................................................................................. 31
3.2 Model 6210 Memory Map................................................................................................................. 31
Table 3−1: Model 6210 Memory Map........................................................................................... 31
3.3 ID EEPROM Readout Register ............................................................................................................. 32
3.4 Control Register.................................................................................................................................. 32
Table 3−2: Control Regi ter .......................................................................................................32
3.4.1 PROCCLK Frequency Divider ........................................................................................ 32
Table 3−3: Ma ter PROCCCLK Signal Source & Frequency.................................. 33
3.4.2 BIFO Disable..................................................................................................................33
3.4.3 External Clock Enable....................................................................................................... 33
3.4.4 Termination Enable........................................................................................................... 33
3.4.5 Master / Slave.................................................................................................................... 34
3.5 Master Clock Divider......................................................................................................................... 34
Table 3−4: Ma ter Clock Divider ..............................................................................................34
3.6 BIFO Decimation Register................................................................................................................. 35
Table 3−5: Motherboard BIFO Decimation Regi ter ............................................................... 35
3.7 Programmable Gain Amplifier............................................................................................................. 36
Table 3−6: Programmable Gain Amplifier Regi ter.................................................................. 36
3.7.1 Loading the 12−bit Gain Control ord ......................................................................... 36
Table 3−7: Gain Control Word v . Full Scale Input Amplitude ............................ 37
Table 3−8: Sequence for Loading Gain Control Word ............................................ 37

Pentek Model 6210 Operating Manual Page 5
Page
Table of Contents
Rev.: C
Chapter 3: Memory Map and Register Descriptions (continued)
3.8 Data Format / Signal Path Register ...................................................................................................... 38
Table 3−9: Data Format / Signal Path Register ...........................................................................38
3.8.1 Decimate DDR Input b 2 ................................................................................................38
3.8.2 Pack Mode ..........................................................................................................................38
Table 3−10: Out ut Data to Motherboard BIFO − Packing Formats........................ 39
Table 3−11: A/D Out ut Data Coding .........................................................................40
3.8.3 Programmable−Gain Amplifier & Low−Pass Filter B pass .......................................40
3.8.4 DDR B pass........................................................................................................................41
3.9 SYNC Generate Register....................................................................................................................41
3.10 Serial Port 0 Connection Register .......................................................................................................... 42
Table 3−12: Serial Port 0 Connection Register............................................................................42
3.10.1 The Other Processor’s Serial Port 0 Transmit Section ..................................................42
3.10.2 The Other Processor’s DDR .............................................................................................42
3.10.3 The Processor’s Own DDR ...............................................................................................42
3.10.4 Not Connected ...................................................................................................................43
3.11 CIC Gain Adjust Register ..................................................................................................................43
Table 3−13: CIC Gain Adjust Register .........................................................................................43
3.12 Processor Interface the HSP50214 DDR ..........................................................................................43
Table 3−14: DDR Interface Resources ..........................................................................................44
Table 3−15: DDR Read Source Definitions.................................................................................45
Table 3−16: DDR Status Read Register ........................................................................................45
Appendix A: Intersil H P50214B − Programmable Downconverter
Appendix B: Analog Devices AD6640 − 12−Bit, 65 M P IF ampling A/D Converter
Appendix C: Analog Devices AD603 − Variable Gain Amplifier
Appendix D: Linear Technology LTC1451 − 12−bit Rail to Rail DAC

Page 6 Pentek Model 6210 Operating Manual
Page
Table of Contents
Rev.: C
Appendix E: Configuration EEP OM Format
E.1 Introduction ..................................................................................................................................... E−1
Table E−1: VIM ID EEPROM Regi ter ..................................................................................... E−1
E.2 EEPROM Format Example ............................................................................................................ E−1
Table E−2: EEPROM Example (Model 6210 hown) .............................................................. E−2
Appendix F: Application Note
F.1 Introduction ..................................................................................................................................... F−1
Figure F−1: HSP50214 Simplified Block Diagram.................................................................. F−1
F.2 Output Sample Rate and Bandwidth Specifications.................................................................. F−1
F.3 Calculating the Low Pass Bandwidth .......................................................................................... F−2
F.4 Calculating the Output Rate Using the Standard 64 MHz Clock ............................................ F−2
F.5 Calculating the Low Pass Bandwidth Using the Standard 64 MHz Clock............................. F−2
F.6 Additional Information/References............................................................................................. F−3

Pentek Model 6210 Operating Manual Page 7
Rev.: C
Chapter 1: Overview
1.1 General De cription
Pentek’s Model 6210 is a VIM−2 Digital Drop Receiver (DDR) module (devices of this
type are also often referred to as Digital Down Converters, or DDCs), designed to be
attached directly to any of Pentek’s DSP− or RISC−based VIM motherboards, such as
Pentek Models 4290, 4291 and 4292. It forms a complete 2−channel software radio
system including tuning, filtering and demodulation.
Two Model 6210s may be attached to any VIM−compatible processor board to form a
4−channel software radio which utilizes all four processors while occupying only one
VMEbus slot. Alternately, the Model 6210 may be combined with another VIM−2
module to provide additional I/O functions.
1.2 Input Section
Each channel includes an analog front end which employs a wideband input ampli−
fier followed by a programmable gain amplifier. It accommodates wideband analog
inputs between 5 kHz and 80 MHz, at full−scale levels of −20 dBm to +10 dBm. Ana−
log inputs are accepted through front panel SMA connectors.
An anti−aliasing filter removes out−of−band frequency components and can be tai−
lored for specific signal types. The standard factory−supplied lowpass filter has a
cutoff frequency of 25 MHz. The programmable−gain amp and filter may be
bypassed to support undersampling applications.
Option 030 provides a filter cut−off frequency of 30 MHz. Option 102 provides full scale
levels of −30 dBm to 0 dBm. Both option Option 030 and Option 102 may be combined.

Page 8 Pentek Model 6210 Operating Manual
Rev.: C
1.3 A/D Converters
Each channel employs an Analog Devices AD6640 12−bit A/D conve te capable of sampling
ates up to 65 MHz. The A/D sample clock can be de ived f om an inte nal 64 MHz c ystal
oscillato o f om an exte nal efe ence supplied to anothe f ont panel SMA connecto .
Both A/D conve te s ope ate synch onously f om the same sampling clock to suppo t
multi−channel applications (such as di ection finding) whe e phase between channels
must be maintained.
1.4 Digital Drop Receivers
The output of each A/D conve te feeds the Inte sil HSP50214B, which ep esents a
new gene ation of complex digital down conve te s and communication signal p o−
cesso s.
Included in the HSP50214B a e an input nume ically−cont olled local oscillato
(NCO) and mixe to t anslate input signals down to baseband. The mixe is followed
by multistage digital filte s, including a comb filte , half−band filte s and an FIR filte
with p og ammable coefficients. Togethe , they suppo t decimation facto s f om 4 to
16,384, and a maximum output bandwidth of 929 kHz with an 84 dB SFDR at an out−
put sampling ate of 12.24 MHz.
A second p ocessing section consists of a esampling polyphase filte which ope ates
asynch onously, with a second clock signal. The output section includes di ect I and
Q complex outputs, a ha dwa e ca tesian−to−pola conve te , a f equency disc imi−
nato with p og ammable FIR filte , a timing e o signal fo symbol t acking, and
AGC outputs.
A digital multiplexe allows eithe the digital eceive output o the A/D output to be
sent into the ’C6x BI−FIFO, to suppo t di ect, wideband input data captu e. A f ont
panel ibbon cable bus allows multiple 6210s to sha e a common sample clock and
synch onize the phase of the digital eceive s ac oss modules.
1.5 Connection to VIM Motherboard
Both 16−bit pa allel output data po ts (po ts A and B) f om the Model 6210 flow into
the FIFO st uctu es on the VIM mothe boa d. A cont ol path f om each mothe boa d
p ocesso pe mits di ect p og amming of the HSP50214B functions including tuning,
decimation, output fo matting, filte cont ol and filte coefficients.
1) Due to packaging constraints the internal oscillator is not user-replace-
able. If other clock frequencies are required, contact Pentek for custom
oscillators.
(2) he maximum sampling rate can only be achieved using an external
reference signal, unless the internal oscillator is replaced
(Option 020 provides a 65 MHz oscillator)
Note

Pentek Model 6210 Operating Manual Page 9
Rev.: C
1.6 Simplified Block Diagram
Figure 1−1, below, provides a simplified block diagram of the Model 6 10.
Sample Clock
In/Out
Clock
Generator
Synchronization
Interrupts and
Control
Programmable
Gain Amplifier
Low Pass
Filter
AD6640
65 MHz
12−bit A/D
RF In
HSP50214
Digital Down
Converter
µ Proc
A
Out
B
Out
Sync Control Bus
Sync
12
16
(Q)
16
(I)
32
32
VIM Motherboard
Model 6210
Bypass
LPF
64 MHz
Crystal
Oscillator
Programmable
Gain Amplifier
Low Pass
Filter
RF In
HSP50214
Digital Down
Converter
A
Out
B
Out
Sync
12
Bypass
LPF
AD6640
65 MHz
12−bit A/D
32
DDR
Bypass
MUX
DDR
Bypass
MUX
16
(Q)
16
(I)
32
Ser
Out A
C
n
t
r
l
µ Proc
Ser
Out A
C
n
t
r
l
Front
Panel
SYNC/
SERIAL
SP1 SP1
XCVR XCVRBi−FIFO Bi−FIFO
−Rx −Tx
SP0
−Rx −Tx
SP0
'C6x DSP
A or C
'C6x DSP
B or D
Figure 1−1: Model 6210 − Simplified Block Diagram

Page 10 Pentek Model 6210 Operating Manual
Rev.: C
1.7 Specification
The specifications below are typical, at 25°C ambient temperature, with + 5 VDC and ± 12 VDC power
supplies within ± 1 % of nominal, unless otherwise specified.
Input Channel
Quantity: 2
Input Type: Single−ended, non inverting
Input Impedance:
Standard: 50 Ω
Option 101: 650 kΩ
Full Scale Voltage: ± 1.0 Volts
Input Amp/Filter
Quantity: 2 (one per A/D Channel)
Amplifier #1
Type: Fixed gain Burr Brown OPA642
Bandwidth: 80 MHz
Bypass: None
Amplifier #2
Type: Analog Devices AD603* Programmable Gain Amp
controlled by 12−bit D/A (Linear Technology LTC1451†)
Bandwidth: 25 MHz
Bypass: Programmable (includes filter)
Gain (full scale):
Standard: 10 dBm to −20 dBm
Option 102: 0 dBm to −30 dBm
* − Data Sheet included as Appendix C, courtesy of Analog Devices Inc., Norwood, MA.
† − Data Sheet included as Appendix D, courtesy of Linear Technology Corp., Milpitas, CA.
Anti−Alia ing Filter
Type: Fixed frequency low pass − 5 pole Chebyshev
Passband (−3 dB):
Standard: 25 MHz
Option 030: 30 MHz
Passband Flatness: ± 1 dB
Stopband: 80 MHz
Stopband Attenuation: > 60 dB
Bypass: Programmable (includes P. G. Amp)
A/D Converter:
Device: Analog Devices AD6640**
Quantity: 2
Sampling Rate: 6.5 MHz min, 65 MHz max.
Coupling: AC, 5 kHz cut in
Clock Source: Selectable − Onboard crystal oscillator or
front panel external clock.
Re olution: 12 bits
** − Data Sheet included as Appendix B, courtesy of Analog Devices Inc., Norwood, MA.

Pentek Model 6210 Operating Manual Page 11
Rev.: C
1.7 Specification (continued)
Signal Purity
Front End Performance w/ Programmable Amp
Harmonic Distortion: −60 dB
Signal/Noise Ratio (30 MHz) −50 dB
Spur Free Dynamic Range: −65 dB
Crosstalk: −60 dB @ 1 MHz
Front End Performance w/o Programmable Amp
Harmonic Distortion: −70 dB
Signal/Noise Ratio (30 MHz) −60 dB
Spur Free Dynamic Range: −70 dB
Crosstalk: −60 dB @ 1 MHz
Sample Rate Control
Clock Source:
Internal: Onboard crystal oscillator
Standard: 64 MHz
Option 020: 65 MHz
Oprion 021: 53.125 MHz
External: Front Panel Low−Voltage Differential Signal (LVDS)
65 MHz max.
Sample Rate Divider: internal or external source can be divided by
1, 2, 4, 8, or 10 .
Digital Receiver
Device: Intersil HSP50214*
Quantity: 2
Data Source: Associated A/D (A/D 1 to DDR 1, A/D 2 to DDR 2)
Clock Source: Same as associated A/D source.
Bypa : Under software control, each DDR can be bypassed
individually to provide A/D output to the BI−FIFO
interface.
Sync: Provided through VIM motherboard−driven
control register or via front panel connector.
* − Data Sheet included as Appendix A, courtesy of Intersil Corp., Palm Bay, FL.
Front Panel
Analog Input: 2 SMA Connectors (1 per channel)
Sample Clock: Multipin connector (programmable as input or output
− differential LVDS compatible only) and 1 SMA
connector (also LVDS only)
Sync: Multipin connector (programmable as input or
output − differential LVDS compatible only) and
one TTL input
VIM Motherboard Function Provides access to VIM Motherboard XDS connec−
tor and status LEDs
VIM Motherboard Re et: Front panel control

Page 12 Pentek Model 6210 Operating Manual
Rev.: C
1.7 Specification (continued)
Power Requirement : +5 VDC
Min. (idle): 760 mA
Max. (loaded): 2000 mA
+12 VDC
Min. (idle): 750 mA
Max. (loaded): 750 mA
−12 VDC
Min. (idle): 500 mA
Max. (loaded): 500 mA
Dimen ion : VIM−2 Module
Height: 114 mm (4.5−in.)
Depth: 82 mm (3.25−in.)
idth: 20 mm (0.8−in.)

Pentek Model 6210 Operating Manual Page 13
Rev.: C
Chapter 2: Installation and Connections
2.1 In pection
After unpacking the unit, inspect it carefully for possible damage to connectors or
components. If any damage is discovered, please contact Pentek immediately at
(201) 818−5900. Also, please save the original shipping container and packing material
in case reshipment is required.
2.2 Jumper Block
The Model 6210 PC board contains several jumper blocks. Figure 2−1, on the next page,
shows all jumper block locations. Please be aware that all of the jumpers are config−
ured at the factory for proper operation and, with the exception of JB2 (see Section 2.2.1
and Table 2−2, at the bottom of this page) should not be moved. Table 2−1, below, pro−
vides the factory jumper settings for reference, or in case you suspect that they have
been tampered with.
2.2.1 External Clock Function Select Jumper − JB2
Install a jumper between pins 2 and 3 of JB2 to use a signal applied to the front
panel EXT CLK input connector as the source of the sample clock signal for the
A/D converter. To use the EXT CLK input as the reference clock signal for the
DDR, place a jumper between pins 1 & 2 of JB2. For a description of the signals
that can be applied to the EXT CLK input connector, please refer to Section 2.3.1.
Table 2−1: Model 6210 − Factory Jumper Settings
Jumper Bloc Factory Setting
JB1 Pins 1−2
JB2 Pins 2−3
JB3 Jumper ON (pins 1−2)
JB4 Pins 2−3
Table 2−2: Model 6210 − External Cloc
Jumper
Position External Cloc Function
1 − 2 DDR Reference Cloc
2 − 3* A/D Sample Cloc *
* − Factory Default Setting

Page 14 Pentek Model 6210 Operating Manual
Rev.: C
Baseboard Mounting Holes
JB2
Baseboard Mounting Holes
JB4 JB3 JB1




Figure 2−1: Model 6210 PC Board, Showing Jumper Bloc s & Mounting Holes
(a) Component Side
(b) Solder Side

Pentek Model 6210 Operating Manual Page 15
Rev.: C
2.3 Model 6210 Front Panel Feature
The Model 6210’s front panel is shown in Figure 2−2, at the right.
This panel occupies one of the VIM module positions available
on a VIM motherboard’s front panel. If the Model 6210 is the
only mezzanine board installed, the other half of the mother−
board’s panel may be filled with a blank, supplied with the
motherboard. Available on the Model 6210’s front panel are
three SMA connectors, one for each channel’s analog input sig−
nal and a third for an external clock signal. Two indicator LEDs
associated with the 6210’s Sync Bus interface are visible between
the two analog input connectors, and four LED’s associated with
each motherboard processor that can access the module can be
seen through cutouts on the left side of the panel. The panel’s
most prominent feature is the 36−pin Sync Bus − Serial I/O con−
nector, which will be covered in Section 2.4. The other panel
features discussed will all be discussed in the subsections that
begin below.
2.3.1 External Clock Input − EXT CLK
The threaded, coaxial SMA connector nearest the top
of the Model 6210’s front panel is provided for the
application of an external clock signal. This signal can
be used either as the sample clock signal for the 6210’s
A/D converters, or as the reference clock signal for its DDR.
The External Clock Input circuit used on Pentek's Model 6210 is designed to
accept Low−Voltage Differential Signals (LVDS). The impedance presented
by the external clock input is 50 Ω. The applied signal is AC coupled via 0.1 µF
to the + input of an LVDS line receiver. This input is diode−protected to
ground and +3.3 V, and biased at +1.65 V (the − input of the receiver is also
biased at +1.65 V). LVDS devices can typically react to differential input sig−
nal swings as low as 250 mV, or, when used in a single−ended manner (as in
this case), to signal levels as low as 100 mV above, or 20 mV below, the bias
voltage. For most applications, Pentek recommends that the signal applied to
this connector be a square or sine wave, with 2 V p−p amplitude, at frequen−
cies up to 65 MHz. Figure 2−3, at the top of the next page, shows the equiva−
lent circuit for the Model 6210’s EXT CLK input.
2.3.1.1 Duty Cycle Sensitivity
The A/D converter used on the Model 6210 is the AD6640, from
Analog Devices. The graphs presented in the AD6640 Data Sheet (see
Appendix B) indicate that the ADC is relatively insensitive to duty
cycle variations between 40% and 65%. Figure 17 in the AD6640 Data
Sheet shows the SNR and Spurious performance at varying duty
cycles for a 2.2 MHz analog input signal sampled at 65 MHz. Under
these conditions, the performance seems quite good.
EXT
CLK
CH2
IN
Model 6210
S
Y
N
C
S
E
R
I
A
L
CH1
IN
EXT
CLK
T
R
M
M
A
S
3
2
1
0
3
2
1
0
Figure 2−2:
Model 6210 −
Front Panel

Page 16 Pentek Model 6210 Operating Manual
Rev.: C
2.3 Model 6210 Front Panel Feature (continued)
2.3.1 External Clock Input (continued)
2.3.1.1 Duty Cycle Sensitivity (continued)
Our experience with this device under different conditions, how−
ever, has not been quite so favorable. e have found that if the
device is operated at sample rates of 60 MHz or more, with an
input signal that is offset slightly from the sample rate (e. g., sam−
pling a 60.05 MHz signal at a 60 MHz sample rate), significant
conversion errors can occur at the ADC’s output if the duty cycle
varies even marginally from 50%.
Referring to the AD6640’s switching specifications for the
ENCODE input (this is where the sample clock signal is delivered),
we see that the minimum high and low pulse widths at that input
are both 6.5 nsec. Bearing that in mind, consider that a perfect
square wave at 65 MHz has a half−cycle time slightly less than
7.7 nsec. Now bring that perfect square wave into the real world,
where such things as rise and fall time exist, and you can see how
it might become difficult NOT to violate the 6.5 nsec pulse width
specification at the maximum sample rate.
There is a significant amount of signal conditioning and selection
circuitry between the 6210’s EXT CLK input and the AD6640’s
ENCODE input. This tends to cause a small amount of difference
between the duty cycle of the signal you deliver to the front panel
connector and the duty cycle of the signal we deliver to the ADC.
So, even if you know that your EXT CLK input signal has a duty
cycle of 50% + 0.00001%, that’s probably not what the ADC sees.
50 Ω
0.1 F µ
1 k Ω
1 k Ω
50 Ω
+ 3.3 V
+
–
10 k
Ω
10 k Ω
DS90LV032A
EXT CLK
0.1 F µ
To
Clock
Select MUX
Figure 2−3: Model 6210 − External Cloc Input Circuit

Pentek Model 6210 Operating Manual Page 17
Rev.: C
2.3 Model 6210 Front Panel Feature (continued)
2.3.1 External Clock Input (continued)
2.3.1.1 Duty Cycle Sensitivity (continued)
Now that we’ve given you what seems to be some bad news, we’ll
follow with the good news. e have ONLY seen the AD6640’s
duty cycle sensitivity become a problem in the very specific situa−
tion where the sample rate is relatively high (> 60 MHz), AND the
analog input signal’s frequency is very close to the absolute sample
rate or a multiple thereof. In such cases, the apparent output signal
from the A/D is an alias of the difference frequency, and contains a
relatively high number of samples per cycle. The problem is easily
visible in real−time plots of the A/D output, as glitches in the out−
put signal. Should your application require that you operate your
6210 in this manner, we make the following recommendations:
1) DO NOT use the internal oscillator as your clock source, as
there is no way to control the internal clock’s duty cycle.
Instead, apply and select an external clock signal with a
variable duty cycle.
2) Before attempting any serious data acquisition, monitor and
plot the A/D output in real time, and adjust the duty cycle of
the clock input until the glitches disappear.
2.3.2 Analog Input − CH1 IN, CH2 IN
The two threaded, coaxial SMA connectors nearest the bottom of the Model
6210’s front panel are the Analog Input Connectors. The analog inputs are
terminated in 50 9, and directly coupled to the non−inverting inputs of
OPA642 Operational Amplifiers. The maximum input signal swing for linear
operation is ± 1 V (i.e., 2 VP−P). The amplifier’s bandwidth is 80 MHz, but
because the Model 6210’s maximum sample rate is 65 MHz (64 MHz if the
internal crystal oscillator is used as the sample clock), the bandwidth of sig−
nals applied to these inputs should be limited to 32.5 MHz (32 MHz if the
internal crystal oscillator is used as the sample clock), or to one half of the
programmed sample rate, unless your application requires undersampling.
2.3.3 Indicator LED
A total of ten LED’s are visible through the front panel of the Model 6210.
Two of these are associated with the 6210’s Sync Bus interface. These are
located between the Analog Input Connectors, slightly to the right of the cen−
ter of the panel. The other eight are general purpose indicators controlled by
the processors on the VIM motherboard, and are visible through the cutouts at
the left side of the 6210’s front panel. These will all be discussed in the sub−
sections that begin at the top of the next page.

Page 18 Pentek Model 6210 Operating Manual
Rev.: C
2.3 Model 6210 Front Panel Feature (continued)
2.3.3 Indicator LED (continued)
2.3.3.1 Sync Bus Master LED − MAS
The red MAS LED, the leftmost one near the panel’s center, indi−
cates that the Sync Bus master function has been enabled for the
6210 in question. This means that the 6210 on whose panel this
LED is lit will be the one that provides the Sync signals to all other
VIM modules connected to the Sync Bus. Any Sync Bus MUST
have one and only one master, and it should physically be located
at the opposite end of the Sync Cable from the Sync Terminator
(see Section 2.3.3.2, below). This LED will be illuminated when−
ever the D0 bit in the 6210’s Control Register (see Section 3.4) is set
to the logic ‘1’ state. It will be turned off when that bit is cleared to
the logic ‘0’ state.
2.3.3.2 Sync Bus Terminator LED − TRM
The red TRM LED, the rightmost one near the panel’s center, indi−
cates that the Sync Bus Master termination has been enabled for
the 6210 in question. This means that the 6210 on whose panel this
LED is lit will be the one that provides the terminating resistors for
the Sync signals generated by the Sync Bus master. Any Sync Bus
MUST have one and only one terminator, and it should physically
be located at the opposite end of the Sync Cable from the Sync
master (see Section 2.3.3.1, above). This LED will be illuminated
whenever the D1 bit in the 6210’s Control Register (see Section 3.4)
is set to the logic ‘1’ state. It will be turned off when that bit is
cleared to the logic ‘0’ state.
2.3.3.3 Motherboard LEDs − 0, 1, 2 & 3
Visible through cutouts at the left side of the Model 6210’s front
panel are two groups of four LEDs controlled by the processors on
the VIM motherboard. Each group of four LEDs contains one red
LED (labeled 0) and 3 green LEDs (labeled 1, 2 & 3), and they are
under the control of one of the motherboard’s processors.
Depending upon the position in which the VIM module is installed
on the motherboard, the four LEDs nearest the top of the panel are
controlled by either Processor A or Processor C, and the four at the
bottom are controlled by either Processor B or Processor D. For
further details about these indicators, please refer to your VIM
motherboard’s Operating Manual.

Pentek Model 6210 Operating Manual Page 19
Rev.: C
2.4 Sync Bu − Serial I/O Connector
Accessible through each Model 6210’s front panel is a 36−
pin serial connector (3M part #81036−500203, Pentek part
# 354.03610), several pins of which are connected to (and
driven by) the VIM motherboard’s serial ports. The mating
connector is 3M part # 83036−6006 or an equivalent, Pentek
part # 353.03605. Also included on this connector are signals
used for synchronizing multiple units. Table 2−3, at the bottom
of this page, contains the pinouts and description of this con−
nector, whose pin numbering scheme is shown in Figure 2−4, at
the right.
2.4.1 Signal for Synchronizing Multiple Board
The following LVDS (Low−Voltage Differential Sig−
naling) signals make up the sync bus; MCLK, PRCLK,
MSYNC, SYNC1, and SYNC2. The sub−sections that
begin on the page after next describe each of these sig−
nals. Figure 2−5, on the next page, shows a block dia−
gram of the Sync and Clock signal sources.
Up to eight (8) 6210’s can be operated synchronously by cabling these connec−
tors together. Further details about how this is accomplished are provided in
the subsections beginning on the page after next, and in Sections 3.4 and 3.9.
If your application requires more than 8 units synchronized units, Pentek’s
Model 9190 can be used to synchronize up to eighty (80) 6210s.
Table 2−3: Model 6210 − Sync Bus − Serial I/O Pinouts
Pin Signal Pin Signal
1Ground2 MCLK
3MCLK4Ground
5 MSYNC 6 MSYNC
7 SYNC1 8 SYNC1
9 SYNC2 10 SYNC2
11 Ground 12 PRCLK
13 PRCLK 14 Ground
15 TTL−SYNC 16 Ground
17 P0−CLKR1 18 Ground
19 P0−FSR1 20 P0−DR1
21 P0−CLKS1 22 Ground
23 P0−CLKX1 24 Ground
25 P0−FSX1 26 P0−DX1
27 P1−CLKR1 28 Ground
29 P1−FSR1 30 P1−DR1
31 P1−CLKS1 32 Ground
33 P1−CLKX1 34 Ground
35 P1−FSX1 36 P1−DX1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
2
4
6
8
10
12
14
16
18
2
0
2
2
2
4
2
6
2
8
3
0
3
2
3
4
3
6
Figure 2−4:
Model 6210 −
Front Panel
Sync Bus −
Serial I/O
Connector
Pin Numbering

Page 20 Pentek Model 6210 Operating Manual
Rev.: C
2.4 Sync Bus − Serial I/O Connector (continued)
2.4.1 Signals for Synchronizing Multiple Boards (continued)
DDR 1 is controlled by VIM Motherboard Processor A or C, and DDR2 is controlled by
Processor B or D, depending where the VIM mod le is installed on the motherboard.
MCLK
MSYNC
SYNC1
SYNC2
LVDS
Receiver
CLK IN
AD6640
A/D 1
CLK IN
MSYNC In
SYNC1
SYNC2
DDR 2
HSP 50214B
PRCLK
MSYNC Out
SYNC Out
Master / Slave
(Control Reg., D0)
PRCLK
LVDS
Driver
CLK IN
MSYNC In
SYNC1
SYNC2
DDR 1
HSP 50214B
PRCLK
MSYNC Out
SYNC Out
CLK IN
AD6640
A/D 2
Divide
by 2
PRCLK Freq.
(Control Reg., D4)
Clock Select
(Control Reg., D2)
EXT CLK
Input
Divide
by N
˛
Master Clock
Divider Register
(DIV0)
64 MHz
Oscillator
Figure 2−5: Model 6210 − Block Diagram of Clock and Sync Signal Sources
Note