Phytec phyFLEX-i.MX 6 User manual

A product of a PHYTEC Technology Holding company
phyFLEX®-i.MX 6
Hardware Manual
Document No.: L-773e_2
SOM Prod. No.: PFL-A-XL1-xxx
SOM PCB. No.: 1362.1
CB Prod. No.: PBA-B-01
CB PCB. No.: 1364.2, 1364.3
Edition: March 2013
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phyFLEX®-i.MX 6 [PFL-A-XL1-xxx
PHYTEC Messtechnik GmbH 2013 L-773e_2
Copyrighted products are not explicitly indicated in this manual. The absence of
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is not protected. Additionally, registered patents and trademarks are similarly not
expressly indicated in this manual.
The information in this document has been carefully checked and is considered to
be entirely reliable. However, PHYTEC Messtechnik GmbH assumes no
responsibility for any inaccuracies. PHYTEC Messtechnik GmbH neither gives
any guarantee nor accepts any liability whatsoever for consequential damages
resulting from the use of this manual or its associated product. PHYTEC
Messtechnik GmbH reserves the right to alter the information contained herein
without prior notification and accepts no responsibility for any damages that
might result.
Additionally, PHYTEC Messtechnik GmbH offers no guarantee nor accepts any
liability for damages arising from the improper usage or improper installation of
the hardware or software. PHYTEC Messtechnik GmbH further reserves the right
to alter the layout and/or design of the hardware without prior notification and
accepts no liability for doing so.
Copyright 2013 PHYTEC Messtechnik GmbH, D-55129 Mainz.
Rights - including those of translation, reprint, broadcast, photomechanical or
similar reproduction and storage or processing in computer systems, in whole or
in part - are reserved. No reproduction may occur without the express written
consent from PHYTEC Messtechnik GmbH.
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Address: PHYTEC Messtechnik GmbH
Robert-Koch-Str. 39
D-55129 Mainz
GERMANY
PHYTEC America LLC
203 Parfitt Way SW, Suite G100
Bainbridge Island, WA 98110
USA
Ordering
Information:
[phone]
[email protected]
1 [phone]
[e-mail]
Technical
Support:
[phone]
[e-mail]
1 [phone]
[email protected]
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Web Site: http://www.phytec.de
http://www.phytec.eu http://www.phytec.com
2nd Edition March 2013
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Contents
PHYTEC Messtechnik GmbH 2013 L-773e_2 i
List of Figures...............................................................................................ii
List of Tables...............................................................................................iii
Conventions, Abbreviations and Acronyms..............................................v
Preface..........................................................................................................ix
1Introduction.........................................................................................1
1.1 Block Diagram ............................................................................. 4
1.2 phyFLEX-i.MX 6 Component Placement.................................... 5
1.3 Minimum Requirements to operate the phyFLEX-i.MX 6.......... 7
2Pin Description....................................................................................8
3Jumpers..............................................................................................23
4Power..................................................................................................27
4.1 Primary System Power (VDD_5V_IN_R)................................. 27
4.2 Power Management IC (PMIC) (U14)....................................... 28
4.2.1 Power Domains ............................................................. 29
4.3 Supply Voltage for external Logic ............................................. 32
4.4 Control Management IC (CMIC) (U17))................................... 32
5System Configuration and Booting .................................................33
6System Memory.................................................................................38
6.1 DDR3-SDRAM (U2-U9) ........................................................... 38
6.2 NAND Flash Memory (U13) ..................................................... 39
6.3 I²C EEPROM (U10)................................................................... 39
6.3.1 EEPROM Write Protection Control (J3) ...................... 40
6.4 SPI Flash Memory (U25) )......................................................... 40
7SD / MMC Card Interfaces..............................................................41
8Serial Interfaces.................................................................................43
8.1 Universal Asynchronous Interface ............................................. 44
8.2 USB OTG Interface.................................................................... 45
8.3 USB Host Interface .................................................................... 46
8.4 Ethernet Interface ....................................................................... 47
8.4.1 Ethernet PHY (U11)...................................................... 47
8.4.2 Software Reset of the Ethernet Controller .................... 48
8.4.3 MAC Address................................................................ 49
8.5 I2C Interface ............................................................................... 49
8.6 SPI Interface ............................................................................... 50
8.7 I2S Audio Interface (SSI)) .......................................................... 51
8.8 CAN Interface ............................................................................ 52
8.9 SATA Interface .......................................................................... 52
8.10 PCI Express Interface................................................................. 53
8.11 Media Local Bus ........................................................................ 54
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phyFLEX®-i.MX 6 [PFL-A-XL1-xxx
ii PHYTEC Messtechnik GmbH 2013 L-773e_2
9General Purpose I/Os.......................................................................55
10 User LEDs..........................................................................................57
11 Debug Interface (X1, X4) .................................................................58
12 LVDS Display Interface...................................................................62
12.1 LVDS Display Interface pixel mapping .................................... 63
13 High-Definition MultimediaInterface (HDMI)................................65
14 LVDS Camera Interface ..................................................................66
14.1 Signal Configuration (J9 and J31) ............................................. 67
15 Environment Management IC (EMIC) (U19)................................68
16 Technical Specifications...................................................................69
17 Hints for Integrating and Handling the phyFLEX-i.MX 6 .......... 72
17.1 Integrating the phyFLEX-i.MX 6 .............................................. 72
17.2 Handling the phyFLEX-i.MX 6 ................................................. 74
List of Figures
Figure 1: Block Diagram of the phyFLEX-i.MX 6................................... 4
Figure 2: phyFLEX-i.MX 6 Component Placement (top view)................ 5
Figure 3: phyFLEX-i.MX 6 Component Placement (bottom view) ......... 6
Figure 4: Pinout of the phyFLEX-Connector (top view) .......................... 9
Figure 5: Typical Jumper Pad Numbering Scheme ................................ 23
Figure 6: Jumper Locations (top view) ................................................... 24
Figure 7: Jumper Locations (bottom view) ............................................. 25
Figure 8: Powering scheme of phyFLEX- i.MX 6...................................... 31
Figure 9: JTAG Interface at X4 (top view) ............................................. 59
Figure 10: JTAG Interface at X4 (bottom view)....................................... 60
Figure 11: Physical Dimensions (top view) .............................................. 69
Figure 12: Footprint of the phyFLEX-i.MX 6 .......................................... 73
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Contents
PHYTEC Messtechnik GmbH 2013 L-773e_2 iii
List of Tables
Table 1: Signal Types used in this Manual ............................................vii
Table 2: Abbreviations and Acronyms used in this Manual .................viii
Table 3: Pinout of the phyFLEX-fix Connector X1, Row A ................. 11
Table 4: Pinout of the phyFLEX-fix Connector X1, Row B ................. 13
Table 5: Pinout of the phyFLEX-optional Connector X2, Row A ........ 16
Table 6: Pinout of the phyFLEX-optional Connector X2, Row B......... 17
Table 7: Pinout of the phyFLEX-flex Connector X3, Row A ............... 19
Table 8: Pinout of the phyFLEX-flex Connector X3, Row B................ 20
Table 9: Jumper Settings ........................................................................ 26
Table 10: Standard phyFLEX Boot Options ............................................ 34
Table 11: phyFLEX-i.MX 6 specific Boot Options................................. 34
Table 12: Boot Configuration Pins at phyFLEX-flex Connector X3 ..... 35
Table 13: Boot Configuration Signals generated by the CMIC............... 37
Table 14: EEPROM write protection states via J3................................... 40
Table 15: Location of SD/ MMC Card Interface Signals ........................ 41
Table 16: Location of the UART Signals................................................. 44
Table 17: Location of the USB OTG Signals .......................................... 45
Table 18: Location of the USB-Host Signals........................................... 46
Table 19: Location of the Ethernet Signals.............................................. 47
Table 20: I2C Interface Signal Location................................................... 49
Table 21: SPI Interface Signal Location .................................................. 50
Table 22: I2S Interface Signal Location ................................................... 51
Table 23: CAN Interface Signal Location................................................ 52
Table 24: SATA Interface Signal Location.............................................. 52
Table 25: PCIe Interface Signal Location ................................................ 53
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phyFLEX®-i.MX 6 [PFL-A-XL1-xxx
iv PHYTEC Messtechnik GmbH 2013 L-773e_2
Table 26: Media Local Bus Interface Signal Location ............................ 54
Table 27: Location of GPIO Pins............................................................. 55
Table 28: Debug Interface Signal Location at phyFLEX-Connector X1 58
Table 29: JTAG Connector X4 Signal Assignment................................. 61
Table 30: Display Interface Signal Location ........................................... 62
Table 31: Second Display Interface Signal Location at X3..................... 63
Table 32: Pixel Mapping of 18-bit LVDS Display Interface................... 64
Table 33: Pixel Mapping of 24-bit LVDS Display Interface................... 64
Table 34: HDMI Interface Signal Location at X2 ................................... 65
Table 35: Camera Interface Signal Location at X2.................................. 66
Table 36: LVDS Signal Configuration J9 and J31 .................................. 67
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Conventions, Abbreviations and Acronyms
PHYTEC Messtechnik GmbH 2013 L-773e_2 v
Conventions, Abbreviations and Acronyms
This hardware manual describes the PFL-A-XL1 System on Module
in the following referred to as phyFLEX®-i.MX 6. The manual
specifies the phyFLEX®-i.MX 6's design and function. Precise
specifications for the Freescale Semiconductor i.MX 6 micro-
controllers can be found in the enclosed microcontroller Data
Sheet/User's Manual.
Note: We refrain from providing detailed part specific information
within this manual, which can be subject to continuous changes, due
to part maintenance for our products. Please read the paragraph
"Product Change Management and information in this manual on
parts populated on the SOM" within the Preface.
Note: The BSP delivered with the phyFLEX®-i.MX 6 usually includes
drivers and/or software for controlling all components such as
interfaces, memory, etc. Therefore programming close to hardware at
register level is not necessary in most cases. For this reason, this
manual contains no detailed description of the controller's registers, or
information relevant for software development. Please refer to the
i.MX 6 Reference Manual, if such information is needed to connect
customer designed applications.
Conventions
The conventions used in this manual are as follows:
Signals that are preceded by an "n", "/", or “#”character (e.g.:
nRD, /RD, or #RD), or that have a dash on top of the signal name
(e.g.: RD) are designated as active low signals. That is, their active
state is when they are driven low, or are driving low.
A "0" indicates a logic zero or low-level signal, while a "1"
represents a logic one or high-level signal.
The hex-numbers given for addresses of I2C devices always
represent the 7 MSB of the address byte. The correct value of the
LSB which depends on the desired command (read (1), or write
(0)) must be added to get the complete address byte. E.g. given
address in this manual 0x41 => complete address byte = 0x83 to
read from the device and 0x82 to write to the device
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phyFLEX®-i.MX 6 [PFL-A-XL1-xxx
vi PHYTEC Messtechnik GmbH 2013 L-773e_2
Tables which describe jumper settings show the default position in
bold, blue text.
Text in blue italic indicates a hyperlink within, or external to the
document. Click these links to quickly jump to the applicable
URL, part, chapter, table, or figure.
References made to the phyFLEX-Connector always refer to the
high density samtec connector on the undersides of the
phyFLEX-i.MX 6 System on Module.
Types of Signals
Different types of signals are brought out at the phyFLEX-Connector.
The following table lists the abbreviations used to specify the type of a
signal.
Signal Type Description Abbr.
Power Supply voltage input PWR_I
Ref-Voltage Reference voltage output REF_O
Input Digital input I
Output Digital output O
IO Bidirectional input/output I/O
IPU Digital input with pull-up, must only
be connected to GND. (jumper or
open-collector output)
IPU
OC-Bidir PU Open collector input/output with pull
up
OC-BI
OC-Output Open collector output without pull up,
requires an external pull up
OC
5V Input PD 5 V tolerant input with pull down 5V_PD
LVDS Input Differential line pairs 100 Ohm
LVDS level input
LVDS_I
LVDS
Output
Differential line pairs 100 Ohm
LVDS level output
LVDS_O
LVDS IO Differential line pairs 100 Ohm
LVDS level bidirectional input/output
LVDS_I/O
TMDS
Output
Differential line pairs 100 Ohm
TMDS level output
TMDS_O
USB IO Differential line pairs 90 Ohm USB
level bidirectional input/output
USB_I/O
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Conventions, Abbreviations and Acronyms
PHYTEC Messtechnik GmbH 2013 L-773e_2 vii
ETHERNET
Input
Differential line pairs 100 Ohm
Ethernet level input
ETH_I
ETHERNET
Output
Differential line pairs 100 Ohm
Ethernet level onput
ETH_O
ETHERNET
IO
Differential line pairs 100 Ohm
Ethernet level bidirectional
input/output
ETH_I/O
PCIe Input Differential line pairs 100 Ohm PCIe
level input
PCIe_I
PCIe Output Differential line pairs 100 Ohm PCIe
level output
PCIe_O
MLB Output Differential line pairs 100 Ohm Media
local bus output
MLB_O
MLB IO Differential line pairs 100 Ohm Media
local bus bidirectional input/output
MLB_I/O
MIPI CSI-2
Inpu
t
Differential line pairs 100 Ohm MIPI
CSI-2 level inpu
t
CSI-2_I
Table 1: Signal Types used in this Manual
Abbreviations and Acronyms
Many acronyms and abbreviations are used throughout this manual.
Use the table below to navigate unfamiliar terms used in this
document.
Abbreviation Definition
BSP Board Support Package (Software delivered with the
Development Kit including an operating system
(Windows, or Linux) preinstalled on the module and
Development Tools).
CB Carrier Board; used in reference to the phyFLEX
Development Kit Carrier Board.
DFF D flip-flop.
EMB External memory
b
us.
EMI Electromagnetic Interference.
GPI General purpose input.
GPIO General purpose input and output.
GPO General purpose output.
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phyFLEX®-i.MX 6 [PFL-A-XL1-xxx
viii PHYTEC Messtechnik GmbH 2013 L-773e_2
IRAM Internal RAM; the internal static RAM on the
Freescale Semiconductor i.MX 6 microcontroller.
J Solder jumper; these types of jumpers require solder
equipment to remove and place.
JP Solderless jumper; these types of jumpers can be
remove
d
an
d
p
lace
d
b
y hand with no special tools.
PCB Printed circuit board.
PDI PHYTEC Display Interface; defined to connect
PHYTEC display adapter boards, or custom adapters
PEB PHYTEC Extension Board
PMIC Power management IC
PoE Power over Ethernet
POR Power-on reset
RTC Real-time clock.
SMT Surface mount technology.
SOM System on Module; used in reference to the
PFL-A-XL1 /phyFLEX®-i.MX 6 module
Sx User button Sx (e.g. S1, S2, etc.) used in reference to
the available user buttons, or DIP-Switches on the
carrier board.
Sx_y Switch y of DIP-Switch Sx; used in reference to the
DIP-Switch on the carrier board.
Table 2: Abbreviations and Acronyms used in this Manual
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Preface
PHYTEC Messtechnik GmbH 2013 L-773e_2 ix
Preface
As a member of PHYTEC's new phyFLEX®product family the
phyFLEX-i.MX 6 is one of a series of PHYTEC System on Modules
(SOMs) that can be populated with different controllers and, hence,
offers various functions and configurations. PHYTEC supports a
variety of 8-/16- and 32-bit controllers in two ways:
(1) as the basis for Rapid Development Kits which serve as a
reference and evaluation platform
(2) as insert-ready, fully functional phyFLEX®OEM modules,
which can be embedded directly into the user’s peripheral
hardware design.
Implementation of an OEM-able SOM subassembly as the "core" of
your embedded design allows you to focus on hardware peripherals
and firmware without expending resources to "re-invent"
microcontroller circuitry. Furthermore, much of the value of the
phyFLEX®module lies in its layout and test.
PHYTEC's new phyFLEX®product family consists of a series of
extremely compact embedded control engines featuring various
processing performance classes while using the newly developed
phyFLEX®embedded bus standard. The standardized connector
footprint and pin assignment of the phyFLEX®bus makes this new
SOM generation extremely scalable and flexible. This also allows to
use the same carrier board to create different applications depending
on the required processing power. With this new SOM concept it is
possible to design entire embedded product families around vastly
different processor performances while optimizing overall system
cost. In addition, future advances in processor technology are already
considered with this new embedded bus standard making product
upgrades very easy. Another major advantage is the forgone risk of
potential system hardware redesign steps caused by processor or other
critical component discontinuation. Just use one of PHYTEC's other
phyFLEX®SOMs thereby ensuring an extended product life cycle of
your embedded application.
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phyFLEX®-i.MX 6 [PFL-A-XL1-xxx
xPHYTEC Messtechnik GmbH 2013 L-773e_2
Production-ready Board Support Packages (BSPs) and Design
Services for our hardware will further reduce your development time
and risk and allow you to focus on your product expertise. Take
advantage of PHYTEC products to shorten time-to-market, reduce
development costs, and avoid substantial design issues and risks. With
this new innovative full system solution you will be able to bring your
new ideas to market in the most timely and cost-efficient manner.
For more information go to:
http://www.phytec.de/de/leistungen/entwicklungsunterstuetzung.html
or www.phytec.eu/europe/oem-integration/evaluation-start-up.html
Ordering Information
The part numbering of the phyFLEX has the following structure:
PFL-A-xx-xxxxxx.A2
Generation
A = First Generation
B = Second Generation
Product number (consecutive)
Assembly options (depending on model)
Version number
In order to receive product specific information on changes and
updates in the best way also in the future, we recommend to register at
http://www.phytec.de/de/support/registrierung.html or
http://www.phytec.eu/europe/support/registration.html
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Preface
PHYTEC Messtechnik GmbH 2013 L-773e_2 xi
For technical support and additional information concerning your
product, please visit the support section of our web site which
provides product specific information, such as errata sheets,
application notes, FAQs, etc.
http://www.phytec.de/de/support/faq/faq-phyFLEX-i.MX6.html or
http://www.phytec.eu/europe/support/faq/faq-phyFLEX-i.MX6.html
Declaration of Electro Magnetic Conformity of the
PHYTEC phyFLEX®-i.MX 6
PHYTEC System on Module (henceforth products) are designed for
installation in electrical appliances or as dedicated Evaluation Boards
(i.e.: for use as a test and prototype platform for hardware/software
development) in laboratory environments.
Caution:
PHYTEC products lacking protective enclosures are subject to
damage by ESD and, hence, may only be unpacked, handled or
operated in environments in which sufficient precautionary measures
have been taken in respect to ESD-dangers. It is also necessary that
only appropriately trained personnel (such as electricians, technicians
and engineers) handle and/or operate these products. Moreover,
PHYTEC products should not be operated without protection circuitry
if connections to the product's pin header rows are longer than 3 m.
PHYTEC products fulfill the norms of the European Union’s
Directive for Electro Magnetic Conformity only in accordance to the
descriptions and rules of usage indicated in this hardware manual
(particularly in respect to the pin header row connectors, power
connector and serial interface to a host-PC).
Implementation of PHYTEC products into target devices, as well as
user modifications and extensions of PHYTEC products, is subject to
renewed establishment of conformity to, and certification of, Electro
Magnetic Directives. Users should ensure conformance following any
modifications to the products as well as implementation of the
products into target systems.
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phyFLEX®-i.MX 6 [PFL-A-XL1-xxx
xii PHYTEC Messtechnik GmbH 2013 L-773e_2
Product Change Management and information in this manual on
parts populated on the SOM
When buying a PHYTEC SOM, you will, in addition to our HW and
SW offerings, receive a free obsolescence maintenance service for the
HW we provide.
Our PCM (Product Change Management) Team of developers, is
continuously processing, all incoming PCN's (Product Change
Notifications) from vendors and distributors concerning parts which
are being used in our products.
Possible impacts to the functionality of our products, due to changes
of functionality or obsolesce of a certain part, are being evaluated in
order to take the right masseurs in purchasing or within our HW/SW
design.
Our general philosophy here is: We never discontinue a product as
long as there is demand for it.
Therefore we have established a set of methods to fulfill our
philosophy:
Avoiding strategies
Avoid changes by evaluating longlivety of parts during design in
phase.
Ensure availability of equivalent second source parts.
Stay in close contact with part vendors to be aware of roadmap
strategies.
Change management in rare event of an obsolete and non replaceable
part
Ensure long term availability by stocking parts through last time
buy management according to product forecasts.
Offer long term frame contract to customers.
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Preface
PHYTEC Messtechnik GmbH 2013 L-773e_2 xiii
Change management in case of functional changes
Avoid impacts on Product functionality by choosing equivalent
replacement parts.
Avoid impacts on Product functionality by compensating changes
through HW redesign or backward compatible SW maintenance.
Provide early change notifications concerning functional relevant
changes of our Products.
Therefore we refrain from providing detailed part specific
information within this manual, which can be subject to
continuous changes, due to part maintenance for our products.
In order to receive reliable, up to date and detailed information
concerning parts used for our product, please contact our support
team for through the given contact information within this
manual.
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phyFLEX®-i.MX 6 [PFL-A-XL1-xxx
xiv PHYTEC Messtechnik GmbH 2013 L-773e_2
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Introduction
PHYTEC Messtechnik GmbH 2013 L-773e_2 1
1Introduction
The phyFLEX-i.MX 6 belongs to PHYTEC’s phyFLEX System on
Module family. The phyFLEX SOMs represent the continuous
development of PHYTEC System on Module technology. Like its
mini-, micro- and nanoMODUL predecessors, the phyFLEX boards
integrate all core elements of a microcontroller system on a
subminiature board and are designed in a manner that ensures their
easy expansion and embedding in peripheral hardware developments.
PHYTEC's phyFLEX family introduces the newly developed
phyFLEX embedded bus standard. Apart from processor performance,
a large number of embedded solutions require a corresponding number
of standard interfaces. Among these process interfaces are for example
Ethernet, USB, UART, SPI, I2C, PCIe, audio, and display
connectivity. The phyFLEX bus exactly meets this requirement with
the phyFLEX-fix connector. As well the location of the commonly
used interfaces as the mechanical specifications are clearly defined.
Beside this, the phyFLEX concept also considers, that different
controllers have many different interfaces. To take this into account,
the phyFLEX concept allows two more connectors: the phyFLEX-
optional connector, which has optional, but defined interfaces at fixed
positions (e.g. SATA, CAN, camera) and the phyFLEX-flex
connector, which has only fixed Ground signals. All other signals of
the phyFLEX-flex connector are module specific. All interface signals
of PHYTEC's new phyFLEX bus are available on up to three, high-
density pitch (0.5 mm) connectors, allowing the phyFLEXs to be
plugged like a "big chip" into a target application.
As independent research indicates that approximately 70 % of all EMI
(Electro Magnetic Interference) problems stem from insufficient
supply voltage grounding of electronic components in high frequency
environments approximately 20 % of all pin header connectors on the
phyFLEX bus are dedicated to Ground. This improves EMI and EMC
characteristics and makes it easier to design complex applications
meeting EMI and EMC guidelines using phyFLEX boards even in
high noise environments.
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phyFLEX®-i.MX 6 [PFL-A-XL1-xxx
2PHYTEC Messtechnik GmbH 2013 L-773e_2
phyFLEX boards achieve their small size through modern SMD
technology and multi-layer design. In accordance with the complexity
of the module, 0402-packaged SMD components and laser-drilled
microvias are used on the boards, providing phyFLEX users with
access to this cutting edge miniaturization technology for integration
into their own design.
The phyFLEX-i.MX 6 is a subminiature (60 mm x 70 mm) insert-
ready System on Module populated with the Freescale Semiconductor
i.MX 6 microcontroller. Its universal design enables its insertion in a
wide range of embedded applications.
Precise specifications for the controller populating the board can be
found in the applicable controller reference manual or datasheet. The
descriptions in this manual are based on the Freescale Semiconductor
i.MX 6. No description of compatible microcontroller derivative
functions is included, as such functions are not relevant for the basic
functioning of the phyFLEX-i.MX 6.
The phyFLEX-i.MX 6 offers the following features:
Subminiature System on Module (60 mm x 70 mm) achieved
through modern SMD technology
Populated with the Freescale Semiconductor i.MX 6
microcontroller (BGA624 packaging)
Max. 1.2 GHz core clock frequency
Boot from different memory devices (NAND Flash (standard))
phyFLEX bus. Commonly used interfaces such as Ethernet, USB,
UART, SPI, I2C, audio, PCIe, SATA, CAN, display and camera
connectivity (both LVDS) are available at up to three high-density
(0.5 mm) samtec connector, enabling the phyFLEX-i.MX 6 to be
plugged like a "big chip" into target application
Single supply voltage of 5 V
All controller required supplies generated on board
Improved interference safety achieved through multi-layer PCB
technology and dedicated ground pins
1 GB (up to 4 GB) DDR3 SDRAM
1 GB (up to 16 GB) on-board NAND Flash
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Introduction
PHYTEC Messtechnik GmbH 2013 L-773e_2 3
Up to 16 MB on-board serial Flash (bootable)
Up to 4 kB I2C EEPROM
Serial interface with 4 lines (TTL) allowing simple hardware
handshake
High-Speed USB OTG transceiver
High-Speed USB HOST transceiver
10/100/1000 Mbit Ethernet interface
Two I2C interfaces
Two SPI interfaces
PCIe Interface
I2S Interface
CAN interface
Media Local Bus (MLB) interface
4 Channel LVDS (24 Bit) LCD-Interface
HDMI interface
Two LVDS Camera Interface
Two SD/MMC card interfaces
SATA interface
Support of standard 20 pin debug interface through JTAG
connector
Eleven GPIO/IRQ ports (with phyFLEX-flex connector even
more)
Two user programmable LEDs
Power Management IC (PMIC)
Optional Environment Management IC (EMIC) to monitor
voltage, current and temperature, and for fan control
One Wake Up input
Industrial temperature range (-40 °C to +85 °C)
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phyFLEX®-i.MX 6 [PFL-A-XL1-xxx
4PHYTEC Messtechnik GmbH 2013 L-773e_2
1.1 Block Diagram
Figure 1: Block Diagram of the phyFLEX-i.MX 6
i.MX 6
DDR3 (64Bit)
Bank1
DDR3 (64Bit)
Bank2
PMIC
NAND-Flash
SPI-NOR-Flash
phyFLEX-fix (X1)
and
phyFLEX-optional
(X2) Connector
USB_OTG, USB_H1 (both i.MX6 internal PHY)
Display LVDS0 (4 lanes + clock)
HDMI
I2S (1 output lanes, 1 input lane)
Ethernet PHY
RGMII 10/100/1000 MBit Ethernet
PCIe
SAT
A
2 x UART
CAN
2 x SD-Interface (8 bit, 4 bit)
2 x SPI (1 with 4 CS, 1 with 1 CS)
2 x I2C
9 GPIOs
JTAG
phyFLEX-flex (X3)
Connector
Display LVDS1
MLB
CSI 1 parallel Camera, GPIOs
CSI0 Camera parallel LVDS Converter Camera0 LVDS
DISP0 parallel Display Inteface and Address/Databus,
multiplexed with other functions at connector X1 or X2
I2C EEPROM
EMIC
I2C1
Control Signals
Control Signals
(Reset, Wake-up, Bootpins)
LVDS Converter Camera1 LVDSCSI1 Camera parallel
CMIC
FAN control, PM-Bus (I2C)
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