Phytec phyCORE-LPC3180 User manual

phyCORE-LPC3180
HARDWARE MANUAL
EDITION APRIL 2007
A product of a PHYTEC Technology Holding company

phyCORE-LPC3180
©PHYTEC America LLC 2007 L-681e_3
In this manual are descriptions for copyrighted products that are not explicitly
indicated as such. The absence of the trademark (™) and copyright (©) symbols
does not imply that a product is not protected. Additionally, registered patents and
trademarks are similarly not expressly indicated in this manual.
The information in this document has been carefully checked and is believed to be
entirely reliable. However, PHYTEC America LLC assumes no responsibility for any
inaccuracies. PHYTEC America LLC neither gives any guarantee nor accepts any
liability whatsoever for consequential damages resulting from the use of this manual
or its associated product. PHYTEC America LLC reserves the right to alter the
information contained herein without prior notification and accepts no responsibility
for any damages which might result.
Additionally, PHYTEC America LLC offers no guarantee nor accepts any liability for
damages arising from the improper usage or improper installation of the hardware or
software. PHYTEC America LLC further reserves the right to alter the layout and/or
design of the hardware without prior notification and accepts no liability for doing so.
©Copyright 2007 PHYTEC America LLC, Bainbridge Island, WA.
Rights - including those of translation, reprint, broadcast, photomechanical or similar
reproduction and storage or processing in computer systems, in whole or in part - are
reserved. No reproduction may occur without the express written consent from
PHYTEC America LLC.
EUROPE NORTH AMERICA
Address: PHYTEC Technologie Holding AG
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GERMANY
PHYTEC America LLC
203 Parfitt Way SW, Suite G100
Bainbridge Island, WA 98110
USA
Ordering
Information: [phone]
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Support: [phone]
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Web Site: http://www.phytec.de http://www.phytec.com
3rd Edition April 2007

Contents
©PHYTEC America LLC 2007 L-681e_3
Preface ............................................................................................................ 1
1Introduction............................................................................................. 2
1.1 Block Diagram .................................................................................. 4
1.2 View of the phyCORE-LPC3180 ...................................................... 5
2Pin Description....................................................................................... 7
3Jumpers................................................................................................. 17
3.1 J503 MCKO Signal........................................................................ 23
3.2 J504 A/D Positive Supply/Reference Voltage ............................... 23
3.3 A/D Negative Supply/Reference Voltage........................................ 23
4Power Requirements............................................................................ 24
4.1 Real Time Clock and SRAM Battery .............................................. 24
4.1.1 Real Time Clock and SRAM Power Source (J506)............ 25
4.2 Voltage Supervision (U409)............................................................ 25
5System Configuration.......................................................................... 26
5.1 Boot Process .................................................................................. 26
5.2 Boot Modes..................................................................................... 29
6System Memory.................................................................................... 30
6.1 Memory Model................................................................................ 30
6.2 SDR SDRAM (U602, U603) ........................................................... 31
6.3 NAND Flash Memory (U600).......................................................... 31
6.3.1 NAND Flash Write Protection Control (J604)..................... 32
6.4 I²C EEPROM (U601) ...................................................................... 32
6.4.1 Setting the EEPROM Lower Address bits
(J600, J601, J602).............................................................. 33
6.4.2 EEPROM Write Protection Control (J603).......................... 33
7SIBL, U-Boot and Linux....................................................................... 34
8Serial Interfaces.................................................................................... 35
8.1 RS-232 Transceivers (U301, U302)............................................... 35
8.1.1 UART2 Routing Jumpers J300, J301, J302 and J303....... 35
8.2 USB Transceiver (U300)................................................................. 36
9Processor Independent Watchdog (U408)......................................... 37
9.1 Setting the Watchdog Timeout Period (J400)................................. 37
9.2 Interfacing the WDI Watchdog Input (J401) ................................... 38
10 Debug Interface X201........................................................................... 39
11 Technical Specifications ..................................................................... 42
12 Hints for Handling the phyCORE-LPC3180 ....................................... 44

phyCORE-LPC3180
©PHYTEC America LLC 2007 L-681e_3
13 The phyCORE-LPC3180 on the phyCORE-LPC3180 Carrier Board 45
13.1phyCORE-LPC3180 Carrier Board Peripherals ............................. 45
13.1.1 Jumpers on the phyCORE-LPC3180 Carrier Board........... 48
13.2Functional Components on the phyCORE-LPC3180
Carrier Board.................................................................................. 53
13.2.1 Power Supply at X304........................................................ 53
13.2.2 System Reset Button S300 ................................................ 53
13.2.3 Boot Selection using JP306................................................ 53
13.2.4 Accessing UART5 through Socket P300A ......................... 54
13.2.5 Accessing UART2 through Socket P300B ......................... 54
13.2.6 SD Card Interface at Connector X300................................ 55
13.2.7 User Buttons S302 and S303............................................. 56
13.2.8 User LEDs D400, D401, D402, and D403.......................... 56
13.2.9 Accessing the USB through Connectors X301, X302, and
X303.................................................................................... 57
13.2.10 A/D Potentiometer R313................................................. 57
13.2.11 Battery Connector BAT300............................................. 58
13.2.12 Power Connectors X306 and X307................................. 58
13.2.13 Keyboard Connector at X203.......................................... 59
13.2.14 Debug Interface X202..................................................... 60
13.2.15 Pin Assignment Summary of the phyCORE, the
Expansion Bus and the Patch Field.................................... 61
14 Revision History................................................................................... 71
15 Component Placement Diagram......................................................... 72
Appendix A ................................................................................................... 74
Index.............................................................................................................. 75

Contents
©PHYTEC America LLC 2007 L-681e_3
Index of Figures
Figure 1: Block Diagram phyCORE-LPC3180............................................... 4
Figure 2: Top View of the phyCORE-LPC3180 (controller side)................... 5
Figure 3: Bottom View of the phyCORE-LPC3180 (connector side)............. 6
Figure 4: Pinout of the phyCORE-Connector (Top View, with Cross
Section Insert) ................................................................................ 8
Figure 5: Numbering of the Jumper Pads.................................................... 17
Figure 6: Location of the Jumpers (Top View)............................................. 18
Figure 7: Location of the Jumpers (Bottom View) ....................................... 19
Figure 8: Default Jumper Settings on the phyCORE-LPC3180 (Top Side). 21
Figure 9: Default Jumper Settings on the phyCORE-LPC3180
(Bottom Side).....................................................................................
............................................................................................ 22
Figure 10: Small Page SLC NAND Flash Structure ...................................... 27
Figure 11: JTAG Interface X201 (Top View).................................................. 39
Figure 12: JTAG Interface X201 (Bottom View) ............................................ 40
Figure 13: Physical Dimensions .................................................................... 42
Figure 14: Component Locations on the phyCORE-LPC3180 Development
Board............................................................................................ 47
Figure 15: Typical Jumper Pad Numbering Scheme (solderless jumpers)... 48
Figure 16: Location of the Jumpers (View of the Component Side).............. 50
Figure 17: Default Jumper Settings of the phyCORE-LPC3180 Carrier
Board (J300, JP302-304) ............................................................. 51
Figure 18: Default Jumper Settings of the phyCORE-LPC3180 Carrier
Board (JP300-301, JP307-311, JP400-403)................................ 51
Figure 19: Default Jumper Settings of the phyCORE-LPC3180 Carrier
Board (JP305-JP306)................................................................... 52
Figure 20: Supply Voltage Connector Dimensions at X304 .......................... 53
Figure 21: Carrier Board Keyboard Connector X203 .................................... 59
Figure 22: Carrier Board JTAG Connector X202........................................... 60
Figure 23: Pin Assignment Scheme of the Expansion Bus X201.................. 61

phyCORE-LPC3180
©PHYTEC America LLC 2007 L-681e_3
Figure 24: Pin Assignment Scheme of the Patch Field on the Optional
GPIO Expansion Board................................................................ 62
Figure 25: phyCORE-LPC3180 Component Placement, Top View.............. 72
Figure 26: phyCORE-LPC3180 Component Placement, Bottom View......... 73

Contents
©PHYTEC America LLC 2007 L-681e_3
Index of Tables
Table 1: Pinout of the phyCORE-Connector X200....................................... 9
Table 2: Jumper Settings............................................................................ 20
Table 3: J503 MCKO Signal Configuration ................................................ 23
Table 4: J504, A/D Positive Supply/Reference Voltage Selection............. 23
Table 5: VBAT Operating Limits................................................................. 24
Table 6: J506 Real Time Clock and SRAM Power Source........................ 25
Table 7: LPC3180 Memory Map................................................................. 30
Table 8: Valid SDRAM Memory Address Ranges...................................... 31
Table 9: Compatible NAND Flash Devices ................................................ 31
Table 10: J604, EEPROM Write Protection States...................................... 32
Table 11: J600, J601, J602 EEPROM Lower Address Bits ........................ 33
Table 12: J603, EEPROM Write Protection States...................................... 33
Table 13: J300, J301, J302, J303 High Speed Serial Interface
Configuration ................................................................................ 36
Table 14: J400, Processor Independent Watchdog Timeout Period
Configuration ................................................................................ 37
Table 15: J401 First Serial Interface Configuration..................................... 38
Table 16: JTAG Connector X201 Signal Assignment .................................. 41
Table 17: Carrier Board Connectors............................................................. 45
Table 18: Carrier Board Buttons................................................................... 46
Table 19: Carrier Board LEDs...................................................................... 46
Table 20: Carrier Board Potentiometers....................................................... 46
Table 21: phyCORE-LPC3180 Carrier Board Jumper Settings ................... 48
Table 22: P300A BOOT/RESET Signal Operating Limits............................ 54
Table 23: A/D Potentiometer Output Routing Options ................................. 57
Table 24: Keyboard Connector X203 Signal Assignment............................ 59
Table 25: JTAG Connector X202 Signal Assignment .................................. 60

phyCORE-LPC3180
©PHYTEC America LLC 2007 L-681e_3
Table 26: GPI Pin Assignment for the phyCORE-LPC3180 /
Carrier Board / Expansion Board ................................................. 63
Table 27: GPO Pin Assignment for the phyCORE-LPC3180 /
Carrier Board / Expansion Board ................................................. 64
Table 28: GPIO Pin Assignment for the phyCORE-LPC3180 /
Carrier Board / Expansion Board ................................................. 64
Table 29: SPI Pin Assignment for the phyCORE-LPC3180 /
Carrier Board / Expansion Board ................................................. 65
Table 30: SD Card Pin Assignment for the phyCORE-LPC3180 /
Carrier Board / Expansion Board ................................................. 65
Table 31: USB Pin Assignment for the phyCORE-LPC3180 /
Carrier Board / Expansion Board ................................................. 65
Table 32: JTAG/DEBUG Pin Assignment for the phyCORE-LPC3180 /
Carrier Board / Expansion Board ................................................. 66
Table 33: System Pin Assignment for the phyCORE-LPC3180 /
Carrier Board / Expansion Board ................................................. 66
Table 34: A/D Pin Assignment for the phyCORE-LPC3180 /
Carrier Board / Expansion Board ................................................. 67
Table 35: PWM Pin Assignment for the phyCORE-LPC3180 /
Carrier Board / Expansion Board ................................................. 67
Table 36: I²C Pin Assignment for the phyCORE-LPC3180 /
Carrier Board / Expansion Board ................................................. 67
Table 37: UART Pin Assignment for the phyCORE-LPC3180 /
Carrier Board / Expansion Board ................................................. 68
Table 38: Keyboard Pin Assignment for the phyCORE-LPC3180 /
Carrier Board / Expansion Board ................................................. 69
Table 39: Power Pin Assignment for the phyCORE-LPC3180 /
Carrier Board / Expansion Board ................................................. 69
Table 40: Carrier Board Generated Signal Pin Assignment for the
phyCORE-LPC3180 / Carrier Board / Expansion Board.............. 70
Table 41: Unused Pins on the phyCORE-LPC3180 / Carrier Board /
Expansion Board.......................................................................... 70

Preface
PREFACE
This phyCORE-LPC3180 Hardware Manual describes the single board computer’s design and
functions. Precise specifications for the NXP Semiconductors (founded by Philips) LPC3180
microcontrollers can be found in the enclosed microcontroller Data Sheet/User's Manual. If software is
included please also refer to additional documentation for this software.
In this hardware manual and in the attached schematics, low active signals are denoted by a "/"
preceding the signal name (i.e.: /RD). A "0" indicates a logic-zero or low-level signal, while a "1"
represents a logic-one or high-level signal.
Declaration of Electro Magnetic Conformity of the PHYTEC
©PHYTEC America LLC 2007 L-681e_3 1
phyCORE-LPC3180
PHYTEC Single Board Computers (henceforth products) are designed for installation in electrical
appliances or as dedicated Evaluation Boards (i.e.: for use as a test and prototype platform for
hardware/software development) in laboratory environments.
Caution:
PHYTEC products lacking protective enclosures are subject to damage by ESD and, hence, may only
be unpacked, handled or operated in environments in which sufficient precautionary measures have
been taken in respect to ESD-dangers. It is also necessary that only appropriately trained personnel
(such as electricians, technicians and engineers) handle and/or operate these products. Moreover,
PHYTEC products should not be operated without protection circuitry if connections to the product's
pin header rows are longer than 3 m.
PHYTEC products fulfill the norms of the European Union’s Directive for Electro Magnetic Conformity
only in accordance to the descriptions and rules of usage indicated in this hardware manual
(particularly in respect to the pin header row connectors, power connector and serial interface to a
host-PC).
Implementation of PHYTEC products into target devices, as well as user modifications and extensions
of PHYTEC products, is subject to renewed establishment of conformity to, and certification of,
Electro Magnetic Directives. Users should ensure conformance following any modifications to the
products as well as implementation of the products into target systems.
The phyCORE-LPC3180 is one of a series of PHYTEC Single Board Computers that can be
populated with different controllers and, hence, offers various functions and configurations. PHYTEC
supports a variety of 8-/16- and 32-bit controllers in two ways:
(1) as the basis for Rapid Development Kits which serve as a reference and evaluation platform
(2) as insert-ready, fully functional phyCORE OEM modules, which can be embedded directly into
the user’s peripheral hardware, design.
PHYTEC's microcontroller modules allow engineers to shorten development horizons, reduce design
costs and speed project concepts from design to market. For more information go to:
http://www.phytec.com/services/phytec-advantage.html

phyCORE-LPC3180
2©PHYTEC America LLC 2007 L-681e_3
1INTRODUCTION
The phyCORE-LPC3180 belongs to PHYTEC’s phyCORE Single Board Computer module family.
The phyCORE SBCs represent the continuous development of PHYTEC Single Board Computer
technology. Like its mini-, micro- and nanoMODUL predecessors, the phyCORE boards integrate all
core elements of a microcontroller system on a subminiature board and are designed in a manner
that ensures their easy expansion and embedding in peripheral hardware developments.
As independent research indicates that approximately 70 % of all EMI (Electro Magnetic Interference)
problems stem from insufficient supply voltage grounding of electronic components in high frequency
environments the phyCORE board design features an increased pin package. The increased pin
package allows dedication of approximately 20 % of all pin header connectors on the phyCORE
boards to Ground. This improves EMI and EMC characteristics and makes it easier to design complex
applications meeting EMI and EMC guidelines using phyCORE boards even in high noise
environments.
phyCORE boards achieve their small size through modern SMD technology and multi-layer design. In
accordance with the complexity of the module, 0402-packaged SMD components and laser-drilled
Microvias are used on the boards, providing phyCORE users with access to this cutting edge
miniaturization technology for integration into their own design.
The phyCORE-LPC3180 is a subminiature (60 x 53 mm) insert-ready Single Board Computer
populated with the NXP Semiconductors (founded by Philips) LPC3180 microcontroller. Its universal
design enables its insertion in a wide range of embedded applications. All controller signals and ports
extend from the controller to high-density pitch (0.635 mm) connectors aligning two sides of the
board, allowing it to be plugged like a "big chip" into a target application.
Precise specifications for the controller populating the board can be found in the applicable controller
User’s Manual or datasheet. The descriptions in this manual are based on the NXP Semiconductors
(founded by Philips) LPC3180. No description of compatible microcontroller derivative functions is
included, as such functions are not relevant for the basic functioning of the phyCORE-LPC3180.

Introduction
©PHYTEC America LLC 2007 L-681e_3 3
The phyCORE-LPC3180 offers the following features:
•Subminiature Single Board Computer (60 x 53 mm) achieved through modern SMD technology
•Populated with the NXP Semiconductors LPC3180 microcontroller (LFBGA320 packaging)
•Improved interference safety achieved through multi-layer PCB technology and dedicated ground
pins
•Controller signals and ports extend to two 100-pin high-density (0.635 mm) Molex connectors
aligning two sides of the board, enabling it to be plugged like a "big chip" into target application
•max. 208 MHz core clock frequency
•32 MByte (up to 128 MByte) on-board NAND Flash1
•32 MByte (up to 64 MByte) SDRAM on-board, max @ 104MHz
•RS-232 transceivers supporting three UARTs at data rates of up to 460kbps
•1 to 32KB I2C EEPROM
•Battery buffered controller based RTC & SRAM with automatic battery switchover
•USB OTG transceiver for OTG/Embedded Host/Device functionality
•Processor independent watchdog with disable, normal, or extended modes
•One operating voltage for core & peripherals, 3.0V, typ. < 160 mA (with maximum circuitry
installed at 208 MHz CPU frequency)
•Controller required 0.9V, 1.2V, and 1.8V supplies generated on board
•Support of ETM9 and EmbeddedICE-RT debug interface through JTAG connector
•Keyboard support for up to 64 keys in an 8 * 8 matrix
•Two SPI interfaces with DMA
•Two PWM output channels with programmable duty cycle in 255 steps
•Two I2C interfaces (1.8V & 3.0V)
•SD card interface with DMA
•One high speed capture port
•Dedicated GPI, GPO, and GPIO pins at 1.8V and 3.0V
1: Please contact PHYTEC for more information about additional module configurations.

phyCORE-LPC3180
1.1 BLOCK DIAGRAM
SDRAM
RS232
TRANS.
USB
ATX
RAM_D0..31
RAM_A0..14
NAND
FLASH
FLASH_I/O_0..7
U2_RX/TX
U3_RX/TX
U5_RX/TX
USB
JTAG
CONNECTOR
phyCORE-connector
JTAG
VDD_CORE
VDD_RTC
DC-DC
REGULATORS
SUPERVISOR
1.8V
1.2V
ADJ. 0.9V-1.2V
BATTERY
CTRL & REG.
1.2V
VCC = 3.0V
VBAT
LPC3180
32KB
EEPROM
WATCHDOG
I²C
/RESET
/RESET IN
RESET
GPO WDI
KEYBOARD
PWM
SPI
SD Card
A/D
GPIO/GPI/GPO
POWER
KEYBOARD
PWM
SPI
SD Card
A/D
GPIO/GPI/GPO
Figure 1: Block Diagram phyCORE-LPC3180
4©PHYTEC America LLC 2007 L-681e_3

Introduction
1.2 VIEW OF THE PHYCORE-LPC3180
Figure 2: Top View of the phyCORE-LPC3180 (controller side)
©PHYTEC America LLC 2007 L-681e_3 5

phyCORE-LPC3180
Figure 3: Bottom View of the phyCORE-LPC3180 (connector side)
6©PHYTEC America LLC 2007 L-681e_3

Pin Description
©PHYTEC America LLC 2007 L-681e_3 7
2PIN DESCRIPTION
Please note that all module connections are not to exceed their expressed maximum voltage or
current. Maximum signal input values are indicated in the corresponding controller manuals/data
sheets. As damage from improper connections varies according to use and application, it is the user's
responsibility to take appropriate safety measures to ensure that the module connections are
protected from overloading through connected peripherals.
As Figure 4 indicates, all controller signals extend to surface mount technology (SMT) connectors
(0.635 mm) lining two sides of the module (referred to as phyCORE-connector). This allows the
phyCORE-LPC3180 to be plugged into any target application like a "big chip".
A new numbering scheme for the pins on the phyCORE-connector has been introduced with the
phyCORE specifications. This enables quick and easy identification of desired pins and minimizes
errors when matching pins on the phyCORE module with the phyCORE-connector on the appropriate
PHYTEC Carrier Board or in user target circuitry.
The numbering scheme for the phyCORE-connector is based on a two dimensional matrix in which
column positions are identified by a letter and row position by a number. Pin 1A, for example, is
always located in the upper left hand corner of the matrix. The pin numbering values increase moving
down on the board. Lettering of the pin connector rows progresses alphabetically from left to right
(refer to Figure 4).
The numbered matrix can be aligned with the phyCORE-LPC3180 (viewed from above; phyCORE-
connector pointing down) or with the socket of the corresponding phyCORE Carrier Board/user target
circuitry. The upper left-hand corner of the numbered matrix (pin 1A) is thus covered with the corner
of the phyCORE-LPC3180 marked with a white triangle. The numbering scheme is always in relation
to the PCB as viewed from above, even if all connector contacts extend to the bottom of the module.
The numbering scheme is thus consistent for both the module’s phyCORE-connector as well as
mating connectors on the phyCORE Carrier Board or target hardware, thereby considerably reducing
the risk of pin identification errors.
Since the pins are exactly defined according to the numbered matrix previously described, the
phyCORE-connector is usually assigned a single designator for its position (X1 for example). In this
manner the phyCORE-connector comprises a single, logical unit regardless of the fact that it could
consist of more than one physical socketed connector. The location of row 1 on the board is marked
by a white triangle on the PCB to allow easy identification.
The following figure (Figure 4) illustrates the numbered matrix system. It shows a phyCORE-LPC3180
with SMT phyCORE-connectors on its underside (defined as dotted lines) mounted on a Carrier
Board. In order to facilitate understanding of the pin assignment scheme, the diagram presents a
cross-view of the phyCORE module showing these phyCORE-connectors mounted on the underside
of the module’s PCB.

phyCORE-LPC3180
Figure 4: Pinout of the phyCORE-Connector (Top View, with Cross Section
Insert)
Table 1 provides an overview of the pinout of the phyCORE-connector, as well as descriptions of
possible alternative functions. Table 1 also provides the appropriate signal level interface voltages
listed in the SL (Signal Level) column. The NXP Semiconductors (founded by Philips) LPC3180 is a
multi-voltage operated microcontroller and as such special attention should be paid to the interface
voltage levels to avoid unintentional damage to the microcontroller and other on-board components.
Please refer to the NXP Semiconductors phyCORE-LPC3180 User’s Manual/Data Sheet for details
on the functions and features of controller signals and port pins.
8©PHYTEC America LLC 2007 L-681e_3

Pin Description
©PHYTEC America LLC 2007 L-681e_3 9
NOTE: SL is short for Signal Level (V) and is the applicable logic level to interface a given
pin. Those pins marked as “N/A” have a range of applicable values that constitute proper
operation.
Table 1: Pinout of the phyCORE-Connector X200
PIN ROW X200A
PIN # SIGNAL I/O SL DESCRIPTION
1A Not Connected - - Unused
2A GND - 0 Ground 0V
3A KEY_COL2 I 3.0 Keyboard column 2 scan input pin of the µC
4A KEY_COL3 I 3.0 Keyboard column 3 scan input pin of the µC
5A KEY_COL4 I 3.0 Keyboard column 4 scan input pin of the µC
6A GPI_8/KEY_COL6/
SPI2_BUSY I 3.0
General purpose input 8 of the µC / keyboard column
scan 6 input / SPI 2 busy input pin of the µC
7A GND - 0 Ground 0V
8A KEY_ROW2 O 3.0 Keyboard row 2 scan output pin of the µC
9A KEY_ROW3 O 3.0 Keyboard row 3 scan output pin of the µC
10A KEY_ROW4 O 3.0 Keyboard row 4 scan output pin of the µC
11A GPIO_2/KEY_ROW6 I/O 3.0
General purpose I/O 2 of the µC / keyboard row 6
scan output pin of the µC
12A GND - 0 Ground 0V
13A GPI_3 I 1.8 General purpose input 3 pin of the µC
14A GPI_5 I 3.0 General purpose input 5 pin of the µC
15A GPI_6/
HSTIM_CAPTURE I 3.0
General purpose input 6 / high-speed timer capture
input pin of the µC
16A GPI_11 I 3.0 General purpose input 11 pin of the µC
17A GND - 0 Ground 0V
18A GPI_4/SPI1_BUSY I 3.0
General purpose input 4 of the µC / SPI 1 busy input
of the µC
19A SPI2_DATIN I 3.0 SPI 2 data input pin of the µC
20A SPI2_CLK I/O 3.0 SPI 2 clock pin of the µC
21A MS_SCLK I/O 3.0 SD card serial clock pin of the µC
22A GND - 0 Ground 0V
23A MS_DIO2 I/O 3.0 SD card data I/O 2 pin of the µC
24A MS_DIO3 I/O 3.0 SD card data I/O 3 pin of the µC
25A USB_VBUS I/O 5.0 VBUS I/O pin of the ISP1301 USB transceiver
26A USB_ID I/O N/A ID I/O pin of the ISP1301 USB transceiver
27A GND - 0 Ground 0V
28A USB_DAT_VP/U5_RX I/O 1.8 USB TX data / D- receive pin of the µC
29A /USB_OE_TP I/O 1.8 USB transmit enable for DAT / SE0 pin of the µC
30A USB_I2C_SDA I/O 1.8 I2C SDA pin of the µC for ISP1301 USB transceiver
31A TST_CLK2 O 3.0 Test clock output pin of the µC

phyCORE-LPC3180
10 ©PHYTEC America LLC 2007 L-681e_3
32A GND - 0 Ground 0V
33A HIGHCORE O 3.0 Core voltage select pin of the µC
34A TDO O 3.0 JTAG TDO pin of the µC
35A TCK I 3.0 JTAG TCK pin of the µC
36A TDI I 3.0 JTAG TDI pin of the µC
37A GND - 0 Ground 0V
38A Not connected - - Unused
39A Not connected - - Unused
40A Not connected - - Unused
41A Not connected - - Unused
42A GND - 0 Ground 0V
43A Not connected - - Unused
44A Not connected - - Unused
45A Not connected - - Unused
46A Not connected - - Unused
47A GND - 0 Ground 0V
48A Not connected - - Unused
49A Not connected - - Unused
50A Not connected - - Unused

Pin Description
©PHYTEC America LLC 2007 L-681e_3 11
Pin Row X200B
PIN # SIGNAL I/O SL DESCRIPTION
1B MCKO O 1.2 System clock output signal
2B KEY_COL0 I 3.0 Keyboard column 0 scan input pin of the µC
3B KEY_COL1 I 3.0 Keyboard column 1 scan input pin of the µC
4B GND - 0 Ground 0V
5B KEY_COL5 I 3.0 Keyboard column 5 scan input pin of the µC
6B GPI_9/KEY_COL7 I 3.0
General purpose input 9 / keyboard column 7 scan
input pin of the µC
7B KEY_ROW0 O 3.0 Keyboard row 0 scan output pin of the µC
8B KEY_ROW1 O 3.0 Keyboard row 1 scan output pin of the µC
9B GND 0 Ground 0V
10B KEY_ROW5 O 3.0 Keyboard row 5 scan output pin of the µC
11B GPIO_3/KEY_ROW7 I/O 0 General purpose I/O 3 / keyboard row 7 scan output
pin of the µC
12B GPI_0 I 3.0 General purpose input pin 0 of the µC
13B GPI_2 I 3.0 General purpose input pin 2 of the µC
14B GND - 0 Ground 0V
15B GPI_7 I 3.0 General purpose input pin 7 of the µC
16B SPI1_CLK O 3.0 SPI 1 clock pin of the µC
17B SPI1_DATIN I 3.0 SPI 1 data input pin of the µC
18B SPI1_DATIO I/O 3.0 SPI 1 data input/output pin of the µC
19B GND - 0 Ground 0V
20B SPI2_DATIO I/O 3.0 SPI 2 data input/output of the µC
21B MS_BS I/O 3.0 SD card serial bus state pin of the µC
22B MS_DIO0 I/O 3.0 SD card data I/O 0 pin of the µC
23B MS_DIO1 I/O 3.0 SD card data I/O 1 pin of the µC
24B GND - 0 Ground 0V
25B USB_D- I/O N/A USB D- pin of the ISP1301 USB transceiver
26B USB_D+ I/O N/A USB D+ pin of the ISP1301 USB transceiver
27B USB_SE0_VM/U5_TX I/O 1.8 Single ended zero transmit/D- receive pin of the µC
28B /USB_ATX_INT I 1.8 Interrupt line of the µC for ISP1301 USB transceiver
29B GND - 0 Ground 0V
30B USB_I2C_SCL I/O 1.8 I2C SCL pin of the µC for ISP1301 USB transceiver
31B ONSW O 1.2 VCCon output pin of the µC
32B TEST O 3.0 TEST pin of the µC
33B SYSCLKEN I/O 3.0 SYSCLKEN pin of the µC
34B GND - 0 Ground 0V
35B RTCK O 3.0 JTAG RTCK pin of the µC
36B TMS I 3.0 JTAG TMS pin of the µC
37B /TRST I 3.0 JTAG /TRST pin of the µC
38B Not connected - - Unused

phyCORE-LPC3180
12 ©PHYTEC America LLC 2007 L-681e_3
39B GND - 0 Ground 0V
40B Not connected - - Unused
41B Not connected - - Unused
42B Not connected - - Unused
43B Not connected - - Unused
44B GND - 0 Ground 0V
45B Not connected - - Unused
46B Not connected - - Unused
47B Not connected - - Unused
48B USB_ADR/PSW I/O 1.8 ADR/PSW pin of the ISP1301 USB transceiver
49B GND - 0 Ground 0V
50B Not connected - - Reserved for future use, do not connect.