Phytec ATOM phyCORE-Z500P(T) User manual

A product of a PHYTEC Technology Holding company
phyCORE-Z500P(T)
ATOM®
HARDWARE MANUAL
EDITION JULY 2009

phyCORE-Z500P(T)
©PHYTEC Messtechnik GmbH 2009 L-732e_0
In this manual are descriptions for copyrighted products that are not explicitly indicated
as such. The absence of the trademark (™) and copyright (©) symbols does not imply
that a product is not protected. Additionally, registered patents and trademarks are
similarly not expressly indicated in this manual.
The information in this document has been carefully checked and is believed to be
entirely reliable. However, PHYTEC Messtechnik GmbH assumes no responsibility for
any inaccuracies. PHYTEC Messtechnik GmbH neither gives any guarantee nor accepts
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or its associated product. PHYTEC Messtechnik GmbH reserves the right to alter the
information contained herein without prior notification and accepts no responsibility for
any damages which might result.
Additionally, PHYTEC Messtechnik GmbH offers no guarantee nor accepts any liability
for damages arising from the improper usage or improper installation of the hardware or
software. PHYTEC Messtechnik GmbH further reserves the right to alter the layout
and/or design of the hardware without prior notification and accepts no liability for doing
so.
©Copyright 2009 PHYTEC Messtechnik GmbH, D-55129 Mainz.
Rights - including those of translation, reprint, broadcast, photomechanical or similar
reproduction and storage or processing in computer systems, in whole or in part - are
reserved. No reproduction may occur without the express written consent from PHYTEC
Messtechnik GmbH.
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Address: PHYTEC Technologie Holding AG
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GERMANY
PHYTEC America LLC
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Bainbridge Island, WA 98110
USA
Ordering
Information: [phone]
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Support: [phone]
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Fax: [phone] [phone]
Web Site: http://www.phytec.de http://www.phytec.com
Preliminary Edition July 2009

Contents
©PHYTEC Messtechnik GmbH 2009 L-732e_0
1Preface.....................................................................................................1
1.1 Introduction.......................................................................................2
1.2 Block Diagram..................................................................................4
1.3 View of the phyCORE-Z500PT.........................................................5
2Pin Description (X2) ...............................................................................7
3Jumpers.................................................................................................15
4Power Requirements............................................................................19
5CPU Intel® Z5xx (U1)...........................................................................20
6SCH US15WP(T) (U2)............................................................................21
6.1 LPC Bus..........................................................................................21
6.2 LVDS Interface...............................................................................22
6.3 SDIO/MMC Interface......................................................................23
6.4 SDVO..............................................................................................24
6.5 PCIe................................................................................................25
6.5.1 Ethernet Controller Intel® 82574I (U16)............................26
6.6 USB ................................................................................................27
6.7 PATA/IDE .......................................................................................28
6.7.1 Solid State Disk SSD (U4,U5,U6,U7).................................29
6.7.2 SATA-II Bridge 88SA8052 (U19).......................................29
6.8 Intel® High Definition Audio (Intel® HD Audio)..............................30
6.9 GPIOs.............................................................................................31
6.10 JTAG...............................................................................................32
6.11 SMB................................................................................................32
6.11.1 Clock-Generator (U26) .......................................................32
6.11.2 I²C EEPROM (U3) ..............................................................33
6.12 DDR2-SDRAM Interface (U9-12,U8,U14,U13,U15).......................33
7LPC to SPI Bridge / Power-Management (U21)..................................34
7.1 BIOS SPI-Flash (U17)....................................................................34
8Real Time Clock / CMOS Battery ........................................................35
9Technical Specifications .....................................................................37
10 Hints for Handling the phyCORE-Z500PT..........................................39
11 The phyCORE Z500P(T) on the Carrier Board...................................41
11.1 Connectors .....................................................................................41
11.2 Jumpers on the Baseboard PCM-966............................................45
11.3 Functional Components on the phyCORE-Z500P(T)
Carrier Board..................................................................................48
11.3.1 Module Connector (X1).......................................................49
11.3.2 Power Supply (X37) / ATX-Power ......................................49
11.4 USB ................................................................................................51
11.4.1 USB-Host connector (X27).................................................51
11.4.2 USB-Host/Client (X26)........................................................52

phyCORE-Z500P(T)
©PHYTEC Messtechnik GmbH 2009 L-732e_0
11.4.3 USB-Pin Header X5............................................................53
11.5 UMTS (U11) ...................................................................................54
11.6 GPS (U8)........................................................................................56
11.7 RS-232 Pin header (X14)...............................................................57
11.8 One-Wire Interface (X30) ...............................................................58
11.9 Bluetooth Interface (U19) ...............................................................59
11.10 Touch connector X21..........................................................60
11.11 RS-232 Interface (X23).......................................................62
11.12 LPT Printer Interface (X22).................................................63
11.13 PS/2 Mouse/Keyboard interface (X24)...............................64
11.14 DVI-I Video interface (X25).................................................65
11.15 Ethernet Interface (X27) .....................................................67
11.16 Audio connector (X28)........................................................68
11.17 Front-Panel Pin header (X15).............................................69
11.18 Audio-Signal Pin header (X19)...........................................70
11.19 CD-Audio-connector (X20) .................................................71
11.20 SATA-connector (X9)..........................................................72
11.21 Universal LVDS Display pinheader (X29)...........................73
11.22 Secure Digital / Multi-Media Card (X31/X32)......................74
11.23 FPGA JTAG-pin header (X10)............................................76
11.24 HSMA JTAG-pin header (X11)...........................................77
11.25 Baseboard PLD JTAG-pin header (X12)............................78
11.26 PCIe-Switch JTAG-Port (X4)..............................................79
11.27 Z500P(T) JTAG/XDP-Port (X34) ........................................80
11.28 US15WP(T) JTAG-Port (X35).............................................81
11.29 phyCORE PLD JTAG-pin header (X36) .............................82
11.30 HSMC connector (X33).......................................................83
11.31 PCIe at the phyCORE-Z500P(T) Baseboard......................87
11.32 PCIe mini Card Connector X8 ............................................89
11.33 Post Code Display / Debug-Port 0x80,0x81.......................91
11.34 Push Buttons and LEDs......................................................92
11.35 Address-Map / USB-Tree ...................................................94
11.36 Baseboard Physical Dimension..........................................95
12 Revision History...................................................................................97
13 Component Placement Diagram.........................................................99
Index............................................................................................................101

Contents
©PHYTEC Messtechnik GmbH 2009 L-732e_0
Index of Figures
Figure 1: Block Diagram phyCORE-Z500PT...................................4
Figure 2: Top View of the phyCORE-Z500PT (controller side)........5
Figure 3: Bottom View of the phyCORE-Z500PT
(connector side)................................................................6
Figure 4: Numbering of the Jumper Pads......................................15
Figure 5: Location of the Jumpers (Top View)...............................16
Figure 6: Location of the Jumpers (Bottom View)..........................17
Figure 7: Physical Dimensions ......................................................37
Figure 8: Carrier Board connector location top side......................43
Figure 9: Carrier Board connector location bottom side................44
Figure 10: Typical jumper numbering scheme.................................45
Figure 11: Carrier Board jumper location.........................................46
Figure 12: Top view of the phyCORE-Z500P(T) Carrier Board.......48
Figure 13: Power Supply (X37)........................................................49
Figure 14: Power adapter ................................................................50
Figure 15: USB-Host connector Port-0/1.........................................51
Figure 16: USB-OTG (X26)..............................................................52
Figure 17: USB-Pin Header X5........................................................53
Figure 18: UMTS (U11)....................................................................55
Figure 19: GPS (U8)........................................................................56
Figure 20: RS232 Pin Header X14..................................................57
Figure 21: One-Wire connector X30................................................59
Figure 22: Bluetooth module (U19)..................................................60
Figure 23: Touch connector X21 .....................................................61
Figure 24: RS232 Interface X23......................................................62
Figure 25: LPT Printer Interface X22...............................................63
Figure 26: PS/2 Mouse and Keyboard interface (X24)....................64
Figure 27: DVI-I connector X25.......................................................66

phyCORE-Z500P(T)
©PHYTEC Messtechnik GmbH 2009 L-732e_0
Figure 28: Ethernet Interface X27....................................................67
Figure 29: Audio connector X28......................................................68
Figure 30: Front Panel Pin Header X15...........................................69
Figure 31: Audio Signal Pin Header X19.........................................70
Figure 32: CD-Audio connector X20................................................71
Figure 33: SATA connector X9........................................................72
Figure 34: Universal LVDS Display pin header X29........................73
Figure 35: Secure Digital / Multi Media Card connector X30/X31...75
Figure 36: FPGA JTAG pin header X10..........................................76
Figure 37: HSMA JTAG pin header X11..........................................77
Figure 38: PLD JTAG pin header X12.............................................78
Figure 39: PCIe Switch JTAG-Port (X4)...........................................79
Figure 40: Z500P(T) JTAG/XDP-Port (X34)....................................80
Figure 41: US15WP(T) JTAG-Port (X35) ........................................81
Figure 42: phyCORE PLD JTAG pin header X36............................82
Figure 43: HSMC connector X33.....................................................86
Figure 44: PCIe Slot X6/X7..............................................................88
Figure 45: PCI Express Mini Card connector X8.............................90
Figure 46: Debug Port 0x80/0x81....................................................91
Figure 47: Push Buttons and LEDs .................................................93
Figure 48: Baseboard physical dimensions.....................................95
Figure 49: phyCORE-Z500P(T) Component Placement,
Top View.........................................................................99
Figure 50: phyCORE-Z500P(T) Component Placement,
Bottom View..................................................................100

Contents
©PHYTEC Messtechnik GmbH 2009 L-732e_0
Index of Tables
Table 1: Pinout of the phyCORE-Connector X2.............................8
Table 2: Jumper Settings..............................................................18
Table 3: Power supply..................................................................19
Table 4: LPC-Bus signals.............................................................21
Table 5: LVDS-Signals .................................................................22
Table 6: VBAT Operating Limits...................................................35
Table 7: Carrier Board connectors ...............................................41
Table 8: Carrier Board jumper descriptions..................................47
Table 9: USB Port usage..............................................................51
Table 10: Pinning of X27 ................................................................51
Table 11: Pinning of X26 ................................................................52
Table 12: Pinning of USB-Pin Header X5.......................................53
Table 13: Pinning of RS232-Pin Header X14.................................57
Table 14: One-Wire connector .......................................................58
Table 15: Bluetooth baudrate.........................................................59
Table 16: Touch signals at X21/X29...............................................60
Table 17: RS-232 Interface X23.....................................................62
Table 18: LPT interface (X22) ........................................................63
Table 19: PS/2 Mouse and Keyboard interface (X24)....................64
Table 20: DVI-I connector X25.......................................................66
Table 21: Ethernet interface X27....................................................67
Table 22: Audio connector X28......................................................68
Table 23: Front Panel Pin Header X15...........................................69
Table 24: Audio Signal Pin header X19..........................................70
Table 25: CD-Audio connector X20................................................71
Table 26: SATA connector X9........................................................72
Table 27: Universal LVDS Display pin header X29........................73
Table 28: Secure Digital / Multi-Media-Card X31...........................74

phyCORE-Z500P(T)
©PHYTEC Messtechnik GmbH 2009 L-732e_0
Table 29: Secure Digital / Multi-Media-Card X32...........................74
Table 30: FPGA JTAG pin header (X10)........................................76
Table 31: HSMA JTAG pin header (X11).......................................77
Table 32 PLD JTAG pin header (X12)..........................................78
Table 33: PCIe Switch JTAG-Port (X4)..........................................79
Table 34: Z500P(T) JTAG/XDP-Port (X34)....................................80
Table 35: US15WP(T) JTAG-Port (X35) ........................................81
Table 36: phyCORE PLD JTAG pin header (X36) .........................82
Table 37: HSMC connector X33 Bank 1.........................................83
Table 38: HSMC connector X33 Bank 2.........................................84
Table 39: HSMC connector X33 Bank 3.........................................85
Table 40: PCIe x 1 slot X6..............................................................87
Table 41: PCIe x 1 slot X7..............................................................87
Table 42: miniPCIe slot X8.............................................................89
Table 43: LEDs at the baseboard...................................................92
Table 44: Switches at the baseboard.............................................92
Table 45: I/O-Address Map.............................................................94
Table 46: I²C-Address Map (8-bit)..................................................94
Table 47: USB Port usage..............................................................94

Preface
©PHYTEC Messtechnik GmbH 2009 L-732e_0 1
1Preface
This phyCORE-Z500PT Hardware Manual describes the single board computer’s design and functions.
Precise specifications for the Intel® Z500PT CPU/Chipset can be found in the enclosed microcontroller
Data Sheet/User's Manual. If software is included please also refer to additional documentation for this
software.
In this hardware manual and in the attached schematics, low active signals are denoted by a "/" or “#”
preceding the signal name (i.e.: /RD or #RD). A "0" indicates a logic-zero or low-level signal, while a "1"
represents a logic-one or high-level signal.
Declaration of Electro Magnetic Conformity of the PHYTEC
phyCORE-Z500PT
PHYTEC Single Board Computers (henceforth products) are designed for installation in
electrical appliances or as dedicated Evaluation Boards (i.e.: for use as a test and prototype platform for
hardware/software development) in laboratory environments.
Caution!
PHYTEC products lacking protective enclosures are subject to damage by ESD and, hence, may only be
unpacked, handled or operated in environments in which sufficient precautionary measures have been
taken in respect to ESD-dangers. It is also necessary that only appropriately trained personnel (such as
electricians, technicians and engineers) handle and/or operate these products. Moreover, PHYTEC
products should not be operated without protection circuitry if connections to the product's pin header rows
are longer than 3 m.
PHYTEC products fulfill the norms of the European Union’s Directive for Electro Magnetic Conformity only
in accordance to the descriptions and rules of usage indicated in this hardware manual (particularly in
respect to the pin header row connectors, power connector and serial interface to a host-PC).
Implementation of PHYTEC products into target devices, as well as user modifications and extensions of
PHYTEC products, is subject to renewed establishment of conformity to, and certification of, Electro
Magnetic Directives. Users should ensure conformance following any modifications to the products as well
as implementation of the products into target systems.
The phyCORE-Z500PT is one of a series of PHYTEC Single Board Computers that can be populated with
different controllers and, hence, offers various functions and configurations. PHYTEC supports a variety of
8-/16- and 32-bit controllers in two ways:
(1) as the basis for Rapid Development Kits which serve as a reference and evaluation platform
(2) as insert-ready, fully functional phyCORE OEM modules, which can be embedded directly into the
user’s peripheral hardware, design.
PHYTEC's microcontroller modules allow engineers to shorten development horizons, reduce design costs
and speed project concepts from design to market. For more information go to:
http://www.phytec.com/services/phytec-advantage.html

phyCORE-Z500P(T)
2©PHYTEC Messtechnik GmbH 2009 L-732e_0
1.1 Introduction
The phyCORE-Z500PT belongs to PHYTEC’s phyCORE Single Board Computer module family. The
phyCORE SBCs represent the continuous development of PHYTEC Single Board Computer technology.
Like its mini-, micro- and nanoMODUL predecessors, the phyCORE boards integrate all core elements of a
microcontroller system on a subminiature board and are designed in a manner that ensures their easy
expansion and embedding in peripheral hardware developments.
As independent research indicates that approximately 70 % of all EMI (Electro Magnetic Interference)
problems stem from insufficient supply voltage grounding of electronic components in high frequency
environments the phyCORE board design features an increased pin package. The increased pin package
allows dedication of approximately 20 % of all pin header connectors on the phyCORE boards to Ground.
This improves EMI and EMC characteristics and makes it easier to design complex applications meeting
EMI and EMC guidelines using phyCORE boards even in high noise environments.
phyCORE boards achieve their small size through modern SMD technology and multi-layer design. In
accordance with the complexity of the module, 0402-packaged SMD components and laser-drilled
Microvias are used on the boards, providing phyCORE users with access to this cutting edge
miniaturization technology for integration into their own design.
The phyCORE-Z500PT is a subminiature (85 x 100 mm) insert-ready Single Board Computer populated
with the Intel® Atom Z510P/PT, Z520PT or Z530P CPU. Its universal design enables its insertion in a
wide range of embedded applications. All controller signals and ports extend from the controller to a high-
density pitch (0.5 mm) connector aligning on one side of the board, allowing it to be plugged like a "big
chip" into a target application.
Precise specifications for the controller populating the board can be found in the applicable controller
User’s Manual or datasheet. The descriptions in this manual are based on the Intel® Z500PT. No
description of compatible microcontroller derivative functions is included, as such functions are not relevant
for the basic functioning of the phyCORE-Z500PT.

Introduction
©PHYTEC Messtechnik GmbH 2009 L-732e_0 3
The phyCORE-Z500PT offers the following features:
•Subminiature Single Board Computer (85 x 100 mm) achieved through modern SMD technology
•Improved interference safety achieved through multi-layer PCB technology and dedicated ground
pins
•Controller signals and ports extend to one 2 x 120-pin high-density (0.5 mm) Samtec connector
aligned one side of the board, enabling it to be plugged like a "big chip" into target application
•Populated with the Intel® Atom Z510P/PT, Z520PT or Z530P microprocessor (packaging
437-ball, µFCBGA8 22 x 22 mm)
•System Controller Hub, US15WP/WPT
•DDR2 RAM up to 2GB (Kitversion with 512 MB)
•Solide State Disc (SSD) up to 16GB (Kitversion with 2 GB)
•Intel® 82574 Ethernet controller with 10/100/1000 Mbit/s
•8 x USB2.0 (6 x Low-/Full-/High-Speed, 2 x HighSpeed only)
•microSD slot on board
•SATA interface (Master / Slave)
•2 x PCIexpress lanes (On the baseboard an additional PCIexpress switch is populated offering
access to two PCIe x 1, 1 miniPCIe and an Altera Aria-GX FPGA)
•3 x SDIO port
•LVDS Display interface (18-/ 24-bit)
•SDVO Display interface
•System Management Bus (SMB)
•Low Pin Count Bus (LPC Bus)
•5 Volt Single Supply
•Physical dimensions: 85 x 100 mm
•Temperature Range:
ostandard: 0...+70°C
oextended: -40...+85°C

phyCORE-Z500P(T)
4©PHYTEC Messtechnik GmbH 2009 L-732e_0
1.2 Block Diagram
Figure 1: Block Diagram phyCORE-Z500PT

Introduction
©PHYTEC Messtechnik GmbH 2009 L-732e_0 5
1.3 View of the phyCORE-Z500PT
Figure 2: Top View of the phyCORE-Z500PT (controller side)

phyCORE-Z500P(T)
6©PHYTEC Messtechnik GmbH 2009 L-732e_0
Figure 3: Bottom View of the phyCORE-Z500PT (connector side)

Pin Description
©PHYTEC Messtechnik GmbH 2009 L-732e_0 7
2Pin Description (X2)
Please note that all module connections are not to exceed their expressed maximum voltage or current.
Maximum signal input values are indicated in the corresponding controller manuals/data sheets. As
damage from improper connections varies according to use and application, it is the user's responsibility to
take appropriate safety measures to ensure that the module connections are protected from overloading
through connected peripherals.
As Table 1 indicates, all controller signals extend to surface mount technology (SMT) connectors (0.5 mm)
on one side of the module (referred to as phyCORE-connector). This allows the phyCORE-Z500P(T) to be
plugged into any target application like a "big chip".
The connector used on the phyCORE-Z500P(T) is a QSH-120-01-L-D-A from Samtec.
QSH-120-01-L-D-A
The mating connector, for the baseboard, is
QTH-120-01-L-D-A
Table 1 provides an overview of the pinout of the phyCORE-connector, as well as descriptions of possible
alternative functions. Table 1 also provides the appropriate signal level interface voltages listed in the SL
(Signal Level) column. The Intel® Z500PT is a multi-voltage operated microcontroller and as such special
attention should be paid to the interface voltage levels to avoid unintentional damage to the microcontroller
and other on-board components. Please refer to the Intel® Z500PT User’s Manual/Data Sheet for details
on the functions and features of controller signals and port pins.

phyCORE-Z500P(T)
8 ©PHYTEC Messtechnik GmbH 2009 L-732e_0
NOTE:
SL is short for Signal Level (V) and is the applicable logic level to interface a given pin. Those pins marked
as “N/A” have a range of applicable values that constitute proper operation.
Table 1: Pinout of the phyCORE-Connector X2
Pin Name Description Type
1,3,5,7,9 VCC5VA Main Power Supply Power
11 GND Ground Power
13 HDA_SDI_0
15 HDA_SDI_1
17 #HDA_DOCKEN
19 HDA_DOCKRST
21 HDA_RST
23 FWH_BSEL Bankselect input
for BIOS backup
25 FWH_EN Disable on board FWH Input (PU)
27 #SMI System Managment Interrupt
29 #PM_SLP_S3 S3 control-signal output
31 #PM_SLP_S4 S4 control-signal output
33 #H_INIT
35 SMB_CLK System-Managment-Bus Clock
37 SMB_DATA System-Managment-Bus Data Bidir (PU)
39 CLK_LPC_PORT80 LPC Clock used for Port 80 output
41 GND Ground Power
43 CLK_LPC_FWH LPC Clock for FWH output
45 LPC_FRAME LPC Frame Signal
47 #LPC_CLKRUN LPC....
49 LPC_SERIRQ LPC interrupt line
51 GND Ground Power
53 GPIO_SUS0
55 #PM_PWRBTTN Debounced copy of #SMC_ONOFF output
57 GPIO_0 IO
59 GPIO_2 IO
61 GND Ground Power
63 GPIO_4 IO
65 GPIO_6 IO
67 GPIO_8 IO
69 #H_IERR
71 GND Ground Power
73 MMC_0_LED Activity output MMC0 output
75 #MMC0_CD Card detect MMC0 Input (PU)

Pin Description
©PHYTEC Messtechnik GmbH 2009 L-732e_0 9
77 MMC0_WP Write protect MMC0 input
79 #MMC0_PWR Power enable output MMC0 output
81 GND Ground Power
83 MMC0_CLK Clock MMC0 output
85 MMC0_CMD Command MMC0 bidir
87 MMC0_DATA0 MMC0 dataline 0 bidir
89 MMC0_DATA1 MMC0 dataline 1 bidir
91 GND Ground Power
93 MMC0_DATA2 MMC0 dataline 2 bidir
95 MMC0_DATA3 MMC0 dataline 3 bidir
97 MMC1_LED Activity output MMC1 output
99 #MMC1_CD Card detect MMC1 input
101 GND Ground Power
103 MMC1_WP Write protect MMC1 Input
105 #MMC1_PWR Power enable output MMC1 Output
107 MMC1_CMD Command MMC1 Bidir
109 MMC1_CLK Clock MMC1 Output
111 GND Ground Power
113 MMC1_DATA2 MMC1 dataline 2 Bidir
115 PLD_TDO TDO from PLD Output (PU/3V3)
117 PLD_TDI TDI from PLD Output (PU/3V3)
119 PLD_TCK TCK from PLD Input
121 GND Ground Power
123 PLD_TMS TMS from PLD Input
125 XDP_TRST TRST from CPU Input
127 XDP_TCK_0 TCK from CPU Input
129 #USB_OC_7 Over current USB port 7 Input
131 USB_DP_7 USB Port 7 pos. Dataline Diff. Bidir
133 USB_DN_7 USB Port 7 neg. Dataline Diff bidir
135 #USB_OC_6 Over current USB port 6 Input
137 GND Ground Power
139 USB_DP_6 USB Port 6 pos. Dataline Diff bidir
141 USB_DN_6 USB Port 6 neg. Dataline Diff bidir
143 #USB_OC_3 Over current USB port 3 Input
145 USB_DP_3 USB Port 3 pos. Dataline Diff bidir
147 USB_DN_3 USB Port 3 neg. Dataline Diff bidir
149 GND Ground Power
151 USB_DP_2 USB Port 2 pos. Dataline Diff bidir
153 USB_DN_2 USB Port 2 neg. Dataline Diff bidir
155 #USB_OC_2 Over current USB port 2 input

phyCORE-Z500P(T)
10 ©PHYTEC Messtechnik GmbH 2009 L-732e_0
157 USB_DP_0 USB Port 0 pos. Dataline Diff bidir
159 USB_DN_0 USB Port 0 neg. Dataline Diff bidir
161 GND Ground Power
163 #USB_OC_0 Over current USB port 0 input
165 LA_DATAP_0 LVDS data group 0 pos. signal Diff output
167 LA_DATAM_0 LVDS data group 0 neg. signal Diff output
169 L_DDC_CLK DDC clock Output (PU)
171 LA_DATAP_1 LVDS data group 1 pos. signal Diff output
173 LA_DATAM_1 LVDS data group 1 neg. signal Diff output
175 GND Ground Power
177 LA_DATAP_3 LVDS data group 3 pos. signal Diff output
179 LA_DATAM_3 LVDS data group 3 neg. signal Diff output
181 SMC_SHUTDOWN ... output
183 L_BKLTEN LCD Backlight enable output
185 SDVO_TVCLKIN SDVO TVCLKIN pos. signal
187 #SDVO_TVCLKIN SDVO TVCLKIN neg. signal
189 GND Ground Power
191 SDVO_CTRLCLK SDVO management clock Output (PU)
193 SDVOB_STALL SDVOB STALL pos. signal
195 #SDVOB_STALL SDVOB STALL neg. signal
197 GND Ground Power
199 MDI_PLUS0 Ethernet MDI0 pos. signal Diff bidir
201 MDI_MINUS0 Ethernet MDI0 neg. signal Diff bidir
203 LAN_LED0 Ethernet Activity Led Output (OD)
205 MDI_PLUS1 Ethernet MDI1 pos. signal Diff bidir
207 MDI_MINUS1 Ethernet MDI1 neg. signal Diff bidir
209 GND Ground Power
211 MDI_PLUS2 Ethernet MDI2 pos. signal Diff bidir
213 MDI_MINUS2 Ethernet MDI2 neg. signal Diff bidir
215 LAN_LED1 Ethernet Link Led Output (OD)
217 MDI_PLUS3 Ethernet MDI3 pos. signal Diff bidir
219 MDI_MINUS3 Ethernet MDI3 neg. signal Diff bidir
221 GND Ground Power
223 CLK_PCIE_SLOT0_CON PCIe pos. clock for Slot 0 Diff output
225 #CLK_PCIE_SLOT0_CON PCIe neg. clock for Slot 0 Diff output
227 #PCIE_WAKE Wake Signal input
229 GND Ground Power
231 PCIE_TXP_1_CON First PCIe Transmit pos. Diff output
233 #PCIE_TXN_1_CON First PCIe Transmit neg. Diff output
235 #CLK_SLOT0_OE Output enable for Slot 0 clock Input (PU)

Pin Description
©PHYTEC Messtechnik GmbH 2009 L-732e_0 11
237 PCIE_RXP_1_CON First PCIe receive pos. Diff input
239 PCIE_RXN_1_CON First PCIe receive neg. Diff input
2,4,6,8,10 VCC5VA Main Power Supply Power
12 GND Ground Power
14 VBAT 3V3 Coin-Cell for CMOS Power
16 HDA_CLK
18 HDA_SDO
20 HDA_SYNC
22 HDA_SPKR
24 #SMC_RST Main-Reset Input
26 #SMC_ONOFF Input for Power Button Input (PU)
28 #SMC_RUNTIME_SCI
30 #PM_SYSRST output
32 #PM_THRM
34 #PM_THERMTRIP
36 #H_A20M
38 #SMB_ALERT System-Managment-Bus Alert Input (PU)
40 CLK_LPC_TPM LPC Clock for TPM output
42 GND Ground Power
44 LPC_AD0 LPC Bus Address 0
46 LPC_AD1 LPC Bus Address 1
48 LPC_AD2 LPC Bus Address 2
50 LPC_AD3 LPC Buss Address 3
52 GND Ground Power
54 #L_BKLTSEL_0_GPIO LVDS Backlight select / GPIO
56 SCH_GPIOSUS_3
58 GPIO_1 IO
60 GPIO_3 IO
62 GND Ground Power
64 GPIO_5 IO
66 #SLPIOVR
68 #L_BKLTSEL LVDS Backlight select output
70 #H_IGNNE
72 GND Ground Power
74 MMC_2_LED Activity output MMC2 output
76 #MMC2_CD Card detect MCM2 Input (PU)
78 MMC2_WP Write protect MMC2 input

phyCORE-Z500P(T)
12 ©PHYTEC Messtechnik GmbH 2009 L-732e_0
80 #MMC2_PWR Power enable output MMC2 output
82 GND Ground Power
84 MMC2_CLK Clock MMC2 output
86 MMC2_CMD Command MMC2 bidir
88 MMC2_DATA0 MMC2 dataline 0 Bidir
90 MMC2_DATA1 MMC2 dataline 1 Bidir
92 GND Ground Power
94 MMC2_DATA2 MMC2 dataline 2 Bidir
96 MMC2_DATA3 MMC2 dataline 3 Bidir
98 MMC2_DATA4 MMC2 dataline 4 Bidir
100 MMC2_DATA5 MMC2_dataline 5 Bidir
102 GND Ground Power
104 MMC2_DATA6 MMC2 dataline 6 bidir
106 MMC2_DATA7 MMC2 dataline 7 bidir
108 MMC1_DATA0 MMC1 dataline 0 bidir
110 MMC1_DATA1 MMC1 dataline 1 bidir
112 GND Ground Power
114 MMC1_DATA3 MMC1 dataline 3 bidir
116 SCH_TDO TDO from SCH Output
118 SCH_TDI TDI from SCH input
120 SCH_TCK TCK from SCH input
122 GND Ground Power
124 SCH_TMS TMS from SCH input
126 SCH_TRST TRST from SCH input
128 XDP_TDI TDI from CPU input
130 XDP_TDO TDO from CPU output
132 XDP_TMS TMS from CPU input
134 VCC1V05S (Refernce) JTAG reference voltage for SCH and
CPU output
136 #USB_OC_5 Over current USB port 5 input
138 GND Ground Power
140 USB_DP_5 USB Port 5 pos. Dataline Diff bidir
142 USB_DN_5 USB Port 5 neg. Dataline Diff bidir
144 #USB_OC_4 Over current USB port 4 input
146 USB_DP_4 USB Port 4 pos. Dataline Diff bidir
148 USB_DN_4 USB Port 4 neg. Dataline Diff bidir
150 GND Ground Power
152 USB_DP_1 USB Port 1 pos. Dataline Diff bidir