Phytec L-808e.A4 User manual

A product of PHYTEC Technology Holding Company
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L-808e.A4 phyCORE-i.MX 6 Hardware Manual
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L-808e.A4 phyCORE-i.MX 6 Hardware Manual
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L-808e.A4 phyCORE-i.MX 6 Hardware Manual
Document Title L-808e.A4 phyCORE-i.MX 6 Hardware Manual
Article Number L-808e.A4
Release Date 14.07.2022
SOM Prod. No. PCM-058
SOM PCB No. 1429.3

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1.
2.
1 Preface
As a member of PHYTEC's phyCORE®product family the phyCORE‑i.MX6 is one of a series of PHYTEC System on
Modules (SOMs) that can be populated with different controllers and, hence, offers various functions and
configurations. PHYTEC supports a variety of 8-/16- and 32-bit controllers in two ways:
as the basis for Rapid Development Kits which serve as a reference and evaluation platform
as insert-ready, fully functional phyCORE® OEM modules, which can be embedded directly into the user’s
peripheral hardware design.
Implementation of an OEM-able SOM subassembly as the "core" of your embedded design allows you to focus on
hardware peripherals and firmware without expending resources to "re-invent" microcontroller circuitry.
Furthermore, much of the value of the phyCORE®module lies in its layout and test.
Production-ready Board Support Packages (BSPs) and Design Services for our hardware will further reduce your
development time and risk and allow you to focus on your product expertise. Take advantage of PHYTEC products
to shorten time-to-market, reduce development costs, and avoid substantial design issues and risks. With this new
innovative full system solution, you will be able to bring your new ideas to market in the most timely and cost-
efficient manner.
For more information go to:
http://www.phytec.de/de/leistungen/entwicklungsunterstuetzung.html
or
http://www.phytec.eu/europe/oem-integration/evaluation-start-up.html
1.1 Ordering Information
The part numbering of the phyCORE has the following structure:
Note
Assembly options include a choice of Controller; RAM (Size/Type); Size of NAND Flash, etc.; Interfaces
available; Vanishing; Temperature Range; and other features. Please contact our sales team to get more
information on the ordering options available.
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1.2 Product Specific Information and Technical Support
In order to receive product-specific information on changes and updates in the best way also in the future, we
recommend registering at:
http://www.phytec.de/support/registrierung.html or http://www.phytec.eu/europe/support/registration.html
For technical support and additional information concerning your product, please visit the support section of our
website which provides product-specific information, such as errata sheets, application notes, FAQs, etc.
https://www.phytec.de/produkte/system-on-modules/phycore-imx-6/#downloads/
1.3 Declaration of Electro Magnetic Conformity of the PHYTEC
phyCORE®‑i.MX 6
PHYTEC System on Module (henceforth products) are designed for installation in electrical appliances or as
dedicated Evaluation Boards (i.e.: for use as a test and prototype platform for hardware/software development) in
laboratory environments.
PHYTEC products fulfill the norms of the European Union’s Directive for Electro Magnetic Conformity in accordance
with the descriptions and rules of usage indicated in this hardware manual (particularly with respect to the pin
header row connectors, power connector, and serial interface to a host-PC).
1.4 Product Change Management and Information Regarding Parts
Populated on the SOM / SBC
With the purchase of a PHYTEC SOM / SBC, you will, in addition to our hardware and software possibilities, receive
free obsolescence maintenance service for the hardware we provide. Our PCM (Product Change Management) team
of developers is continuously processing all incoming PCNs (Product Change Notifications) from vendors and
distributors concerning parts that are used in our products. Possible impacts on the functionality of our products
Warning
PHYTEC products lacking protective enclosures are subject to damage by ESD and, therefore, must be
unpacked, handled, or operated in environments in which sufficient precautionary measures have been
taken with respect to ESD dangers. Only appropriately trained personnel such as qualified electricians,
technicians, and engineers should handle and/or operate these products. Moreover, PHYTEC products
should not be operated without protection circuitry if connections to the product's pin header rows are
longer than 3 m.
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Tip
Implementation of PHYTEC products into target devices, as well as user modifications and extensions of
PHYTEC products, is subject to renewed establishment of conformity to and certification of Electro
Magnetic Directives. Users should ensure conformance following any modifications to the products as well
as the implementation of the products into target systems.
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due to changes in functionality or obsolesce of certain parts are constantly being evaluated in order to take the
right measures either in purchasing decisions or within our hardware/software design.
Our general philosophy here is: We never discontinue a product as long as there is a demand for it.
Therefore, we have established a set of methods to fulfill our philosophy:
Avoidance strategies:
Avoid changes by evaluating the longevity of parts during the design-in phase.
Ensure the availability of equivalent second source parts.
Stay in close contact with part vendors to be aware of roadmap strategies.
Change management in the rare event of an obsolete and non-replaceable part:
Ensure long-term availability by stocking parts through last-time buy management according to product
forecasts.
Offer long-term frame contracts to customers.
Change management in case of functional changes:
Avoid impacts on product functionality by choosing equivalent replacement parts.
Avoid impacts on product functionality by compensating for changes through hardware redesign or
backward-compatible software maintenance.
Provide early change notifications concerning functional, relevant changes to our products.
We refrain from providing detailed part-specific information within this manual, which can be subject to
continuous changes, due to part maintenance for our products.
In order to receive reliable, up-to-date, and detailed information concerning parts used for our product,
please contact our support team through the contact information given within this manual.
1.5 PHYTEC Documentation
PHYTEC will provide a variety of hardware and software documentation for all of our products. This includes any or
all of the following:
Quickstart Guide: A short guide on how to set up and boot a phyCORE board along with brief information on
building a BSP, the device tree, and accessing peripherals.
Hardware Manual: A detailed description of the System on Module and accompanying carrier board.
Yocto Guide: A comprehensive guide for the Yocto version the phyCORE uses. This guide contains an
overview of Yocto; an introduction, installing, and customizing the PHYTEC BSP; how to work with programs
like Poky and Bitbake; and much more.
BSP Manual: A manual specific to the BSP version of the phyCORE. Information such as how to build the
BSP, booting, updating software, device tree, and accessing peripherals can be found here.
Development Environment Guide:This guide shows how to work with the Virtual Machine (VM) Host
PHYTEC has developed and prepared to run various Development Environments. There are detailed step-by-
step instructions for Eclipse and Qt Creator, which are included in the VM. There are instructions for running
demo projects for these programs on a phyCORE product as well. Information on how to build a Linux host
PC yourself is also a part of this guide.
Pin Muxing Table: phyCORE SOMs have an accompanying pin table (in Excel format). This table will show
the complete default signal path, from processor to carrier board. The default device tree muxing option will
also be included. This gives a developer all the information needed in one location to make muxing changes
and design options when developing a specialized carrier board or adapting a PHYTEC phyCORE SOM to an
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On top of these standard manuals and guides, PHYTEC will also provide Product Change Notifications, Application
Notes, and Technical Notes. These will be done on a case-by-case basis. Most of the documentation can be found
on the applicable download page of our products.
Tip
After finishing the Quickstart Guide, we recommend working through the Development Environment
Guide. This will give you a comprehensive overview of the features and functions of both the SOM and
carrier board.
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2 Conventions, Abbreviations, and Acronyms
This hardware manual describes the PCM-058 System on Module in the following referred to as phyCORE®-i.MX6.
The manual specifies the phyCORE®-i.MX 6's design and function. Precise specifications for the NXP® Semiconductor
i.MX 6 microcontrollers can be found in the enclosed Microcontroller Data Sheet/User's Manual.
2.1 Conventions
The conventions used in this manual are as follows:
Signals that are preceded by an "n", "/", or “#” character (e.g.: nRD, /RD, or #RD), or that have a dash on top
of the signal name (e.g.: RD) are designated as active low signals. That is, their active state is when they are
driven low or are driving low.
A "0" indicates a logic zero or low-level signal, while a "1" represents a logic one or high-level signal.
The hex numbers are given for addresses of I2C devices always represent the 7 MSB of the address byte. The
correct value of the LSB which depends on the desired command (read (1), or write (0)) must be added to get
the complete address byte. E.g. given address in this manual 0x41 => complete address byte = 0x83 to read
from the device and 0x82 to write to the device
Tables that describe jumper settings show the default position in bold, blue text.
Text in blueindicates a hyperlink within, or external to the document. Click these links to quickly jump to the
applicable URL, part, chapter, table, or figure.
References made to the phyCORE-Connector always refer to the high-density Samtec connector on the undersides
of the phyCORE‑i.MX 6 System on Module.
We refrain from providing detailed part-specific information within this manual, which can be subject to
continuous changes, due to part maintenance for our products. Please read the paragraph "Product
Change Management and information in this manual on parts populated on the SOM" within the
Preface.
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The BSP delivered with the phyCORE®-i.MX 6 usually includes drivers and/or software for controlling all
components such as interfaces, memory, etc. Therefore programming close to hardware at register level is
not necessary in most cases. For this reason, this manual contains no detailed description of the
controller's registers, or information relevant to software development. Please refer to the i.MX6 Reference
Manual, if such information is needed to connect customer-designed applications.
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2.2 Types of Signals
Different types of signals are brought out at the phyCORE-Connector. The following table lists the abbreviations
used to specify the type of a signal.
TABLE 1: Signal Types Used in this Manual
Signal Type Description Abbr.
Power Supply voltage input PWR_I
Ref-Voltage Reference voltage output REF_O
Input Digital input I
Output Digital output O
IO Bidirectional input/output I/O
OC-Bidir PU Open collector input/output with pull up OC-BI
OC-Output Open collector output without pull up requires an
external pull up
OC
5V Input PD 5 V tolerant input with pull-down 5V_PD
LVDS Input Differential line pairs 100 Ohm LVDS level input LVDS_I
LVDS Output Differential line pairs 100 Ohm LVDS level output LVDS_O
TMDS Output Differential line pairs 100Ohm TMDS level output TMDS_O
USB IO Differential line pairs 90Ohm USB level bidirectional
input/output
USB_I/O
ETHERNET Input Differential line pairs 100Ohm Ethernet level input ETH_I
ETHERNET Output Differential line pairs 100Ohm Ethernet level output ETH_O
ETHERNET IO Differential line pairs 100Ohm Ethernet level
bidirectional input/output
ETH_I/O
PCIe Input Differential line pairs 100Ohm PCIe level input PCIe_I
PCIe Output Differential line pairs 100Ohm PCIe level output PCIe_O

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MIPI CSI‑2 Input Differential line pairs 100Ohm MIPI CSI‑2 level input CSI‑2_I

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2.3 Abbreviations and Acronyms
Many acronyms and abbreviations are used throughout this manual. Use the following tableto navigate unfamiliar
terms used in this document.
TABLE 2: Abbreviations and Acronyms Used in this Manual
Abbreviation Definition
BSP Board Support Package (Software delivered with the Development Kit
including an operating system (Windows, or Linux) preinstalled on the module
and Development Tools)
CB Carrier Board; used in reference to the phyCORE Development Kit Carrier
Board
DFF D flip-flop
EMB External memory bus
EMI Electromagnetic Interference
GPI General-purpose input
GPIO General-purpose input and output
IRAM Internal RAM; the internal static RAM on the NXP® Semiconductor i.MX 6
microcontroller
J Solder jumpers; these types of jumpers require solder equipment to remove
and place
JP Solderless jumpers; these types of jumpers can be removed and placed by
hand with no special tools
PCB Printed circuit board
PDI PHYTEC Display Interface; defined to connect PHYTEC display adapter boards,
or custom adapters
PEB PHYTEC Extension Board
PMIC Power management IC
PoE Power over Ethernet

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Abbreviation Definition
POR Power-on reset
RTC Real-time clock
SMT Surface mount technology
SOM System on Module; used in reference to the PCM-058 /phyCORE®-i.MX6
module
Sx User button Sx (e.g. S1, S2, etc.) used in reference to the available user
buttons, or DIP-Switches on the carrier board
Sx_y Switch y of DIP-Switch Sx; used in reference to the DIP-Switch on the carrier
board

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3 phyCORE-i.MX 6 Introduction
The phyCORE‑i.MX 6 belongs to PHYTEC’s phyCORE System on Module family. The phyCORE SOMs represent the
continuous development of PHYTEC System on Module technology. Like its mini-, micro-, and nanoMODUL
predecessors, the phyCORE boards integrate all core elements of a microcontroller system on a subminiature board
and are designed in a manner that ensures their easy expansion and embedding in peripheral hardware
developments.
As independent research indicates that approximately 70 % of all EMI (Electro-Magnetic Interference) problems
stem from insufficient supply voltage grounding of electronic components in high-frequency environments, the
phyCORE board design features an increased pin package. The increased pin package allows the dedication of
approximately 20 % of all connector pins on the phyCORE boards to Ground. This improves EMI and EMC
characteristics and makes it easier to design complex applications meeting EMI and EMC guidelines using phyCORE
boards even in high-noise environments.
phyCORE boards achieve their small size through modern SMD technology and multi-layer design. In accordance
with the complexity of the module, 0402-packaged SMD components and laser-drilled microvias are used on the
boards, providing phyCORE users with access to this cutting-edge miniaturization technology for integration into
their own design.
The phyCORE‑i.MX6 is a subminiature (40mm x 50mm) insert-ready System on Module populated with the NXP®
Semiconductor i.MX6 microcontroller. Its universal design enables its insertion in a wide range of embedded
applications. All controller signals and ports extend from the controller to high-density pitch (0.5 mm) connectors
aligning two sides of the board, allowing it to be plugged like a "big chip" into a target application.
Precise specifications for the controller populating the board can be found in the applicable controller reference
manual or datasheet. The descriptions in this manual are based on the NXP® Semiconductor i.MX6. No description
of compatible microcontroller derivative functions is included, as such functions are not relevant for the basic
functioning of the phyCORE‑i.MX6.
3.1 Features of the phyCORE-i.MX 6
The phyCORE‑i.MX6 offers the following features:
Insert-ready, sub-miniature (40mm x 50mm) System on Module (SOM) subassembly in low EMI design,
achieved through advanced SMD technology
Populated with the NXP® Semiconductor i.MX 6 microcontroller (BGA624 packaging)
1.0 GHz core clock frequency (optional 1.2 GHz)
Boot from different memory devices (NAND Flash (standard))
Controller signals and ports extend to two high-density (0.5mm) Samtec connectors aligning two sides of the
board, enabling the phyCORE‑i.MX 6 to be plugged like a "big chip" into the target application
Single supply voltage of +3.3 V with on-board power management
All controller-required supply voltages are generated onboard
Improved interference safety achieved through multi-layer PCB technology and dedicated ground pins
512MB (up to 2 GB[1]) DDR3 SDRAM
256MB (up to 16GB[1]) onboard NAND Flash
Alternatively 2GB (up to 32GB[1]) onboard eMMC
16MB2 on-board serial Flash (bootable)
4kB2 I2C EEPROM
2x serial interfaces (TTL). One with 4 lines allows a simple hardware handshake
1x High-Speed USB OTG interface
1x High-Speed USB HOST interface

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1x 10/100/1000 Mbit Ethernet interface. Either with Ethernet transceiver on the phyCORE-i.MX 6 allowing for
direct connection to an existing Ethernet network, or without onboard transceiver and provision of the RMII
signals at TTL-level at the phyCORE-Connector instead[2]
1x I2C interface
2x SPI interfaces
1x PCIe interface
1x I2S interface
1x SPDIF interface
1x PWM output
1x CAN interface
2x 4-channel LVDS (24-bit) LCD-interfaces
1x Parallel LCD interface with up to 24-bit
1x HDMI interface
Up to 2x parallel camera interfaces
1x MIPI CSI camera interface
2x SD/MMC card interfaces (1 x 8 bit, 1 x 4 bit)
1x SATA interface
1x JTAG interface
1x user-programmable LED
Tamper detection
Several dedicated GPIOs[3]
Power Management IC (PMIC)
Available for different temperature grades (Product Temperature Grades)
1. The maximum memory size listed is as of the printing of this manual.
Please contact PHYTEC for more information about additional, or new module configurations available.
2. Please refer to the order options described in the Preface,
or contact PHYTEC for more information about additional module configurations.
3. Almost every controller port which connects directly to the phyCORE‑Connector
may be used as GPIO by using the i.MX 6's pin muxing options.

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3.2 Block Diagram
FIGURE 1: Block Diagram of the phyCORE-i.MX 6
Note
The specified direction indicated refers to the standard phyCORE use of the pin.
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3.3 phyCORE-i.MX 6Component Placement
FIGURE 2: phyCORE‑i.MX6 Component Placement (PCB 1429.3, top view)

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FIGURE 3: phyCORE‑i.MX 6 Component Placement (PCB 1429.3, bottom view)
3.4 Minimum Requirements to Operate the phyCORE-i.MX 6
The basic operation of the phyCORE‑i.MX 6 only requires a supply of a +3.3 V input voltage with a typical 2.5 A load
and the corresponding GND connection.
These supplypins are located at the phyCORE-Connector X1:
 VDD_3V3: X1 A1, A2, A3, A4, B1, B2, B3, B4
Connect all +3.3V VCC input pins to your power supply and at least the matching number of GND pins.
 Corresponding GND: X1 A6, A11, A16, A21, B6, B12, B17, B22
Please refer toPin Description for information on additional GND Pins located at the phyCORE-Connector X1.
Note
The layout is identical for 1429.4 and 1429.5 except for some minor changes.

Warning
We recommend connecting all available +3.3 V input pins to the power supply system on a custom carrier
board housing the phyCORE‑i.MX 6 and at least the matching number of GND pins neighboring the +3.3 V
pins. In addition, proper implementation of the phyCORE‑i.MX6 module into a target application also
requires connecting all GND pins.
Please refer toPower for more information.
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4 Pin Description
Please note that all module connections are not to exceed their expressed maximum voltage or current. Maximum
signal input values are indicated in the corresponding controller manuals/datasheets. As damage from improper
connections varies according to use and application, it is the user's responsibility to take appropriate safety
measures to ensure that the module connections are protected from overloading through connected peripherals.
AsPinout of the phyCORE-Connector (top view) indicates, all controller signals selected extend to surface mount
technology (SMT) connectors(0.5mm) lining two sides of the module (referred to as phyCORE‑Connector). This
allows the phyCORE‑i.MX6 to be plugged into any target application like a "big chip".
The numbering scheme for the phyCORE‑Connector is based on a two-dimensional matrix in which column
positions are identified by a letter and row positions by a number. The pin numbering values increase moving down
on the board (Pinout of the phyCORE-Connector (top view)).
The numbered matrix can be aligned with the phyCORE‑i.MX6 (viewed from above; phyCORE‑Connector pointing
down) or with the socket of the corresponding phyCORE Carrier Board/user target circuitry. The upper left-hand
corner of the numbered matrix (pin X1C1) is thus covered with the corner of the phyCORE‑i.MX6. The numbering
scheme is always in relation to the PCB as viewed from above, even if all connector contacts extend to the bottom
of the module.
The numbering scheme is thus consistent for both the module’s phyCORE-Connector as well as the mating
connector on the phyCORE Carrier Board or target hardware, thereby considerably reducing the risk of pin
identification errors.
Since the pins are exactly defined according to the numbered matrix previously described, the phyCORE-Connector
is usually assigned a single designator for its position (X1 for example). In this manner, the phyCORE‑Connector
comprises a single, logical unit regardless of the fact that it could consist of more than one physical socketed
connector.
The following figure illustrates the numbered matrix system. It shows a phyCORE‑i.MX6 with both SMT phyCORE-
Connectors on its underside (defined as dotted lines) mounted on a carrier board. In order to facilitate
understanding of the pin assignment scheme, the diagram presents a cross-view of the phyCORE‑i.MX6 module
showing the phyCORE-Connector mounted on the underside of the module’s PCB.
The following tables provide an overview of the pinout of phyCORE-Connector X1 with signal names and
descriptions specific to phyCORE‑i.MX 6. It also provides the appropriate voltage domain, signal type (ST), and a
functional grouping of the signals. The signal type includes also information about the signal direction. A
description of the signal types can be found in Types of Signals.
Note
The specified direction indicated refers to the standard phyCORE use of the pin.
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FIGURE 4: Pinout of the phyCORE-Connector (top view)
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Warning
The NXP® Semiconductor i.MX6 is a multi-voltage operated microcontroller and as such special
attention should be paid to the interface voltage levels to avoid unintentional damage to the
microcontroller and other on-board components. Please refer to the NXP Semiconductor i.MX6
Reference Manual for details on the functions and features of controller signals and port pins.
As some of the signals which are brought out on the phyCORE-Connector are used to configure the
boot mode for specific boot options, please make sure that these signals are not driven by any
device on the baseboard during reset. The signals which may affect the boot configuration are
shown in Boot Configuration Pins at the phyCORE‑Connector.
It is mandatory to avoid voltages at the IO pins of the phyCORE-i.MX 6 which are sourced from the
supply voltage of peripheral devices attached to the SOM during power-up, or power–down. These
voltages can cause a current flow into the controller, especially if peripheral devices attached to
the interfaces of the i.MX 6 are supposed to be powered while the phyCORE‑i.MX 6 is in suspend
mode or turned off. To avoid this, bus switches either supplied by VDD_3V3_LOGIC on the phyCORE
side or having their output enable the SOM controlled by the X_3V3_GOOD signal (Supply Voltage
for External Logic) must be used.
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Most of the controller pins have multiple multiplexed functions. As most of these pins are
connected directly to the phyCORE-Connector the alternative functions are available by using the
i.MX6's pin muxing options. Signal names and descriptions in the tables below however are in
regard to the specification of the phyCORE‑i.MX 6 and the functions defined Please refer to the
i.MX6 Reference Manual, or the schematic to get to know about alternative functions. In order to
utilize a specific pin's alternative function, the corresponding registers must be configured within
the appropriate driver of the BSP.
The tables below describe the full set of signals available at the phyCORE‑Connector according to
the phyCORE-i.MX 6 specification. However, the availability of some interfaces is order-specific (e.g.
Camera_0). Thus, some signals might not be available on your module.
If the phyCORE-i.MX6 is delivered with a carrier board (e.g. the phyBOARD‑Mira) the pin muxing
might be changed within the appropriate BSP in order to support all features of the carrier board. If
so, information on the differences from the pinout given in the following tables can be found in the
carrier board's documentation.
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