Phytec phyCORE i.MX8X User manual

A product of a PHYTEC Technology Holding company
phyCORE®-i.MX8X
Hardware Manual
Document No.: L-864e.A1
SOM Prod. No.: PCM-065
SOM PCB. No.: 1488.2
CB Prod. No.: PCM-942
CB PCB. No.: 1491.1
Edition: Feb 2021

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Copyright 2021 PHYTEC Technologie Holding AG (and affiliated companies, hereafter “PHYTEC”),
D-55129 Mainz.
Rights - including those of translation, reprint, broadcast, photomechanical or similar reproduction and storage
or processing in computer systems, in whole or in part - are reserved. No reproduction may occur without the
express written consent from PHYTEC.
The information in this document has been carefully checked and is considered to be entirely reliable. However,
PHYTEC assumes no responsibility for any inaccuracies. PHYTEC neither gives any guarantee nor accepts any
liability whatsoever for consequential damages resulting from the use of this manual or its associated product.
PHYTEC reserves the right to alter the information contained herein without prior notification and accepts no
responsibility for any damages that might result.
Additionally, PHYTEC offers no guarantee nor accepts any liability for damages arising from the improper usage
or improper installation of the hardware or software. PHYTEC further reserves the right to alter the layout and/or
design of the hardware without prior notification and accepts no liability for doing so.
Copyrighted products are not explicitly indicated in this manual. The absence of the trademark (™ or ®) and
copyright (©) symbols does not imply that a product is not protected. Additionally, registered patents and
trademarks are similarly not expressly indicated in this manual.

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Table of Contents
Table of Contents..............................................................................................................................................3
List of Figures....................................................................................................................................................5
List of Tables.....................................................................................................................................................6
Preface..............................................................................................................................................................8
Product Change Management...........................................................................................................................9
Conventions, Abbreviations and Acronyms......................................................................................................10
1Introduction...........................................................................................................................................13
2SOM Features ......................................................................................................................................14
3Block Diagram ......................................................................................................................................15
4Physical Dimensions.............................................................................................................................16
5Component Placement Diagram...........................................................................................................17
6Technical Specifications........................................................................................................................20
7Electrical Specifications ........................................................................................................................21
8Minimum Requirements for Operation...................................................................................................22
9Solder Jumpers.....................................................................................................................................23
1.1 Solder Jumper Locations ...............................................................................................................25
2Pin Descriptions....................................................................................................................................27
2.1 Pinout Tables.................................................................................................................................29
3Power ...................................................................................................................................................36
3.1 Primary System Power (VCC)........................................................................................................36
3.2 Backup Power (VBAT)...................................................................................................................36
3.3 Reset.............................................................................................................................................36
3.4 Power Management.......................................................................................................................37
4System Memory....................................................................................................................................38
4.1 DDR4 RAM....................................................................................................................................38
4.2 EEPROM.......................................................................................................................................38
4.3 eMMC Flash ..................................................................................................................................38
4.4 NAND ............................................................................................................................................39
4.5 OSPI..............................................................................................................................................39
4.6 SD/MMC/SDIO ..............................................................................................................................40
5System Boot Configuration ...................................................................................................................41
6Serial Interfaces....................................................................................................................................42
6.1 CAN...............................................................................................................................................42
6.2 Ethernet.........................................................................................................................................42
6.3 I2C..................................................................................................................................................44
6.4 Media Local Bus............................................................................................................................45

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6.5 PCIe...............................................................................................................................................45
6.6 SAI and ESAI.................................................................................................................................45
6.7 SPDIF............................................................................................................................................47
6.8 SPI.................................................................................................................................................47
6.9 UART.............................................................................................................................................48
6.10 USB...............................................................................................................................................48
7Control Interfaces..................................................................................................................................50
7.1 M4F ...............................................................................................................................................50
7.2 PWM..............................................................................................................................................50
8Debug Interfaces...................................................................................................................................51
8.1 JTAG .............................................................................................................................................51
8.2 UART0...........................................................................................................................................51
9Display Interfaces .................................................................................................................................52
9.1 LVDS/MIPI DSI..............................................................................................................................52
9.2 Parallel LCD Display......................................................................................................................53
10 Camera Interfaces ................................................................................................................................54
10.1 MIPI CSI........................................................................................................................................54
10.2 Parallel Camera Input Port.............................................................................................................54
11 Peripheral Interfaces.............................................................................................................................55
11.1 ADC...............................................................................................................................................55
11.2 FlexTimer.......................................................................................................................................55
11.3 GPIO..............................................................................................................................................55
11.4 GPT...............................................................................................................................................58
11.5 KPP ...............................................................................................................................................59
11.6 MQS..............................................................................................................................................59
11.7 Security..........................................................................................................................................59
11.8 Tamper..........................................................................................................................................60
11.9 Watchdog ......................................................................................................................................60
12 Hints for Integrating and Handling the phyCORE-i.MX8X......................................................................61
12.1 Integration......................................................................................................................................61
12.2 Modification....................................................................................................................................61
Revision History...............................................................................................................................................62

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List of Figures
Figure 1. phyCORE-i.MX8X Block Diagram....................................................................................................15
Figure 2. phyCORE-i.MX8X Component Placement (processor side).............................................................18
Figure 3. phyCORE-i.MX8X Component Placement (connector side).............................................................19
Figure 4. Three-Position Solder Jumper Pad Numbering Scheme..................................................................23
Figure 5. Pinout of the phyCORE-Connector (top view, with cross section insert) ..........................................28
Figure 6. Jumper Locations (Top Side)...........................................................................................................25
Figure 7. Jumper Locations (Underside).........................................................................................................26
Figure 8. Power Management Diagram..........................................................................................................37

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List of Tables
Table 1. Abbreviations and Acronyms used in this Manual.............................................................................10
Table 2. Signal Types Used in this Manual.....................................................................................................11
Table 3. Technical Specifications ...................................................................................................................20
Table 4. Recommended Operating Conditions for the Input and Output Power Domains...............................21
Table 5. Voltage Domain Configurations ........................................................................................................23
Table 6. Solder Jumper Settings.....................................................................................................................24
Table 7. phyCORE-i.MX8X Connector X1, Column A Pinout..........................................................................29
Table 8. phyCORE-i.MX8X Connector X1, Column B Pinout..........................................................................30
Table 9. phyCORE-i.MX8X Connector X1, Column C Pinout..........................................................................32
Table 10. phyCORE-i.MX8X Connector X1, Column D Pinout........................................................................33
Table 11. Reset Pin Description .....................................................................................................................36
Table 12. External Supply Voltages................................................................................................................37
Table 13. Internal Voltage Rails......................................................................................................................37
Table 14. eMMC Signal Connections to the Processor...................................................................................38
Table 15. NAND Signal Connections to the Processor ...................................................................................39
Table 16. OSPI0 Connections at the phyCORE-Connector............................................................................40
Table 17. MMC1 Connections at the phyCORE-Connector............................................................................40
Table 18. BOOTMODE Description................................................................................................................41
Table 19. FlexCAN Connections at the phyCORE-Connector.........................................................................42
Table 20. Ethernet Connections at the phyCORE-Connector .........................................................................42
Table 21. Ethernet PHY Default Strapping Configuration................................................................................44
Table 22. Connections at the phyCORE-Connector........................................................................................44
Table 23. MLB Connections at the phyCORE-Connector ...............................................................................45
Table 24. PCIe Connections at the phyCORE-Connector...............................................................................45
Table 25. SAI0 Connections at the phyCORE-Connector...............................................................................45
Table 26. SAI1 Connections at the phyCORE-Connector...............................................................................46
Table 27. SAI2 Connections at the phyCORE-Connector...............................................................................46
Table 28. SAI3 Connections at the phyCORE-Connector...............................................................................46
Table 29. MCLK Connections at the phyCORE-Connector.............................................................................46
Table 30. ESAI0 Connections at the phyCORE-Connector.............................................................................46
Table 31. SPDIF Connections at the phyCORE-Connector............................................................................47
Table 32. SPI Connections at the phyCORE-Connector.................................................................................47
Table 33. UART Connections at the phyCORE-Connector.............................................................................48
Table 34. USB0 SS3 Connections at the phyCORE-Connector......................................................................48
Table 35. USB0 OTG Connections at the phyCORE-Connector.....................................................................49
Table 36. USB1 OTG Connections at the phyCORE-Connector.....................................................................49
Table 37. M4F Connections at the phyCORE-Connector................................................................................50
Table 38. PWM Connections at the phyCORE-Connector..............................................................................50
Table 39. JTAG Connections at the phyCORE-Connector..............................................................................51
Table 40. UART Connections at the phyCORE-Connector.............................................................................51
Table 41. LVDS/MIPI Connections at the phyCORE-Connector.....................................................................52
Table 42. Parallel Display Connections at the phyCORE-Connector ..............................................................53
Table 43. MIPI CSI Connections at the phyCORE-Connector.........................................................................54
Table 44. Parallel Camera Connections at the phyCORE-Connector .............................................................54
Table 45. ADC Connections at the phyCORE-Connector...............................................................................55
Table 46. FlexTimer Signals...........................................................................................................................55
Table 47. Total Available GPIO ......................................................................................................................55
Table 48. GPIO0 Accessibility at phyCORE-Connector..................................................................................56

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Table 49. GPIO1 Accessibility at phyCORE-Connector..................................................................................56
Table 50. GPIO2 Accessibility at phyCORE-Connector..................................................................................57
Table 51. GPIO3 Accessibility at phyCORE-Connector..................................................................................57
Table 52. GPIO4 Accessibility at phyCORE-Connector..................................................................................58
Table 53. GPIO5 Accessibility at phyCORE-Connector..................................................................................58
Table 54. GPT Signals....................................................................................................................................59
Table 55. KPP Signals....................................................................................................................................59
Table 56. MQS Signals..................................................................................................................................59
Table 57. Security Signals..............................................................................................................................59
Table 58. Tamper Signals...............................................................................................................................60
Table 59. Watchdog Signals...........................................................................................................................60
Table 60. Document Revision History.............................................................................................................62

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Preface
Members of PHYTEC's phyCORE®product family can be populated with different processors and offer various
functions and configurations. PHYTEC supports a variety of Arm-based and other microprocessors in two ways.
1. As the basis for PHYTEC development kits and Single Board Computers, which serves as a reference and
evaluation platform.
2. As insert-ready, fully functional phyCORE®OEM System on Modules (SOMs) and phyBOARD Single
Board Computers (SBCs), which can be incorporated directly into the user’s hardware design.
Implementing an OEM-able SOM subassembly as the "core" of your embedded design allows for increased
focus on hardware peripherals and firmware without expending resources to "re-invent" microprocessor circuitry.
Production-ready Board Support Packages (BSPs) and Design Services for our hardware will further reduce
development time, risk and allows for increased focus on product expertise. Take advantage of PHYTEC
products to shorten time-to-market, reduce development costs, and avoid substantial design issues and risks.
With this new innovative full system solution, new ideas can be brought to market in the most timely and cost-
efficient manner.
For more information go to: https://phytec.com/design-services/
Declaration of Electromagnetic Conformity of the
PHYTEC phyCORE-i.MX8X System On Module
PHYTEC System on Modules (SOM) and Single Board Computers (SBC), henceforth collectively referred to as
“products”, are designed as subcomponents for integration in electrical devices.
Combined with PHYTEC Carrier Boards, PHYTEC SOMs can be used as dedicated Evaluation Boards (i.e.: for
use as a test and prototype platform for hardware/software development) in laboratory environments.
CAUTION:
PHYTEC products lacking protective enclosures are subject to damage by ESD and, hence, may
only be unpacked, handled or operated in environments in which sufficient precautionary measures
have been taken in respect to ESD-dangers. It is also necessary that only appropriately trained
personnel (such as electricians, technicians, electronic manufacturing personnel and engineers)
handle and/or operate these products.
PHYTEC products fulfill the rules and regulations of the European Union’s Directive for Electromagnetic
Conformity and the Federal Communications Commission Title 47 CFR Part 15 Subpart B only in accordance
with the descriptions and rules of usage indicated in this hardware manual, particularly in respect to the external
SOM connector, power interfaces and interfaces to host systems for programming.
NOTE:
Integration of PHYTEC products into target devices, as well as user modifications and extensions of
PHYTEC products, is subject to renewed establishment of conformity to, and certification of,
Electromagnetic Directives. Users should ensure conformance following any modifications to the
products as well as implementation of the products into target systems.

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Product Change Management
Use of PHYTEC products ensures interchangeable microprocessor core circuitry in the event of obsolescence
of parts used on our SOMs and SBCs. End users no longer need to redesign entire CPU circuitry and engage
in version control to accommodate new or obsolete parts. Instead, PHYTEC manages this at the SOM-level.
PHYTEC ensure continued availability of pin- and function-compatible SOMs and SBCs, further minimizing
maintenance costs and risks. This pro-active PLM policy has enabled deployment of the same PHYTEC SOM
in designs for over twenty years. See https://www.phytec.com/product-lifecycle-management-obsolescence-
policy/ for more details on our Product Longevity, Product Obsolescence and Product Maintenance policies.

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Conventions, Abbreviations and Acronyms
This hardware manual describes the PCM-065 System on Module, henceforth referred to as phyCORE-i.MX8X.
The manual specifies the phyCORE-i.MX8X's design and function. Precise specifications for the NXP
Semiconductor i.MX8X microprocessors can be found in the i.MX8X Processor Reference Manual.
We refrain from providing detailed part specific information within this manual which can be subject to changes.
This is due to the continuous maintenance of our products. Please read the section Product Change
Management within the Preface.
The BSP delivered with the phyCORE-i.MX8X includes drivers and/or software for controlling all components
such as interfaces, memory, etc. Therefore, programming close to the hardware (at the register level) is not
necessary in most cases. For this reason, this manual contains no detailed description of the processor's
registers, or information relevant for software development. Please refer to the i.MX8X Processor Reference
Manual if such information is needed.
Conventions
The conventions used in this manual are as follows:
•Signals that are preceded by an "n", "/", or “#”character (e.g.: nRD, /RD, or #RD), are designated as
active low signals. That is, their active state is when they are driven low, or are driving low.
•A "0" indicates a logic zero or low-level signal, while a "1" represents a logic one or high-level signal.
•The hex-numbers given for addresses of I2C devices always represent the 7 most-significant bits
(MSB) of the address byte. The correct value of the least-significant bit (LSB) will depend on the desired
command (read (1), or write (0)) and must be added to get the complete address byte. E.g. given the
address in this manual 0x41 => complete address byte = 0x83 to read from the device and 0x82 to write
to the device
•Text in blue italics indicate a cross-reference to an internal section of this document. Click these links to
quickly jump to the applicable part, chapter, table, or figure.
•Text in underlined in blue indicate an external link. Click these links to quickly jump to the applicable URL.
•References made to the phyCORE-Connector always refer to the high density Samtec connectors on the
undersides of the phyCORE-i.MX8X System on Module.
Abbreviations and Acronyms
Many acronyms and abbreviations are used throughout this manual. Use the table below to navigate unfamiliar
terms used in this document.
Table 1. Abbreviations and Acronyms used in this Manual
Abbreviation
Definition
BSP
Board Support Package (Software delivered with the Development Kit including an operating system (Windows,
or Linux) preinstalled on the module and Development Tools)
CB
Carrier Board; used in reference to the phyCORE Development Kit Carrier Board
CSI
CMOS Sensor Interface
DDR
Double data rate
DRAM
Dynamic random access memory
EMC
Electromagnetic Compatibility
EMI
Electromagnetic Interference
GPIO
General-Purpose Input/Output
GPT
General-Purpose Timer
J
Solder Jumper: these types of jumpers require solder equipment to remove and place

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JP
Solderless Jumper: these types of jumpers can be removed and placed by hand with no special tools
JTAG
Joint Test Action Group (a serial bus protocol usually used for test purposes)
KPP
Key Pad Port
LCD
Liquid Crystal Display
LVDS
Low Voltage Differential Signaling
MQS
Medium Quality Sound
PCB
Printed circuit board
PCI
Peripheral Component Interconnect
PCIe
PCI express
PCM
Product Change Management
PCN
Product Change Notification
PDI
PHYTEC Display Interface; defined to connect PHYTEC display adapter boards, or custom adapters
PEB
PHYTEC Expansion Board
PMIC
Power management IC
POR
Power-on reset
PWM
Pulse-width Modulation
RTC
Real-time clock
SD
Secure Digital
SMT
Surface mount technology
SOM
System on Module; used in reference to the BOARD DESIGNATOR/ SOM BOARD NAME module
SPI
Serial Peripheral Interface
Sx
User button Sx(e.g. S1, S2, etc.) used in reference to the available user buttons, or DIP-Switches on the carrier
board
UART
Universal Asynchronous Receiver/Transmitter
Signal Types
Different types of signals are brought out at the phyCORE-Connector. Table 2 below lists the abbreviations used
to specify the type of a signal.
Table 2. Signal Types Used in this Manual
Signal Type
Description
Abbreviation
Analog
Analog
A
Power
Supply voltage input
PWR_I
Input
Digital input
I
Output
Digital output
O
IO
Bidirectional input/output
I/O
OD-Bidir PU
Open drain input/output with pull up
OD-BI
OD-Output
Open drain output without pull-up, requires an external pull-up
OD
5V Input PD
5 V tolerant input with pull down
5V_PD
LVDS Input
Differential line pairs 100 Ohm LVDS level input
LVDS_I
LVDS Output
Differential line pairs 100 Ohm LVDS level output
LVDS_O
USB IO
Differential line pairs 90 Ohm USB level bidirectional input/output
USB_I/O
ETHERNET Input
Differential line pairs 100 Ohm Ethernet level input
ETH_I
ETHERNET Output
Differential line pairs 100 Ohm Ethernet level output
ETH_O
ETHERNET IO
Differential line pairs 100 Ohm Ethernet level bidirectional input/output
ETH_I/O

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PCIe Input
Differential line pairs 100 Ohm PCIe level input
PCIe_I
PCIe Output
Differential line pairs 100 Ohm PCIe level output
PCIe_O
MIPI CSI-2 Input
Differential line pairs 100 Ohm MIPI CSI-2 level input
CSI-2_I

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1Introduction
The phyCORE-i.MX8X belongs to PHYTEC’s phyCORE System on Module family. Like its mini, micro, and
nanoMODUL predecessors, the phyCORE boards integrate all core elements of a microprocessor system on a
subminiature board and are designed in a manner that ensures their easy expansion and embedding in
peripheral hardware developments.
Independent research indicates that approximately 70% of all EMI problems stem from insufficient grounding of
electronic components in high frequency environments. The phyCORE board design features an increased pin
package that dedicates approximately 37% of all connector pins to ground. This improves EMI and EMC
characteristics and makes it easier to design complex applications meeting EMI and EMC guidelines using
phyCORE boards, even in high noise environments.
Our phyCORE boards achieve their small size through SMD technology and multi-layer PCB designs. In
accordance with the complexity of the module, 0201 packaged SMT components andlaser-drilled micro-vias are
also used and provide phyCORE users with access to cutting edgeminiaturization technology for integration into
their own designs.
The phyCORE-i.MX8X is a subminiature (52mm x 42mm) insert-ready System on Module populated with the
NXP Semiconductor's i.MX8X microprocessor. Its universal design enables its insertion in a wide range of
embedded applications. All microprocessor signals and ports extend from the microprocessor to high-density
pitch (0.5 mm) connectors aligning two sides of the board, allowing it to be plugged like a "big chip" into a target
application.
Precise specifications for the processor populating the board can be found in the applicable processor reference
manual or datasheet. The descriptions in this manual are based on the NXP Semiconductor's i.MX8X. No
descriptions of compatible microprocessor derivative functions are included; these are not relevant for the basic
functioning of the phyCORE-i.MX8X.

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2SOM Features
The phyCORE-i.MX8X offers the following features:
•Insert-ready, sub-miniature (52 mm x 42 mm) System on Module (SOM) subassembly in low EMI design,
achieved through advanced SMD technology
•Populated with the NXP Semiconductors i.MX8X microprocessor (21 x 21 mm, 0.8 mm pitch S-PBGA)
•Single supply voltage of 3.3V with on-board power management
•Improved interference safety achieved through multi-layer PCB technology and dedicated ground pins
•1 x PMIC
•Up to 2GB LPDDR4 RAM
•Up to 8GB on-board eMMC
•1x Octal SPI (FlexSPI) for fast boot from SPI NOR flash (or 2x QSPI interfaces)
•1x SD 3.0 card
•2x 32KB I2C EEPROM
•2x MIPI or LVDS display
•1x 18-bit parallel LCD display
•1x 16-bit parallel CSI camera
•1x MIPI-CSI camera with 4-lanes
•1x Independent 1-lane PCIe Gen3 with L1 substate support
•2x USB OTG (2.0)
•1x SuperSpeed USB3.0 dual-role port
•2x 10/100/1000 Mbit Ethernet (1 provided via on-board PHY)
•3x FlexCAN
•1x Media Local Bus
•5x UART
•1x ESAI (Enhanced Serial Audio Interface)
•4x SAI (Serial Audio Interface)
•9x I2C
•2x ASRC (Asynchronous Sample Rate Converter)
•1x SPDIF
•1x JTAG debug port
•1x 6-channel ADC converter
•4x SPI
•1x 4x4 KPP (Key Pad Port)
•1x MQS (Medium Quality Sound)
•3.3V/1.8V GPIOs
•4x PWM
•1x Security Module
NOTE:
Some of the features listed are not available simultaneously due to the muxing options of the various
processor pins. Refer to the i.MX8X Datasheet and Processor Reference Manual for further
information on available muxing options.

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3Block Diagram
Figure 1. phyCORE-i.MX8X Block Diagram

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4Physical Dimensions
The physical dimensions of the phyCORE-i.MX8X are asfollows. The module’s profile is approximately 7.261mm
thick from the tallest component on the top (processor) to the tallest component on the bottom (phyCORE-
Connectors). The maximum component height (excluding the connector X1) is approximately 1.0 mm on the
bottom (connector) side of the PCB and approximately 2.37mm on the top (microprocessor) side. The PCB is
approximately 1.68mm thick, 42mm wide, and 52mm long. For more detailed information please refer to the
phyCORE-i.MX8X Dimensional Drawing

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5Component Placement Diagram
The phyCORE-i.MX8X component placement diagrams presented in this manual (Figure 2 and Figure 3) are for
quick reference only. Visit our Hardware Documentation Page for a comprehensive, searchable PDF:
Component Placement Diagram –phyCORE-i.MX8X

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Figure 2. phyCORE-i.MX8X Component Placement (Processor Side)

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Figure 3. phyCORE-i.MX8X Component Placement (Connector Side)

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6Technical Specifications
Table 3. Technical Specifications
Specification
Dimensions
52 mm x 42 mm x 4.8 mm
Mass
~16.65g
Storage Temperature
-25C to +85C
Operating Temperature
-25C to +85C
Humidity
TBD
Typical Idling Power Consumption1
1.92W1
1Calculated from idle Ivcc in Table 4