Phytec phyCORE-MPC5200B tiny User manual

A product of a PHYTEC Technology Holding company
phyCORE-MPC5200B
FPGA
Hardware Manual
Edition February 2006

phyCORE-MPC5200B FPGA
PHYTEC Messtechnik GmbH 2006 L-672e_0
In this manual are descriptions for copyrighted products that are not explicitly
indicated as such. The absence of the trademark () and copyright () symbols
does not imply that a product is not protected. Additionally, registered patents and
trademarks are similarly not expressly indicated in this manual.
The information in this document has been carefully checked and is believed to be
entirely reliable. However, PHYTEC Messtechnik GmbH assumes no
responsibility for any inaccuracies. PHYTEC Messtechnik GmbH neither gives
any guarantee nor accepts any liability whatsoever for consequential damages
resulting from the use of this manual or its associated product. PHYTEC
Messtechnik GmbH reserves the right to alter the information contained herein
without prior notification and accepts no responsibility for any damages which
might result.
Additionally, PHYTEC Messtechnik GmbH offers no guarantee nor accepts any
liability for damages arising from the improper usage or improper installation of
the hardware or software. PHYTEC Messtechnik GmbH further reserves the right
to alter the layout and/or design of the hardware without prior notification and
accepts no liability for doing so.
Copyright 2006 PHYTEC Messtechnik GmbH, D-55129 Mainz.
Rights - including those of translation, reprint, broadcast, photomechanical or
similar reproduction and storage or processing in computer systems, in whole or
in part - are reserved. No reproduction may occur without the express written
consent from PHYTEC Messtechnik GmbH.
EUROPE NORTH AMERICA
Address: PHYTEC Technologie Holding AG
Robert-Koch-Str. 39
D-55129 Mainz
GERMANY
PHYTEC America LLC
203 Parfitt Way SW, Suite G100
Bainbridge Island, WA 98110
USA
Ordering
Information: [phone]
[email protected] 1 [phone] [email protected]
Technical
Support: [phone]
[email protected] 1 [phone] [email protected]
Fax: [phone] [phone]
Web Site: http://www.phytec.de http://www.phytec.com
Preliminary Edition: February 2006

Contents
PHYTEC Messtechnik GmbH 2006 L-672e_0
Preface...........................................................................................................1
1Introduction.........................................................................................3
1.1 Block Diagram .............................................................................6
1.2 View of the phyCORE-MPC5200B.............................................7
1.3 Minimum Requirements to Operate the
phyCORE-MPC5200B.................................................................9
2Pin Description..................................................................................11
3Jumpers..............................................................................................23
4Power Requirements.........................................................................27
4.1 Voltage Supervision and Reset ..................................................29
5System Start-Up Configuration.......................................................31
6System Memory.................................................................................33
6.1 Flash Memory ............................................................................35
6.2 DDR SDRAM ............................................................................38
6.3 SRAM (U15)..............................................................................39
6.4 Serial Memory............................................................................40
6.5 NAND-Flash (U28)....................................................................41
6.6 Video-RAM (U20).....................................................................41
7Altera Cyclone II FPGA...................................................................43
8Serial Interfaces.................................................................................45
8.1 RS-232 Interface ........................................................................45
8.2 CAN Interface ............................................................................46
8.3 COP Debug Interface .................................................................47
8.4 Ethernet Interface.......................................................................49
8.4.1 PHY Physical Layer Transceiver..................................49
8.4.2 MAC Address................................................................50
8.5 USB 1.1 Host Interface ..............................................................51
9Real-Time Clock RTC-8564 (U7)....................................................53
10 phyCORE Carrier Board PCM-980 ...............................................55
10.1 Concept of the phyCORE Carrier Board PCM-980...................55
10.2 Carrier Board PCM-980 Overview............................................56
10.2.1 Connectors, Buttons, LEDs...........................................56
10.2.2 Jumpers on the phyCORE Carrier Board PCM-980.....59

phyCORE-MPC5200B FPGA
PHYTEC Messtechnik GmbH 2006 L-672e_0
10.3 Functional Components on the phyCORE Carrier
Board PCM-980......................................................................... 61
10.3.1 Power Supply at X10....................................................61
10.3.2 First Serial Interface at Socket P2A.............................. 62
10.3.3 Second Serial Interface at Socket P2B .........................62
10.3.4 First CAN Interface at Plug P1A.................................. 63
10.3.5 Second CAN Interface at Plug P1B..............................65
10.3.6 Programmable LED D29.............................................. 67
10.3.7 Pin Assignment Summary of the phyCORE,
the Expansion Bus and the Patch Field......................... 67
10.3.8 Silicon Serial Number/Temperature Sensor.................76
10.3.9 BDM Port X2................................................................ 77
10.3.10 Technical Specification of the Carrier Board............... 78
10.3.11 Release Notes................................................................ 80
11 Technical Specifications of the phyCORE-MPC5200B................81
12 Hints for Handling the Module .......................................................85
13 Design Considerations - Check List................................................86
14 Revision History................................................................................ 87
15 Component Placement Diagram .....................................................89
AAppendices......................................................................................... 91
A.1 Release Notes............................................................................. 91
Index ...........................................................................................................93

Contents
PHYTEC Messtechnik GmbH 2006 L-672e_0
Index of Figures
Figure 1: Block Diagram phyCORE-MPC5200B.....................................6
Figure 2: View of the phyCORE-MPC5200B Revision 1238.0 ...............8
Figure 3: Pinout of the phyCORE-MPC5200B (Bottom View) .............12
Figure 4: Numbering of the Jumper Pads................................................23
Figure 5: Location of the Jumpers (Controller Side)
(phyCORE-MPC5200B Standard Version).............................23
Figure 6: Power Supply Diagram............................................................28
Figure 7: Serial Memory I2C Slave Address...........................................41
Figure 8: COP Interface Card Edge Header X1 (Top View) ..................47
Figure 9: View of the Carrier Board PCM-980.......................................58
Figure 10: Numbering of Jumper Pads......................................................59
Figure 11: Location of the Jumpers (View of the Component Side) ........59
Figure 12: Connecting the Supply Voltage at X10....................................61
Figure 13: Pin Assignment of the DB-9 Socket P2A as First RS-232
(Front View).............................................................................62
Figure 14: Pin Assignment of the DB-9 Socket P2B as Second RS-232
(Front View).............................................................................62
Figure 15: Pin Assignment of the DB-9 Plug P1A (CAN Transceiver on
phyCORE-MPC5200B, Front View).......................................63
Figure 16: Pin Assignment of the DB-9 Plug P1A (CAN Transceiver on
Carrier Board with Galvanic Separation).................................64
Figure 17: Pin Assignment of the DB-9 Plug P1B (CAN Transceiver
on phyCORE-MPC5200B, Front View)..................................65
Figure 18: Pin Assignment of the DB-9 Plug P2B (CAN Transceiver
on arrier Board with Galvanic Separation)..............................66
Figure 19: Pin Assignment Scheme of the Expansion Bus.......................68
Figure 20: Pin Assignment Scheme of the Patch Field.............................68
Figure 21: Connecting the DS18B20 Temperature Sensor with Silicon
Serial Number ..........................................................................76
Figure 22: Pin Assignment of the DS2401 Silicon Serial Number...........76

phyCORE-MPC5200B FPGA
PHYTEC Messtechnik GmbH 2006 L-672e_0
Figure 23 Physical Dimensions of the Carrier Board PCM-980.............. 78
Figure 24: Physical Dimensions................................................................ 81
Figure 25: phyCORE-MPC5200B Component Placement, Top View..... 89
Figure 26: phyCORE-MPC5200B Component Placement,
Bottom View............................................................................ 90
Index of Tables
Table 1: Default Port Configuration ...................................................... 11
Table 2: Pinout of the phyCORE-Connector X3................................... 21
Table 3: Jumper Settings........................................................................ 26
Table 4: System Start-up Configuration ................................................ 32
Table 5: Choice of Flash Memory Devices and Manufacturers............ 35
Table 6: Control Signal for 64 MByte Flash Configuration.................. 36
Table 7: DDR SDRAM Device Selection.............................................. 38
Table 8: Serial Memory Options for U6................................................ 40
Table 9: Serial Memory I2C Address (Examples) ................................. 41
Table 10: 16-pin COP Connector (X1) and Corresponding Pins on the
phyCORE-Connector (X3) ...................................................... 48
Table 11: Signal Definition PHY Ethernet Port (U2).............................. 50
Table 12: Carrier Board Jumper Overview.............................................. 60
Table 13: Jumper Configuration for CAN Plug P1A Using the CAN
Transceiver on the phyCORE-MPC5200B ............................. 63
Table 14: Jumper Configuration for CAN Plug P1A Using the CAN
Transceiver on the Carrier Board with Galvanic Separation... 64
Table 15: Jumper Configuration for CAN Plug P2B Using the CAN
Transceiver on the phyCORE-MPC5200B ............................. 65
Table 16: Jumper Configuration for CAN Plug P2B using the CAN
Transceiver on the Carrier Board with Galvanic Separation... 66
Table 17: Signal Pin Assignment for the phyCORE-MPC5200B /
Carrier Board / Expansion Board............................................. 74
Table 18: Pin Assignment Power Supply for the
phyCORE-MPC5200B / Carrier Board / Expansion Board.... 75

Contents
PHYTEC Messtechnik GmbH 2006 L-672e_0
Table 19: Pin Assignment of the BDM Pin Header X2...........................77
Table 20: Technical Data of the Carrier Board PCM-980.......................79
Table 21: Technical Data of the phyCORE-MPC5200B.........................82

phyCORE-MPC5200B FPGA
PHYTEC Messtechnik GmbH 2006 L-672e_0

Preface
PHYTEC Messtechnik GmbH 2006 L-672e_0 1
Preface
This phyCORE-MPC5200B Hardware Manual describes the board’s
design and functions. Precise specifications for the Freescale
MPC5200B microcontroller series can be found in the enclosed
MPC5200B microcontroller Data Sheet/User's Manual. If software is
included please also refer to additional documentation for this
software.
In this hardware manual and in the attached schematics, low active
signals are denoted by a "/" in front of the signal name (i.e.: /RD). A
"0" indicates a logic-zero or low-level signal, while a "1" represents a
logic-one or high-level signal.
Declaration regarding Electro Magnetic Conformity
of the PHYTEC phyCORE-MPC5200B
PHYTEC Single Board Computers (henceforth products) are designed
for installation in electrical appliances or as dedicated Evaluation
Boards (i.e.: for use as a test and prototype platform for
hardware/software development) in laboratory environments.
Note:
PHYTEC products lacking protective enclosures are subject to
damage by ESD and, hence, may only be unpacked, handled or
operated in environments in which sufficient precautionary measures
have been taken in respect to ESD dangers. It is also necessary that
only appropriately trained personnel (such as electricians, technicians
and engineers) handle and/or operate these products. Moreover,
PHYTEC products should not be operated without protection circuitry
if connections to the product’s pin header rows are longer than 3 m.

phyCORE-MPC5200B FPGA
PHYTEC Messtechnik GmbH 2006 L-672e_0
PHYTEC products fulfill the norms of the European Union's Directive
for Electro Magnetic Conformity only in accordance to the
descriptions and rules of usage indicated in this hardware manual
(particularly in respect to the pin header rows or connectors, power
connector and serial interface to a host-PC).
Implementation of PHYTEC products into target devices, as well as
user modifications and extensions of PHYTEC products, is subject to
renewed establishment of conformity to, and certification of, Electro
Magnetic Directives. Users should ensure conformance following any
modifications to the products as well as implementation of the
products into target systems.
The phyCORE-MPC5200B is one of a series of PHYTEC Single
Board Computers that can be populated with different controllers and,
hence, offers various functions and configurations. PHYTEC supports
common 8-, 16- and selected 32-bit controllers on two types of Single
Boards Computers:
(1) as the basis for Rapid Development Kits which serve as a
reference and evaluation platform
(2) as insert-ready, fully functional phyCORE OEM modules, which
can be embedded directly into the user’s peripheral hardware,
design.
PHYTEC's microcontroller modules allow engineers to shorten
development horizons, reduce design costs and speed project concepts
from design to market.

Introduction
PHYTEC Messtechnik GmbH 2006 L-672e_0 3
1Introduction
The phyCORE-MPC5200B belongs to PHYTEC's phyCORE Single
Board Computer module family. The phyCORE SBCs represent the
continuous development of PHYTEC Single Board Computer
technology. Like its mini-, micro- and nanoMODUL predecessors, the
phyCORE boards integrate all core elements of a microcontroller
system on a sub-miniature board and are designed in a manner that
ensures their easy expansion and embedding in peripheral hardware
developments.
As independent research indicates that approximately 70 % of all EMI
(Electro Magnetic Interference) problems stem from insufficient
supply voltage grounding of electronic components in high frequency
environments the phyCORE board design features an increased pin
package. The increased pin package allows dedication of
approximately 20 % of all pin header connectors on the phyCORE
boards to Ground. This improves EMI and EMC characteristics and
makes it easier to design complex applications meeting EMI and EMC
guidelines using phyCORE boards even in high noise environments.
phyCORE boards achieve their small size through modern SMD
technology and multi-layer design. In accordance with the complexity
of the module, 0402-packaged SMD and laser-drilled Microvias
components are used on the boards, providing phyCORE users with
access to this cutting edge miniaturization technology for integration
into their own design.
The phyCORE-MPC5200B is a subminiature (77 x 84 mm) insert-
ready Single Board Computer populated with Freescale's PowerPC
MPC5200 microcontroller. Its universal design enables its insertion in
a wide range of embedded applications. All controller signals and
ports extend from the controller to high-density (0.635 mm) Molex pin
header connectors aligning two sides of the board, allowing it to be
plugged like a "big chip" into a target application.

phyCORE-MPC5200B FPGA
PHYTEC Messtechnik GmbH 2006 L-672e_0
Precise specifications for the controller populating the board can be
found in the applicable controller User's Manual or Data Sheet. The
descriptions in this manual are based on the MPC5200 controller. No
description of compatible microcontroller derivative functions is
included, as such functions are not relevant for the basic functioning
of the phyCORE-MPC5200B.
The phyCORE-MPC5200B offers the following features:
Single Board Computer in subminiature form factor
(77 x 84 mm) according to phyCORE specifications
all applicable controller and other logic signals extend to two
high-density 200-pin Molex connectors
processor: Freescale embedded PowerPC MPC5200B
single 3.3 V (max. 2.2 A) supply voltage
Internal Features of the MPC5200:
e300 core
— 760 MIPS at 400 MHz (-40 to +85 oC)
— 32 k Instruction cache, 32 k data cache
— double precision FPU
— instruction and data MMU
SDRAM / DDR memory interface
— up to 132-MHz operation
— SDRAM and DDR SDRAM support
— 256 MByte addressing range per CS, two CS available
Flexible multi-function external bus interface
Peripheral Component Interconnect (PCI) controller
ATA controller
BestComm DMA subsystem
6 Programmable Serial Controllers (PSC), configurable for the
following functions:
Fast Ethernet Controller (FEC)
— Supports 100Mbps IEEE 802.3 MII, 10 Mbps IEEE 802.3 MII
Universal Serial Bus controller (USB)
— USB Revision 1.1 host
two Inter-Integrated Circuit interfaces (I2C)

Introduction
PHYTEC Messtechnik GmbH 2006 L-672e_0 5
Serial Peripheral Interface (SPI)
dual CAN 2.0 A/B controller (MSCAN)
J1850 Byte Data Link Controller (BDLC)
Test/debug features
— JTAG (IEEE 1149.1 test access port)
— Common On-chip Processor (COP) debug port
Memory Configuration1:
DDR SDRAM: 64 MByte to 128 MByte
Flash: 32 MByte to 64 MByte Intel Strata Flash memory, 32-bit
memory width, only asynchronous (J3) devices are supported
SRAM: up to 2 MBytes, 16-bit data bus width, with battery backup
support
I2C memory: 4 kByte EEPROM
Other Board-Level Features:
optional: Altera Cyclone 2 FPGA (EPC2C8) with up to 64 MByte
DDR-RAM for video data and 256 MByte NAND Flash as mass
storage device.
two UART ports, RS-232 interfaces (RxD/TxD)
two CAN ports, on-board CAN transceivers; also configurable as
TTL
one 10/100 Mbit/s Ethernet port via optional Micrel PHY
I2C Real-Time Clock with calendar and alarm function
industrial temperature range (-40…+85C)
1: Please contact PHYTEC for more information about additional module configurations.

phyCORE-MPC5200B FPGA
PHYTEC Messtechnik GmbH 2006 L-672e_0
1.1 Block Diagram
Figure 1: Block Diagram phyCORE-MPC5200B
Memor Management
Unit
BestCom I/O Sub-
system
Floating Point
Unit
+1V2
+1V5
+2V5
+3V3 Power +3V3@2,2A
VBAT +3V for RTC and SRAM
I
2
C Bus 0
10/100 Mbit Ethernet
/IRQRTC
PSC1 could be used as AC97 codec
UART3 RXD3 / TXD3
UART0 RXD6 / TXD6
CAN0
CAN1
CAN1 TTL
CAN0 TTL
32 to 64MB
FLASH-
EEPROM
32-bit
I
2
C RTC
Clock
Calendar
Alarm
I
2
C Memory
FRAM or
EEPROM
CAN Transceiver
CAN Transceiver
PS3 (UART + SPI)
PSC1 (AC97)
MPC5200B
33 MHz Quartz
p
h
y
C
O
R
E
-
C
o
n
n
e
c
t
o
r
64 to 128MB
DDR-SDRAM
133MHz
32-bit
FPG
A
Alterra
Cyclone 2
PSC2 (CAN1/2)
PSC 6 (UART)
Powe
r
Supply
UART3 TTL
Ethernet PHY
FEC FastEthernet
UART6 TTL
I2C 0
DDR SDRAM Bus
LocalPlus Bus
462MHz core clock
JTAG port for re-programming
LocalPlus-Bus:
External Bus Interface
PCI Bus V2.2 (33/66MHz)
A
TA Interface
COP/JTAG COP/JTAG Debug / Test Port
FPU
MMU
DMA
MPC603e
series e300
core
16k D-cache
16k I-cache
SPI Bus
Timer
ATA_CS Timer Outputs (PWM)
/CS Signals for ATA Interface
I2C 1
RS232 Transceiver
RS232 Transceiver
256MByte
NAND-
Flash
32 to 64MByte
Video-RAM
(DDR 16-bit)
up to 2 MByte
SRAM
16-bit
FPGA
config device
I
2
C Bus 1
USB Host USB 1.1 Host Interface

Introduction
PHYTEC Messtechnik GmbH 2006 L-672e_0 7
1.2 View of the phyCORE-MPC5200B
RN3
R33
CB121
R69
R36
CB310
U18
CB330
TP1
J16
RN10
C56
CB341
U16
CB337
C55
CB342
R38
TP11
CB344
RN20
CB124
U11
CB703
R67
RN8
CB335
J9
C58
CB701
R70
J15 RN14
RN7
CB707
J3
C59
U14
U9
X2
RN6
RN12
RN1
RN19
R31
CB314
CB334
C18
U2
U27
CB308
C32
CB302
R2
C8
TP9
J10
R30
J8
XT2
U21
CB708
R7
J1
C38
R3
U20
J17
TP5
C15
R34
R32
CB313
R29
RN21
CB123
CB304
U17
CB343
TP4
CB303
C5
RN9
J4
CB702
CB339
U15
RN5
CB309
R68
XT3
CB331
RN18
U10
R83
U1
C7
CB307
U12
CB709
J13
CB332
CB700 RN4
C2
U28
TP2
TP10
J7
U13
R39
C4
RN17
C33
TP7
R82
L1
U3 R37
J11
C3 RN15
CB312
CB333
RN16
J12
J2
RN13
CB705
C17
J14
CB311
R1
CB706
J5
R8
CB340
CB301
CB704
R6
R35
C29
TP8
R40
R28
RN11
J6
CB305
CB306
C1
CB338
RN2
R66
CB122
CB300
TP3
X1
J18
J19
CB120
CB336
NAND-Flash
Video-RAM DDR-RAM
DDR-RAM
PHY
Flash
Flash
MPC5200B
Alterra
Cyclone 2
SRAM

phyCORE-MPC5200B FPGA
PHYTEC Messtechnik GmbH 2006 L-672e_0
CB603
R18
L4
U4
C62
CB252
R54
C50
CB804
R53
Q1
R10
C28
C13
R64
D2
C24
L9
L10
C49
CB253
R81
R60
CB651
CB602
C36
R65
R12
C31
C54
C21
CB259
CB157
R44
R71
R26
C16
U5
D4
CB155
CB600
C67
CB850
CB851
CB127
R23
CB152
CB201 C11
C40
R4
CB150
D1
D3
U22 R74
CB106
R13
C30
R17
R75 C48
CB251
C9
R15
R57
CB202
C20
CB126
C64
R72
R80
R76
C65
C45
C39
CB102
CB206
C43 C44
CB156
CB205
C61
R61
L2
R22
CB109
C35
R20
C23
CB254
U25
CB256
C52
CB159
R62
CB108
C63
CB801
R5
R48
C12
C6
CB100
R25
C60
U23
CB852
Q2
CB154
R55
C26
R24
R19
CB255
R9
L6
CB854
C41
CB652
R58
U6
C66
CB104
C10
U7
CB209
R47
CB258
CB107
CB653
C34
R42
R51
CB650
R43
R50
C22
C42
CB802
R16
CB800 R63
R21
C19
L5
L8
C47
CB853
C51
C27
CB128
U26
D5
CB803
CB203
L3
L11
R27
R77
R85
CB208
CB604
CB153
CB103
R52 U24
R84
CB158
CB125
CB601
C46 CB101
CB129
L7
CB207
R45
C57
CB200
R46
CB204
R78
C14
C25
R59
R41
R11
CB105
CB151
CB257
CB654
XT1
R73
R79
R56
R14
D6
R49
C53
CB250
Figure 2: View of the phyCORE-MPC5200B Revision 1238.0

Introduction
PHYTEC Messtechnik GmbH 2006 L-672e_0 9
1.3 Minimum Requirements to Operate the
phyCORE-MPC5200B
Basic operation of the phyCORE-MPC5200B only requires supply of
a +3.3 V input voltage and the corresponding GND connection.
These supply pins are located at the phyCORE-connector X3:
+3V3 X3 1C, 2C, 4C, 5C, 1D, 2D, 4D, 5D
GND X3 3C, 3D, 7C, 9D, 12C, 14D
Caution:
We recommend connecting all available +3V3 input pins to the power
supply system on a custom carrier board housing the
phyCORE-MPC5200B and at least the matching number of GND pins
neighboring the +3V3 pins.
In addition, proper implementation of the phyCORE module into a
target application also requires connecting all GND pins neighboring
signals that are being used in the application circuitry.
Please refer to section 4 for more information.

phyCORE-MPC5200B FPGA
PHYTEC Messtechnik GmbH 2006 L-672e_0

Pin Description
PHYTEC Messtechnik GmbH 2006 L-672e_0 11
2Pin Description
Please note that all module connections are not to exceed their
expressed maximum voltage or current. Maximum signal input values
are indicated in the corresponding controller manuals/data sheets. As
damage from improper connections varies according to use and
application, it is the user's responsibility to take appropriate safety
measures to ensure that the module connections are protected from
overloading through connected peripherals.
Many of the phyCORE-MPC5200B pins offer alternative functions.
These alternative functions must be activated by configuring the
applicable controller registers prior to their use. Certain controller
functions are pre-configured based on the module’s design and are
shown in Table 1. Signals that are routed directly from the CPU to the
Molex connectors can configured to any available alternative function
desired by the user. In contrast, signals that are used on the phyCORE-
MPC5200 tiny as listed in Table 1 can only be used if a special
module configuration was purchased (e.g. SBC version without
Ethernet PHY, no CAN, no on-board RS-232 transceivers). Please
contact PHYTEC for more details.
Note:
The following sections of this manual assume use of the port pins
according to configuration listed in Table 1.
CPU Port Function Port_conf
Register Bits Used on phyCORE SBC
PSC1 AC97_1 01x [29:31] No
PSC2 CAN 1/2 001 [25:27] Yes (PSC2_4 = IDE Reset)
PSC3 UART3/SPI 1100 [20:23] Yes
USB USB 01 [18:19] No
Ethernet Ethernet w/ MD 0101 [12:15] Yes
Timer ATA_CS 00_11 [2:3_6:7] No
I2C I2C1 / I2C2 default Yes (I2C2 available)
PSC6 UART6 101 [9:11] Yes
Table 1: Default Port Configuration

phyCORE-MPC5200B FPGA
PHYTEC Messtechnik GmbH 2006 L-672e_0
As Figure 3 indicates, all controller signals extend to surface mount
technology (SMT) connectors (0.635 mm) lining two sides of the
module (referred to as phyCORE-connector; refer to section 11). This
allows the phyCORE-MPC5200B to be plugged into any target
application like a "big chip".
Figure 3: Pinout of the phyCORE-MPC5200B (Bottom View)
Table 2 provides an overview of the pinout of the phyCORE-
connector. The pin assignment assumes the default port configuration
depicted in Table 1. Alternative functions of the controller pins can be
found in the MPC5200B Data Sheet.
Please refer to the Freescale MPC5200 User Manual/Data Sheet for
details on the functions and features of controller signals and port
pins.
Pin Number Signal I/O Comments
Pin Row X1A
1A NC - Not connected
2A, 7A, 12A,
17A, 22A, 27A,
32A, 37A, 42A,
47A, 52A, 57A,
62A, 67A, 72A,
77A, 82A, 87A,
92A, 97A
GND - Ground 0 V
3A /IRQ3 I Interrupt input 3 of the processor.
4A /IRQ0 I Interrupt input 0 of the processor.
/ DC
X3
BA
X
3
1 1
100
11
100 10
0