Phytec phyCORE-MCF548x User manual

A product of a PHYTEC Technology Holding company
phyCORE-MCF548x
Hardware Manual
Edition January 2005

phyCORE-MCF548x
PHYTEC Messtechnik GmbH 2005 L-645e_1
In this manual are descriptions for copyrighted products that are not explicitly
indicated as such. The absence of the trademark () and copyright () symbols
does not imply that a product is not protected. Additionally, registered patents and
trademarks are similarly not expressly indicated in this manual.
The information in this document has been carefully checked and is believed to be
entirely reliable. However, PHYTEC Messtechnik GmbH assumes no
responsibility for any inaccuracies. PHYTEC Messtechnik GmbH neither gives
any guarantee nor accepts any liability whatsoever for consequential damages
resulting from the use of this manual or its associated product. PHYTEC
Messtechnik GmbH reserves the right to alter the information contained herein
without prior notification and accepts no responsibility for any damages which
might result.
Additionally, PHYTEC Messtechnik GmbH offers no guarantee nor accepts any
liability for damages arising from the improper usage or improper installation of
the hardware or software. PHYTEC Messtechnik GmbH further reserves the right
to alter the layout and/or design of the hardware without prior notification and
accepts no liability for doing so.
Copyright 2005 PHYTEC Messtechnik GmbH, D-55129 Mainz.
Rights - including those of translation, reprint, broadcast, photomechanical or
similar reproduction and storage or processing in computer systems, in whole or
in part - are reserved. No reproduction may occur without the express written
consent from PHYTEC Messtechnik GmbH.
EUROPE NORTH AMERICA
Address: PHYTEC Technologie Holding AG
Robert-Koch-Str. 39
D-55129 Mainz
GERMANY
PHYTEC America LLC
203 Parfitt Way SW, Suite G100
Bainbridge Island, WA 98110
USA
Ordering
Information: [phone] [e-mail] 1 [phone] [e-mail]
Technical
Support: [phone] [e-mail] 1 [phone] [e-mail]
Fax: [phone] [phone]
Web Site: http://www.phytec.de http://www.phytec.com
1st Edition: January 2005

Contents
PHYTEC Messtechnik GmbH 2005 L-645e_1
Preface...........................................................................................................1
1 Introduction .........................................................................................3
1.1 Block Diagram..............................................................................6
1.2 View of the phyCORE-MCF548x................................................7
1.3 Minimum Requirements to Operate the phyCORE-MCF548x....8
2 Pin Description ....................................................................................9
3 Jumpers..............................................................................................23
4 Power Requirements.........................................................................33
4.1 Voltage Supervision and Reset...................................................35
5 System Start-Up Configuration .......................................................37
6 System Memory.................................................................................39
6.1 Flash Memory.............................................................................40
6.2 DDR SDRAM.............................................................................42
6.3 Serial Memory............................................................................43
7 XPLD System Logic Device..............................................................45
7.1 XPLD Firmware Development...................................................46
8 Serial Interfaces.................................................................................47
8.1 RS-232 Interface.........................................................................47
8.2 CAN Interface.............................................................................48
8.3 BDM Debug Interface ................................................................50
8.4 Ethernet Interface .......................................................................52
8.4.1 PHY Physical Layer Transceiver ..................................52
8.4.2 MAC Address................................................................54
8.5 USB 2.0 Interface.......................................................................54
9 Real-Time Clock RTC-8564 (U16)...................................................55
10 phyCORE Development Board PCM-982 ......................................57
10.1 Concept of the phyCORE Development Board PCM-982.........57
10.2 Development Board PCM-982 Overview ..................................58
10.2.1 Connectors, Buttons, LEDs...........................................58
10.2.2 Jumpers on the phyCORE Development Board
PCM-982 .......................................................................61

phyCORE-MCF548x
PHYTEC Messtechnik GmbH 2005 L-645e_1
10.3 Functional Components on the phyCORE Development
Board PCM-982 .........................................................................63
10.3.1 Power Supply at X10.....................................................63
10.3.2 First Serial Interface at Socket P2A..............................64
10.3.3 Second Serial Interface at Socket P2B..........................64
10.3.4 First CAN Interface at Plug P1A ..................................65
10.3.5 Second CAN Interface at Plug P1B ..............................67
10.3.6 Programmable LED D29...............................................69
10.3.7 Pin Assignment Summary of the phyCORE, the
Expansion Bus and the Patch Field...............................69
10.3.8 Silicon Serial Number/Temperature Sensor..................78
10.3.9 BDM Port X2 ................................................................79
10.3.10 Technical Specification of the Development Board .....80
10.3.11 Release Notes................................................................82
11 Technical Specifications of the phyCORE-MCF548x ...................83
12 Hints for Handling the Module........................................................86
13 Design Considerations - Check List ................................................87
14 Revision History................................................................................88
15 Component Placement Diagram......................................................89
A Appendices.........................................................................................90
A.1 Release Notes .............................................................................90
Index............................................................................................................91

Contents
PHYTEC Messtechnik GmbH 2005 L-645e_1
Index of Figures
Figure 1: Block Diagram phyCORE-MCF548x .....................................6
Figure 2: View of the phyCORE-MCF548x Revision 1229.0
(M 1.5:1) ..................................................................................7
Figure 3: Pinout of the phyCORE-MCF548x (Bottom View)................9
Figure 4: Numbering of the Jumper Pads..............................................23
Figure 5: Location of the Jumpers (Controller Side)and Default
Settings (phyCORE-MCF548x Standard Version) ...............23
Figure 6: Location of the Jumpers (Connector Side) and Default
Settings (phyCORE-MCF548x Standard Version) ...............24
Figure 7: Power Supply Diagram..........................................................34
Figure 8: Serial Memory I2C Slave Address.........................................44
Figure 9: XPLD Configuration..............................................................46
Figure 10: BDM Interface Card Edge Header X1 (Top View)...............50
Figure 11: View of the Development Board PCM-982 ..........................60
Figure 12: Numbering of Jumper Pads....................................................61
Figure 13: Location of the Jumpers (View of the Component Side) ......61
Figure 14: Connecting the Supply Voltage at X10 .................................63
Figure 15: Pin Assignment of the DB-9 Socket P2A as First RS-232
(Front View)...........................................................................64
Figure 16: Pin Assignment of the DB-9 Socket P2B as Second
RS-232 (Front View) .............................................................64
Figure 17: Pin Assignment of the DB-9 Plug P1A (CAN Transceive
on phyCORE-MCF548x, Front View) ..................................65
Figure 18: Pin Assignment of the DB-9 Plug P1A (CAN Transceiver
on Development Board with Galvanic Separation)...............66
Figure 19: Pin Assignment of the DB-9 Plug P1B (CAN Transceiver
on phyCORE-MCF548x, Front View) ..................................67
Figure 20: Pin Assignment of the DB-9 Plug P2B (CAN Transceiver
on Development Board with Galvanic Separation)...............68
Figure 21: Pin Assignment Scheme of the Expansion Bus.....................70
Figure 22: Pin Assignment Scheme of the Patch Field...........................70

phyCORE-MCF548x
PHYTEC Messtechnik GmbH 2005 L-645e_1
Figure 23: Connecting the DS18B20 Temperature Sensor with
Silicon Serial Number ...........................................................78
Figure 24: Pin Assignment of the DS2401 Silicon Serial Number.........78
Figure 25 Physical Dimensions of the Development Board
PCM-982................................................................................80
Figure 26: Physical Dimensions..............................................................83
Figure 27: phyCORE-MCF548x Component Placement, Top View.....89
Figure 28: phyCORE-MCF548x Component Placement,
Bottom View..........................................................................89
Index of Tables
Table 1: Pinout of the phyCORE-Connector X2 .................................21
Table 2: Jumper Settings......................................................................31
Table 3: System Start-up Configuration ..............................................37
Table 4: System Start-up Configuration Test/Debug Port...................38
Table 5: Choice of Flash Memory Devices and Manufacturers ..........40
Table 6: DDR SDRAM Device Selection............................................42
Table 7: Serial Memory Options for U15............................................43
Table 8: Serial Memory I2C Address (Examples)................................44
Table 9: 26-Pin BDM Connector (X1) and Corresponding Pins on
the phyCORE-Connector (X2) ..............................................51
Table 10: Signal Definition PHY 0 Ethernet Port (U17).......................53
Table 11: Signal Definition PHY 1 Ethernet Port (U18).......................53
Table 12: Signal Definition USB 2.0 Port .............................................54
Table 13: Development Board Jumper Overview..................................62
Table 14: Jumper Configuration for CAN Plug P1A Using the CAN
Transceiver on the phyCORE-MCF548x ..............................65
Table 15: Jumper Configuration for CAN Plug P1A Using the CAN
Transceiver on the Development Board with Galvanic
Separation...............................................................................66
Table 16: Jumper Configuration for CAN Plug P2B Using the CAN
Transceiver on the phyCORE-MCF548x ..............................67

Contents
PHYTEC Messtechnik GmbH 2005 L-645e_1
Table 17: Jumper Configuration for CAN Plug P2B using the CAN
Transceiver on the Development Board with Galvanic
Separation.................................................................................68
Table 18: Signal Pin Assignment for the phyCORE-MCF548x /
Development Board / Expansion Board...................................76
Table 19: Pin Assignment Power Supply for the phyCORE-MCF548x /
Development Board / Expansion Board...................................77
Table 20: Pin Assignment of the BDM Pin Header X2 ...........................79
Table 21: Technical Data of the Development Board PCM-982 .............81
Table 22: Technical Data of the phyCORE-MCF548x............................84

phyCORE-MCF548x
PHYTEC Messtechnik GmbH 2005 L-645e_1

Preface
PHYTEC Messtechnik GmbH 2005 L-645e_1 1
Preface
This phyCORE-MCF548x Hardware Manual describes the board’s
design and functions. Precise specifications for the Freescale
MCF548X microcontroller series can be found in the enclosed
MCF548X microcontroller Data Sheet/User's Manual. If software is
included please also refer to additional documentation for this
software.
In this hardware manual and in the attached schematics, low active
signals are denoted by a "/" in front of the signal name (i.e.: /RD). A
"0" indicates a logic-zero or low-level signal, while a "1" represents a
logic-one or high-level signal. The MSB and LSB of the data and
address busses shown in the circuit diagram are based on the
conventions of Freescale. Accordingly, D0 and A0 represent the LSB,
while D31 and A31 represent the MSB. These conventions are also
valid for the parallel I/O signals.
Declaration regarding Electro Magnetic Conformity
of the PHYTEC phyCORE-MCF548x
PHYTEC Single Board Computers (henceforth products) are designed
for installation in electrical appliances or as dedicated Evaluation
Boards (i.e.: for use as a test and prototype platform for
hardware/software development) in laboratory environments.
Note:
PHYTEC products lacking protective enclosures are subject to
damage by ESD and, hence, may only be unpacked, handled or
operated in environments in which sufficient precautionary measures
have been taken in respect to ESD dangers. It is also necessary that
only appropriately trained personnel (such as electricians, technicians
and engineers) handle and/or operate these products. Moreover,
PHYTEC products should not be operated without protection circuitry
if connections to the product’s pin header rows are longer than 3 m.

phyCORE-MCF548x
PHYTEC Messtechnik GmbH 2005 L-645e_1
2
PHYTEC products fulfill the norms of the European Union’s Directive
for Electro Magnetic Conformity only in accordance to the
descriptions and rules of usage indicated in this hardware manual
(particularly in respect to the pin header rows or connectors, power
connector and serial interface to a host-PC).
Implementation of PHYTEC products into target devices, as well as
user modifications and extensions of PHYTEC products, is subject to
renewed establishment of conformity to, and certification of, Electro
Magnetic Directives. Users should ensure conformance following any
modifications to the products as well as implementation of the
products into target systems.
The phyCORE-MCF548x is one of a series of PHYTEC Single Board
Computers that can be populated with different controllers and, hence,
offers various functions and configurations. PHYTEC supports
common 8-, 16- and selected 32-bit controllers on two types of Single
Boards Computers:
(1) as the basis for Rapid Development Kits which serve as a
reference and evaluation platform
(2) as insert-ready, fully functional micro-, mini- and phyCORE
OEM modules, which can be embedded directly into the user’s
peripheral hardware, design.
PHYTEC's microcontroller modules allow engineers to shorten
development horizons, reduce design costs and speed project concepts
from design to market.

Introduction
PHYTEC Messtechnik GmbH 2005 L-645e_1 3
1Introduction
The phyCORE-MCF548x belongs to PHYTEC’s phyCORE Single
Board Computer module family. The phyCORE SBCs represent the
continuous development of PHYTEC Single Board Computer
technology. Like its mini-, micro- and nanoMODUL predecessors, the
phyCORE boards integrate all core elements of a microcontroller
system on a sub-miniature board and are designed in a manner that
ensures their easy expansion and embedding in peripheral hardware
developments.
As independent research indicates that approximately 70 % of all EMI
(Electro Magnetic Interference) problems stem from insufficient
supply voltage grounding of electronic components in high frequency
environments the phyCORE board design features an increased pin
package. The increased pin package allows dedication of
approximately 20 % of all pin header connectors on the phyCORE
boards to Ground. This improves EMI and EMC characteristics and
makes it easier to design complex applications meeting EMI and EMC
guidelines using phyCORE boards even in high noise environments.
phyCORE boards achieve their small size through modern SMD
technology and multi-layer design. In accordance with the complexity
of the module, 0402-packaged SMD and laser-drilled Microvias
components are used on the boards, providing phyCORE users with
access to this cutting edge miniaturization technology for integration
into their own design.
The phyCORE-MCF548x is a subminiature (70 x 57 mm) insert-ready
Single Board Computer populated with Freescale’s ColdFire
MCF548X microcontroller. Its universal design enables its insertion in
a wide range of embedded applications. All controller signals and
ports extend from the controller to high-density (0.635 mm) Molex pin
header connectors aligning two sides of the board, allowing it to be
plugged like a "big chip" into a target application.

phyCORE-MCF548x
4PHYTEC Messtechnik GmbH 2005 L-645e_1
Precise specifications for the controller populating the board can be
found in the applicable controller User’s Manual or Data Sheet. The
descriptions in this manual are based on the MCF548X controller. No
description of compatible microcontroller derivative functions is
included, as such functions are not relevant for the basic functioning
of the phyCORE-MCF548x.
The phyCORE-MCF548x offers the following features:
•Single Board Computer in subminiature form factor
(70 x 57 mm) according to phyCORE specifications
•all applicable controller and other logic signals extend to two
high-density 160-pin Molex connectors
•processor: Freescale embedded ColdFire MCF548X (200 MHz
clock)
Internal Features of the MCF548X:
•32-bit ColdFire V4e core, 200 MHz CPU speed
•32 kByte instruction cache
•32 kByte data cache
•MMU with 32 entries
•64-bit FPU double precision IEEE-754
•EMAC unit
•DMA unit
•Encryption unit
•32 kByte SRAM
•Watchdog
•Two system timers
•Four 32-bit general purpose timers
•Four UARTs
•SPI interfaces
•Two CAN 2.0B interfaces
•I²C Maser/Slave controller
•Two Fast Ethernet controllers
•USB2.0 Slave
•PCI bus
•BDM test/debug port

Introduction
PHYTEC Messtechnik GmbH 2005 L-645e_1 5
Memory Configuration1:
•DDR SDRAM: 64 MByte to 128 MByte
•Flash: 32 MByte to 64 MByte Intel Strata Flash memory, 32-Bit
memory width, synchronous (K3) or asynchronous (J3) devices are
supported
•I2C Memory: 4 kByte EEPROM (up to 32 kByte, alternatively I2C
FRAM, I2C SRAM)
Other Board-Level Features:
•Four UART ports
RS-232 interfaces (RxD/TxD/RTS/CTS) and two TTL-level
interfaces
•Two CAN ports, on-board CAN transceivers; also configurable as
TTL
•Two 10/100Mbit Ethernet ports
•Logic Device Lattice ispXPLD 5000 family
256/512/768 Macrocells and 128/256/384 kBit SRAM, in-system-
programmable
For applications like:
single-, dual-port RAM or FIFO
Timer, PWM, CapComp etc.
Decoder, Encoder
IP core
application-specific logic
special bus interfaces
multi-purpose I/O signals etc.
•PCI 2.2 bus
•SPI bus, Synchronous Serial Interface with two Chip Selects
•I2C bus
•I2C Real-Time Clock with calendar and alarm function
•12-bit ADC, 8 channels, connected to I2C Bus
•12-bit DAC, 1 channel, connected to I2C Bus
•JTAG/BDM test/debug port
•Industrial temperature range (-40…+85°C)
1: Please contact PHYTEC for more information about additional module configurations.

phyCORE-MCF548x
6PHYTEC Messtechnik GmbH 2005 L-645e_1
1.1 Block Diagram
Figure 1: Block Diagram phyCORE-MCF548x
Memor Management
Unit
Multiply and
Accumulate Unit
Direct Memory
Access Controller
Floating Point
Unit
Security
Engine
Timer Unit
6 Timer/Watchdog
+1V5
+2V5
+3V3 Power +3V3@1A
VBat +3V for RTC
I2C-Bus
Use specific programmable I/O:
Flexible Bus interface
Control signals
Multi Purpose I/O 5V-tolerant
Embedded Dual-Port SRAM, FIFO
LVTTL, LVCMOS etc. Level
LVDS Signals
10/100 Mbit Ethernet 0
/IRQRTC
UART0 RXD0/TXD
UART1 RXD1/TXD1
UART0 TTL
FlexCAN0
FlexCAN1
FlexCAN1 TTL
FlexCAN0 TTL
VPD
32 to 64MB
FLASH-
EEPROM
32-bit
I
2
C-RTC
Clock
Calendar
Alarm
I
2
C-Memory
FRAM or
EEPROM or
SRAM
RS232 Transceiver
CAN Transceiver
CAN Transceiver
FlexCAN 0
FlexCAN 1
PSC UART 2
PSC UART 0
MCF5485
50 MHz Quarz
p
h
y
C
O
R
E
-
C
o
n
n
e
c
t
o
r
64 to 128MB
DDR-SDRAM
200MHz
32-bit
XPLD
Logic Device
Free User
Logic and I/O
RS232 TransceiverPSC UART 1
PSC UART 3
Power
Supply
UART1 TTL
Ethernet PHY 0
Ethernet PHY 1 10/100 Mbit Ethernet 1
FEC FastEthernet 0
FEC FastEthernet 1
UART2 TTL
UART3 TTL
I2C
PCI 2.2 Bus
DDR SDRAM Bus
FlexBus
PLL 200MHz Clock
JTAG port for re-programming
PCI Bus V2.2
Clock Ratio 1 or 1/2
50MHz CPU-/System Clock
BDM/JTAG BDM/JTAG Debug-/Test Port
FPU
MMU
EMAC
DMA
SEC
ColdFire
32.Bit
V4e Core
CTM
32k D-cache
32k I-cache
32k SRAM
DSPI SPI Bus 25MHz
MPIO Multi Purpose I/O
ADC
12-Bit
8 channels
I2C Bus
DAC
12-Bit
1 channel
I2C Bus
12-Bit ADC, 8 channel
12-Bit DAC, 1 channel

Introduction
PHYTEC Messtechnik GmbH 2005 L-645e_1 7
1.2 View of the phyCORE-MCF548x
OZ1
J15
J5 J6
J36
U7
XT2
J19
U6
U22
J3
U16
X1
U1
U5
J21
J28
J12
U15
U19
J7 U10
J11
J22
J14
J18
J37
U11
J2
J8
U21
J13
J1
U14
J38
J35
J27
U17
U13
J10
J17
U12
J23
J4
J24
J16
ColdFire MCF548x XPLD
BDM
Flash
Flash
Phy
Pin 1
PCB 1229.0
PHYTEC
U9
XT3
Q1
U3
J30
J9
J32
U4
U20
J20
XT1
J25
J33
U23
U18
J29
U8
J26
J31
J34
X1
Pin 2
SDRAM
SDRAM
Phy
X2
1A
X2
1B
1C
1D
Figure 2: View of the phyCORE-MCF548x Revision 1229.0 (M 1.5:1)

phyCORE-MCF548x
8PHYTEC Messtechnik GmbH 2005 L-645e_1
1.3 Minimum Requirements to Operate the
phyCORE-MCF548x
Basic operation of the phyCORE-MCF548x only requires supply of a
+3V3 input voltage and the corresponding GND connection.
These supply pins are located at the phyCORE-connector X2:
+3V3 X2 1C, 2C, 1D, 2D, 4D, 5D
GND X2 3C, 3D, 7C, 9D, 12C, 14D
Caution:
We recommend connecting all available +3V3 input pins to the power
supply system on a custom carrier board housing the
phyCORE-MCF548x and at least the matching number of GND pins
neighboring the +3V3 pins.
In addition, proper implementation of the phyCORE module into a
target application also requires connecting all GND pins neighboring
signals that are being used in the application circuitry.
Please refer to section 4 for more information.

Pin Description
PHYTEC Messtechnik GmbH 2005 L-645e_1 9
2Pin Description
Please note that all module connections are not to exceed their
expressed maximum voltage or current. Maximum signal input values
are indicated in the corresponding controller manuals/data sheets. As
damage from improper connections varies according to use and
application, it is the user’s responsibility to take appropriate safety
measures to ensure that the module connections are protected from
overloading through connected peripherals.
As Figure 3 indicates, all controller signals extend to surface mount
technology (SMT) connectors (0.635 mm) lining two sides of the
module (referred to as phyCORE-connector; refer to section 11). This
allows the phyCORE-MCF548x to be plugged into any target
application like a "big chip".
Figure 3: Pinout of the phyCORE-MCF548x (Bottom View)
Many of the controller port pins accessible at the edges of the board
have been assigned alternate functions that can be activated via soft-
ware.
/ D C
X1
B A
X1
1 1
100
1 1
100 10
0

phyCORE-MCF548x
10 PHYTEC Messtechnik GmbH 2005 L-645e_1
Table 1 provides an overview of the pinout of the phyCORE-
connector , as well as descriptions of possible alternative functions.
Reset state means the behavior of the signal while the processor’s reset
input /RSTI is active.
Please refer to the Freescale MCF548x User Manual/Data Sheet for
details on the functions and features of controller signals and port
pins.
Pin Number Signal I/O Comments
Pin Row X1A
1A EXTCLK I Clock input for GCLK3 of the XPLD
10 kOhm pull-down
2A, 7A, 12A,
17A, 22A, 27A,
32A, 37A, 42A,
47A, 52A, 57A,
62A, 67A, 72A,
77A
GND - Ground 0 V
3A /IRQ7 I Interrupt input 7 of the ColdFire processor.
I GPI PIRQ7
Reset state: GPI
4A XPLD3_0 I/O XPLD GPIO
5A /FB_CS1 O Chip Select 1 of the ColdFire FlexBus.
Reset state: high
I/O PFBCS1 GPIO

Pin Description
PHYTEC Messtechnik GmbH 2005 L-645e_1 11
Pin Number Signal I/O Comments
6A
8A
9A
10A
11A
13A
14A
15A
16A
18A
19A
20A
21A
23A
24A
25A
26A
28A
29A
30A
31A
33A
34A
35A
36A
38A
39A
40A
XPLD3_1
XPLD3_3
XPLD3_5
XPLD3_6
XPLD3_8
XPLD3_11
XPLD3_13
XPLD3_14
XPLD3_16
XPLD3_19
XPLD3_21
XPLD3_22
XPLD3_24
XPLD3_27
XPLD3_29
XPLD3_30
XPLD3_32
XPLD3_35
XPLD0_1
XPLD0_2
XPLD0_4
XPLD0_7
XPLD0_9
XPLD0_10
XPLD0_12
XPLD0_15
XPLD0_17
XPLD0_18
XPLD GPIO
Freely available I/O pins to implement
application-specific functionality.
41A /FB_CS4 O Chip Select 4 of the ColdFire FlexBus.
Reset state: high
I/O PFBCS4 GPIO
43A /DACK0 O DMA acknowledge 0
I/O PDMA2 GPIO
Reset state: GPI
OTOUT0 GP timer output 0
44A /DACK1 O DMA acknowledge 1
I/O PDMA3 GPIO
Reset state: GPI
OTOUT1 GP timer output 1
45A /PCI_RESET O PCI reset
Reset state: Low
46A /PCI_BR0 I PCI bus request 0
I/O PPCIBR0 GPIO
Reset state: GPI
ITIN0 GP timer input 0

phyCORE-MCF548x
12 PHYTEC Messtechnik GmbH 2005 L-645e_1
Pin Number Signal I/O Comments
48A /PCI_BR1 I PCI bus request 1
I/O PPCIBR1 GPIO
Reset state: GPI
ITIN1 general purpose timer input 1
49A /PCI_BR2 I PCI bus request 2
I/O PPCIBR0 GPIO
Reset state: GPI
ITIN2 general purpose timer input 2
50A /PCI_BR3 I PCI bus request 3
I/O PPCIBR3 GPIO
Reset state: GPI
ITIN3 general purpose timer input 3
51A /PCI_BR4 I PCI bus request 4
I/O PPCIBR4 GPIO
Reset state: GPI
I/IRQ4 interrupt input 4 of the ColdFire processor.
53A
54A
55A
56A
59A
60A
61A
63A
71A
73A
74A
75A
76A
78A
79A
80A
PCI_AD31
PCI_AD29
PCI_AD27
PCI_AD25
PCI_AD23
PCI_AD21
PCI_AD19
PCI_AD17
PCI_AD14
PCI_AD12
PCI_AD10
PCI_AD8
PCI_AD7
PCI_AD5
PCI_AD3
PCI_AD1
I/O PCI address/data bus
Reset state: tristate
Bootstrap configuration1: FBMODE=1
Refer to A.1 for additional information.
OFBADDRx FlexBus address lines
58A /PCI_CXBE3 I/O PCI command/byte enable signal 3
Reset state: tristate
64A /PCI_CXBE2 I/O PCI command/byte enable signal 2
Reset state: tristate
65A /PCI_IRDY I/O PCI initiator ready signal
Reset state: tristate
66A /PCI_DEVSEL I/O PCI device select signal
Reset state: tristate
68A /PCI_PERR I/O PCI parity error signal
Reset state: tristate
69A /PCI_SERR I/O PCI system error signal
Reset state: tristate
70° /PCI_CXBE1 I/O PCI command/byte enable signal 1
Reset state: tristate
1Refer to Table 3 for additional information to the system’s start-up configuration.