Quectel EG21-G Guide

EG21-G
Reference Design
LTE Standard Module Series
Rev. EG21-G_Reference_Design_V1.0
Date: 2019-12-05
Status: Released
www.quectel.com

LTE Standard Module Series
EG21-G Reference Design
EG21-G_Reference_Design 1 / 8
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EG21-G Reference Design
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About the Document
Revision History
Revision
Date
Author
Description
1.0
2019-12-05
Lim PENG/
Woody WU
Initial

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EG21-G Reference Design
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Contents
About the Document...................................................................................................................................2
Contents.......................................................................................................................................................3
Figure Index.................................................................................................................................................4
1Reference Design.................................................................................................................................5
1.1. Introduction ................................................................................................................................5
1.2. Power-on/off and Resetting Scenarios......................................................................................6
1.2.1. Power-on Scenario...........................................................................................................6
1.2.2. Power-off Scenario...........................................................................................................7
1.2.3. Resetting Scenario...........................................................................................................8
1.3. Schematics ................................................................................................................................8

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Figure Index
FIGURE 1: TIMING OF TURNING ON MODULE ............................................................................................... 6
FIGURE 2: TIMING OF TURNING OFF MODULE ............................................................................................. 7
FIGURE 3: TIMING OF RESETTING MODULE ................................................................................................. 8

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1Reference Design
1.1. Introduction
This document provides the reference design for Quectel EG21-G module. And the reference design
includes power-on/off/resetting scenarios, block diagrams of power supply and module design, UART
interfaces, (U)SIM interface, audio interfaces, etc.

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EG21-G Reference Design
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1.2. Power-on/off and Resetting Scenarios
1.2.1. Power-on Scenario
VIL≤0.5V
VH=0.8V
VBAT
PWRKEY
≥500ms
RESET_N
STATUS
(OD)
Inactive Active
UART
NOTE 1
Inactive Active
USB
≥2.5s
≥12s
≥13s
VDD_EXT
About 100ms
BOOT_CONFIG &
USB_BOOT Pins
≥100ms. After this time, the BOOT_CONFIG
pins can be set to high level by external circuit.
Figure 1: Timing of Turning on Module
1. Please make sure that VBAT is stable before pulling down PWRKEY pin. The time between them is
no less than 30ms.
2. When using MCU to control module to enter the emergency download mode, please follow the above
timing sequence. It is not recommended to pull up USB_BOOT to 1.8V before powering up VBAT.
Short the test points as shown in Figure 28 can manually force the module to enter download mode.
NOTES

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EG21-G Reference Design
EG21-G_Reference_Design 7 / 8
1.2.2. Power-off Scenario
VBAT
PWRKEY
≥29.5s
≥650ms
RUNNING Power-down procedure OFF
Module
Status
STATUS
(OD)
Figure 2: Timing of Turning off Module
1. In order to avoid damaging internal flash, please do not switch off the power supply when the module
works normally. Only after the module is shut down by PWRKEY or AT command, the power supply
can be cut off.
2. When turning off module with the AT command, please keep PWRKEY at a high level after the
execution of the command. Otherwise, the module will turn itself back on after being shut down.
NOTES

LTE Standard Module Series
EG21-G Reference Design
EG21-G_Reference_Design 8 / 8
1.2.3. Resetting Scenario
VIL≤0.5V VIH≥1.3V
VBAT
≥150ms
Resetting
Module
Status Running
RESET_N
Restart
≤460ms
Figure 3: Timing of Resetting Module
1. Please ensure that there is no large capacitance with the max value exceeding 10nF on PWRKEY
and RESET_N pins.
2. RESET_N only resets the internal baseband chip of the module and does not reset the power
management chip.
3. It is recommended to use RESET_N only when failing to turn off the module by AT+QPOWD
command or PWRKEY pin.
1.3. Schematics
The schematics illustrated in the following pages are provided for your reference only.
NOTES

A2
EG21-G Reference Design
2019/12/5
DATE
1.0
114
VER
TITLE
SIZE
PROJECT
Quectel Wireless Solutions
B
C
D
6543 21
D
C
B
A
SHEET
1
23
4
5
6
A
OF
DRAWN BY
CHECKED BY
Woody WU
Lorry XU
Power Supply Block Diagram
DC-DC
DC 5V OUT
e.g. DC 12V IN DC 3.8V @2.0A
EG21-G
MIC29302WU
MOS ON/OFF USB_VBUS
EN
VBAT_EN
SGM2019-ADJYN5G/TR DC 3.3V
SGM2019-ADJYN5G/TR DC 1.8V
CODEC_
EN
EN
VDD_EXT
MIC29302WU
EN
ALC5616
TLV320AIC3104
or
Codec
VBUS_CTRL EN
POWER_EN
SD card
MOS ON/OFF
EN
DC 3.3V @0.8A
SD_PWR_EN
SGMII
DC 3.3V @0.8A
51K