Quectel EG21-G Guide

EG21-G
Reference Design
LTE Standard Module Series
Rev. EG21-G_Reference_Design_V1.0
Date: 2019-12-05
Status: Released
www.quectel.com

LTE Standard Module Series
EG21-G Reference Design
EG21-G_Reference_Design 1 / 8
Our aim is to provide customers with timely and comprehensive service. For any
assistance, please contact our company headquarters:
Quectel Wireless Solutions Co., Ltd.
Building 5, Shanghai Business Park Phase III (Area B), No.1016 Tianlin Road, Minhang District, Shanghai,
China 200233
Tel: [phone]
Email: [email protected]om
Or our local office. For more information, please visit:
http://www.quectel.com/support/sales.htm
For technical support, or to report documentation errors, please visit:
http://www.quectel.com/support/technical.htm
Or email to: [e-mail]
GENERAL NOTES
QUECTEL OFFERS THE INFORMATION AS A SERVICE TO ITS CUSTOMERS. THE INFORMATION
PROVIDED IS BASED UPON CUSTOMERS’ REQUIREMENTS. QUECTEL MAKES EVERY EFFORT
TO ENSURE THE QUALITY OF THE INFORMATION IT MAKES AVAILABLE. QUECTEL DOES NOT
MAKE ANY WARRANTY AS TO THE INFORMATION CONTAINED HEREIN, AND DOES NOT ACCEPT
ANY LIABILITY FOR ANY INJURY, LOSS OR DAMAGE OF ANY KIND INCURRED BY USE OF OR
RELIANCE UPON THE INFORMATION. ALL INFORMATION SUPPLIED HEREIN IS SUBJECT TO
CHANGE WITHOUT PRIOR NOTICE.
COPYRIGHT
THE INFORMATION CONTAINED HERE IS PROPRIETARY TECHNICAL INFORMATION OF
QUECTEL WIRELESS SOLUTIONS CO., LTD. TRANSMITTING, REPRODUCTION, DISSEMINATION
AND EDITING OF THIS DOCUMENT AS WELL AS UTILIZATION OF THE CONTENT ARE
FORBIDDEN WITHOUT PERMISSION. OFFENDERS WILL BE HELD LIABLE FOR PAYMENT OF
DAMAGES. ALL RIGHTS ARE RESERVED IN THE EVENT OF A PATENT GRANT OR
REGISTRATION OF A UTILITY MODEL OR DESIGN.
Copyright © Quectel Wireless Solutions Co., Ltd. 2019. All rights reserved.

LTE Standard Module Series
EG21-G Reference Design
EG21-G_Reference_Design 2 / 8
About the Document
Revision History
Revision
Date
Author
Description
1.0
2019-12-05
Lim PENG/
Woody WU
Initial

LTE Standard Module Series
EG21-G Reference Design
EG21-G_Reference_Design 3 / 8
Contents
About the Document...................................................................................................................................2
Contents.......................................................................................................................................................3
Figure Index.................................................................................................................................................4
1Reference Design.................................................................................................................................5
1.1. Introduction ................................................................................................................................5
1.2. Power-on/off and Resetting Scenarios......................................................................................6
1.2.1. Power-on Scenario...........................................................................................................6
1.2.2. Power-off Scenario...........................................................................................................7
1.2.3. Resetting Scenario...........................................................................................................8
1.3. Schematics ................................................................................................................................8

LTE Standard Module Series
EG21-G Reference Design
EG21-G_Reference_Design 4 / 8
Figure Index
FIGURE 1: TIMING OF TURNING ON MODULE ............................................................................................... 6
FIGURE 2: TIMING OF TURNING OFF MODULE ............................................................................................. 7
FIGURE 3: TIMING OF RESETTING MODULE ................................................................................................. 8

LTE Standard Module Series
EG21-G Reference Design
EG21-G_Reference_Design 5 / 8
1Reference Design
1.1. Introduction
This document provides the reference design for Quectel EG21-G module. And the reference design
includes power-on/off/resetting scenarios, block diagrams of power supply and module design, UART
interfaces, (U)SIM interface, audio interfaces, etc.

LTE Standard Module Series
EG21-G Reference Design
EG21-G_Reference_Design 6 / 8
1.2. Power-on/off and Resetting Scenarios
1.2.1. Power-on Scenario
VIL≤0.5V
VH=0.8V
VBAT
PWRKEY
≥500ms
RESET_N
STATUS
(OD)
Inactive Active
UART
NOTE 1
Inactive Active
USB
≥2.5s
≥12s
≥13s
VDD_EXT
About 100ms
BOOT_CONFIG &
USB_BOOT Pins
≥100ms. After this time, the BOOT_CONFIG
pins can be set to high level by external circuit.
Figure 1: Timing of Turning on Module
1. Please make sure that VBAT is stable before pulling down PWRKEY pin. The time between them is
no less than 30ms.
2. When using MCU to control module to enter the emergency download mode, please follow the above
timing sequence. It is not recommended to pull up USB_BOOT to 1.8V before powering up VBAT.
Short the test points as shown in Figure 28 can manually force the module to enter download mode.
NOTES

LTE Standard Module Series
EG21-G Reference Design
EG21-G_Reference_Design 7 / 8
1.2.2. Power-off Scenario
VBAT
PWRKEY
≥29.5s
≥650ms
RUNNING Power-down procedure OFF
Module
Status
STATUS
(OD)
Figure 2: Timing of Turning off Module
1. In order to avoid damaging internal flash, please do not switch off the power supply when the module
works normally. Only after the module is shut down by PWRKEY or AT command, the power supply
can be cut off.
2. When turning off module with the AT command, please keep PWRKEY at a high level after the
execution of the command. Otherwise, the module will turn itself back on after being shut down.
NOTES

LTE Standard Module Series
EG21-G Reference Design
EG21-G_Reference_Design 8 / 8
1.2.3. Resetting Scenario
VIL≤0.5V VIH≥1.3V
VBAT
≥150ms
Resetting
Module
Status Running
RESET_N
Restart
≤460ms
Figure 3: Timing of Resetting Module
1. Please ensure that there is no large capacitance with the max value exceeding 10nF on PWRKEY
and RESET_N pins.
2. RESET_N only resets the internal baseband chip of the module and does not reset the power
management chip.
3. It is recommended to use RESET_N only when failing to turn off the module by AT+QPOWD
command or PWRKEY pin.
1.3. Schematics
The schematics illustrated in the following pages are provided for your reference only.
NOTES

A2
EG21-G Reference Design
2019/12/5
DATE
1.0
114
VER
TITLE
SIZE
PROJECT
Quectel Wireless Solutions
B
C
D
6543 21
D
C
B
A
SHEET
1
23
4
5
6
A
OF
DRAWN BY
CHECKED BY
Woody WU
Lorry XU
Power Supply Block Diagram
DC-DC
DC 5V OUT
e.g. DC 12V IN DC 3.8V @2.0A
EG21-G
MIC29302WU
MOS ON/OFF USB_VBUS
EN
VBAT_EN
SGM2019-ADJYN5G/TR DC 3.3V
SGM2019-ADJYN5G/TR DC 1.8V
CODEC_
EN
EN
VDD_EXT
MIC29302WU
EN
ALC5616
TLV320AIC3104
or
Codec
VBUS_CTRL EN
POWER_EN
SD card
MOS ON/OFF
EN
DC 3.3V @0.8A
SD_PWR_EN
SGMII
DC 3.3V @0.8A
51K

EG21-G
A2
Reference Design
2019/12/5
DATE
1.0
214
VER
TITLE
SIZE
PROJECT
Quectel Wireless Solutions
B
C
D
6543 21
D
C
B
A
SHEET
1
23
4
5
6
A
OF
DRAWN BY
CHECKED BY
Woody WU
Lorry XU
NOTE:
A transistor translation circuit or a level translator TXS0108EPWR provided by Texas Instruments is recommended.
Reference Design Block Diagram
EG21-G
(U)SIM
VDD_EXT
FORCE_USB_BOOT
PCM
ANT_MAIN
ADC0
ADC1
MAIN UART
I2C
ANT_MAIN
WAKEUP_IN
STATUS
NET_MODE
NET_STATUS
MCU
PWRKEYGPIO_03
GPIO_04 RESET_N
GPIO_08
GPIO_05 W_DISABLE#
GPIO_06
USB USB
3.3V/1.8V
ALC5616
TLV320AIC3104
or
(U)SIM Card
SDC2 SD Card
UART
DEBUG UART
Test Points
12-bit ADC
0.3V～VBAT_BB
Status Indication
NOTE
VBAT 3.8V, 2.0A
AP_READY
GPIO_01
GPIO_02
GPIO_07
GPIO_09
VDD
VBAT_EN
VBUS_CTRL
CODEC_POWER_EN
SD_PWR_EN
VDD_MCU
VBAT
Transistor
Circuit
Main Antenna
Handset
or
Earphone
Level Translator
AR8033-AL1B-R FC3004
SGMII
EPHY RJ45
ANT_GNSS ANT_GNSS
GNSS Antenna
ANT_DIV ANT_DIV
Rx-diversity
Antenna

1.0
EG21-G
TITLE
PROJECT
Reference Design
A2
2019/12/5
DATE314
VER
SIZE
Quectel Wireless Solutions
B
C
D
6543 21
D
C
B
A
SHEET
1
23
4
5
6
A
OF
DRAWN BY
CHECKED BY
Woody WU
Lorry XU
Module Interface
1. Keep all RESERVED and unused pins unconnected, and ensure all GND pins are connected to the ground network.
Notes:
2. Pins 73～84 are unused in the design, and can be ignored in schematic and PCB decal.
3. A common mode choke L0101 is recommended to be added in series between the module and customers' MCU in order to
Meanwhile, it is recommended to reserve the test points for upgrading the firmware over USB interface and minimize the
4. ADC pins cannot be directly connected to the module's power supply and the input voltage must not exceed VABT_BB.
5. C0101 and C0102 should be placed close to the SGMII interface of the module.
Note 3
Note 6
Note 4
EG21-G
EG21-G
Note 5
extra stubs of the trace. The two resistors should be placed close to the module.
suppress EMI spurious transmission, and should be placed close to the module.
6. Do not pull up pin1,pin5, pin40,pin136,pin137and pin138 unless the module starts up sucessfully.
Meanwhile, these pins should be served as a keepout area.
R0111 NM_0R
R0109 NM_0R
R0113 100K
R0114 100K
R0116
100K
R0115
100K
R0118 0R
R0120 0R
R0122 0R
R0124 0R
R0108 0R
R0104 0R
R0106 0R
R0102 0R
1WAKEUP_IN
2AP_READY
3RESERVED
4W_DISABLE#
5NET_MODE
6NET_STATUS
7VDD_EXT
8GND
9GND
10 USIM_GND
11 DBG_RXD
12 DBG_TXD
13 USIM_PRESENCE
14 USIM_VDD
15 USIM_DATA
16 USIM_CLK
17 USIM_RST
18 RESERVED
19 GND 20 RESET_N 21 PWRKEY 22 GND 23 SD2_INS_DET 24 PCM_IN 25 PCM_OUT 26 PCM_SYNC 27 PCM_CLK 28 SDC2_DATA3 29 SDC2_DATA2 30 SDC2_DATA1 31 SDC2_DATA0 32 SDC2_CLK 33 SDC2_CMD 34 VDD_SDIO 35 ANT_DIV 36 GND
37
RESERVED
38
RESERVED
39
RESERVED
40
RESERVED
41
I2C_SCL
42
I2C_SDA
43
RESERVED
44
ADC1
45
ADC0
46
GND
47
ANT_GNSS
48
GND
49
ANT_MAIN
50
GND
51
GND
52
GND
53
GND
54
GND
55
RESERVED 56
GND 57
VBAT_RF 58 VBAT_RF 59 VBAT_BB 60 VBAT_BB 61
STATUS 62
RI 63
DCD 64
CTS 65 RTS 66
DTR 67
TXD 68
RXD 69
USB_DP 70
USB_DM 71
USB_VBUS 72
GND
115 USB_BOOT 116 RESERVED
113
RESERVED 114 RESERVED
141 RESERVED
142 RESERVED 143
RESERVED
144
RESERVED
U0101-A
85 GND
86 GND
87 GND
88 GND
89 GND
90 GND
91 GND
92 GND
93 GND
94 GND
95 GND
96 GND
97 GND
98 GND
99 GND
100 GND
101 GND
102 GND
103 GND
104 GND
105 GND
106 GND
107 GND
108 GND
109 GND
110 GND 111
GND
112
GND
117
RESERVED
118
RESERVED
119
EPHY_RST_N
120
EPHY_INT_N
121
SGMII_MDATA
122
SGMII_MCLK
123
SGMII_TX_M
124
SGMII_TX_P
125
SGMII_RX_P
126
SGMII_RX_M
127
RESERVED
128
USIM2_VDD
129
RESERVED
130
RESERVED
131
RESERVED
132
RESERVED
133
RESERVED
134
RESERVED
135
RESERVED
136
RESERVED
137
RESERVED
138
RESERVED
139
RESERVED
140
RESERVED
U0101-B
C0101 100nF
C0102 100nF
12
34
L0101
DLM0NSN900HY2D
[6] USIM_GND
[14] DBG_RXD
[14] DBG_TXD
[6] USIM_VDD
[6] USIM_CLK
[6] USIM_RST
[6] USIM_DATA
[4,5,6,11,13,14] VDD_EXT
[14] NET_STATUS
[14] NET_MODE
[4] W_DISABLE_EG21-G
[4] AP_READY_EG21-G
[4] RESET_N
[4,14] PWRKEY
[10] ANT_DIV
[10]
ANT_MAIN
[10]
ANT_GNSS
[4,14] USB_VBUS
[6] RXD_EG21-G
[6] TXD_EG21-G
[6]
DTR_EG21-G
[6] RTS_EG21-G
[6] CTS_EG21-G
[6]
DCD_EG21-G
[6]
RI_EG21-G
[14]
STATUS
[3,5,14]
VBAT
[3,5,14]
VBAT
[6] USIM_PRESENCE
[7,8] CODEC_PCM_IN
[7,8] CODEC_PCM_OUT
[7,8] CODEC_PCM_SYNC
[7,8] CODEC_PCM_CLK
[7,8]
I2C_SDA
[14] USB_DM_TEST
[14] USB_DP_TEST
ADC0_INPUT
ADC1_INPUT
[7,8]
I2C_SCL
[14] USB_BOOT
[4] WAKEUP_IN_EG21-G
[13] SD2_INS_DET
[13] SD2_DATA3 [13] SD2_DATA2 [13] SD2_DATA1 [13] SD2_DATA0
[13] SD2_CLK
[13] SD2_CMD
[13] VDD_SDIO
[11]
USIM2_VDD
[11]
SGMII_RX_M [11]
SGMII_RX_P
[11]
SGMII_TX_P
[11]
SGMII_TX_M
[11]
SGMII_MDIO_CLK
[11]
SGMII_MDIO_DATA
[11]
EPHY_INT_N
[11]
EPHY_RST_N
[4] USB_DP
[4] USB_DM

TITLE
PROJECT
Lorry XU
Woody WU
CHECKED BY
DRAWN BY
OF
A
65432
1
SHEET
A
B
C
D
123456
D
C
B
Quectel Wireless Solutions
SIZE VER
144
1.0
DATE 2019/12/5
EG21-G
A2
Reference Design
5V power source from main board.
It is used to reset the module.
It is used to turn on or off the module.
MCU Interface
The USB_VBUS pins of MCU and EG21-G should be powered by a 5V power system for USB detection, and USB_VBUS_CTRL is used to turn on/off USB_VBUS power supply.
2. EG21-G can only work as a USB device and supports Full Speed and High Speed modes. To communicate with USB interface, MCU needs to support USB host or OTG function.
1. U0201 represents customers's MCU. The power domain of GPIO interfaces on EG21-G modules is 1.8V. If the domain on U0201's GPIO interfaces is the same, then the level translation circuit can be omitted.
Notes:
3. AP_READY is used to detect the MCU's sleep state. For more details, please refer to
It is used to wake up the module. It is used to let the module enter airplane mode.
4. WAKEUP_IN_EG21-G should be kept at low level before the module starts up successfully.
Quectel_EG21-G_Hardware_Design.
G
SD
Q0205
SI2333CDS-T1
Q0207
DTC043ZEBTL
R0204
10K
Q0202
DTC043ZEBTL
Q0201
DTC043ZEBTL
Q0206
2SC4617TLQ
R0201
4.7K
R0202
4.7K
Q0204
DTC043ZEBTL
Q0203
DTC043ZEBTL
VDD
GND
TXD
RXD
CTS
RTS
USB_VBUS
USB_D+
USB_D-
GPIO_01
GPIO_02
GPIO_03
USB_ID
GPIO_04
GPIO_05
GPIO_06
GPIO_07
GPIO_08
GPIO_09
GPIO_10
GPIO_11
GPIO_12
GPIO_13
RI
DCD
DTR
U0201
C0201
10nF
C0202
10nF
C0203
10nF
C0204
1nF
VDD_MCU
[6]
RXD
[6]
TXD
[3]
USB_DP
[3]
USB_DM
[3,4,14]
USB_VBUS
[4]
ON/OFF_MCU
[4]
RESET_MCU
[4]
VBUS_CTRL
[5,14] DC_5V [3,4,14]
USB_VBUS
[4] VBUS_CTRL
[4]
W_DISABLE_MCU
[4]
SLEEP_STATUS
[3]
RESET_N
[4] RESET_MCU
[3,14]
PWRKEY
[4] ON/OFF_MCU
[6]
CTS
[6]
RTS
[5]
VBAT_EN
[3] AP_READY_EG21-G [4]
SLEEP_STATUS
VDD_EXT VDD_EXT
[3]
W_DISABLE_EG21-G
[4] W_DISABLE_MCU
[5]
CODEC_POWER_EN
[3]
WAKEUP_IN_EG21-G
[4] WAKEUP_IN_MCU
[4]
WAKEUP_IN_MCU
[13]
SD_PWR_EN
[6]
DTR
[6]
RI
[6]
DCD

1.0
EG21-G
PROJECT TITLE
Lorry XU
Woody WU
CHECKED BY
DRAWN BY
OF
A
65432
1
SHEET
A
B
C
D
123456
D
C
B
Quectel Wireless Solutions
SIZE VER
145 DATE 2019/12/5
A2
Reference Design
DC-DC Application
Notes:
2. VBAT should be routed in star mode to VBAT_BB and VBAT_RF pins.
Power Supply Design
VBAT Design
Closed to VBAT_BB pins.
Closed to VBAT_RF pins.
1. The power supply must be able to provide sufficient current up to 2A or more.
VDD_1V8 = (R0310/R0312+1)*1.207 = 1.8V
Power Supply for PCM Codec
VDD_3.3V = (R0305/R0308+1)*1.207 = 3.3V
LDO Application
It is used when the input voltage is below 7V.
VBAT = (R0301/R0307+1)*1.24 = 3.88V
The recommended load current is greater than 10mA.
Power Supply for SGMII and SD Card
VBAT = (R0314/R0318+1)*1.24 = 3.3V
Note:
DC-DC LDO
LDO DC 1.8V
LDO DC 3.3V
Codec
LDO DC 3.3V 3.0A
EG21-G
SD Card
DC 5V OUT DC 3.8V 2.0A
e.g. DC12V IN
3. The recommended operating voltage of VBAT is 3.3V～4.3V.
The recommended load current of MIC29302WU is greater than 10mA.
Notes:
1. CODEC_POWER_EN must be at low level in order to ensure the normal output voltage of VDD_3.3V.
2. The following power-on/off sequences should be complied with to ensure the audio codec
Power-on Sequence: power on VDD_1V8 first, then VDD_3.3V.
Note 1
If VDD_3.3V power supply needs to be switched off, please keep CODEC_POWER_EN at high level.
SGMII
It is used when the input voltage is above 7V. Use a DC-DC converter to convert a high input voltage
into a 5V output, and then the LDOs will generate 3.8V, 3.3V and 1.8V typical voltages.
Power-off Sequence: power off VDD_3.3V first, then VDD_1V8.
works normally.
+
C0301
100μF
C0302
100nF
C0303
33pF
C0304
10pF
C0306
100nF
C0307
33pF
C0308
10pF
+
C0305
100μF
D0301
WS4.5D3HV
1IN
3EN
5
OUT 4
BP
2GND
U0303
SGM2019-ADJYN5G/TR
C0320
4.7μF
R0310
39K
1%
R0312
75K
1%
C0318
100nF C0321
100nF
C0322
33pF
C0319
1μF
C0315
4.7μF
R0305
73.2K
1%
R0308
42.2K
1%
C0316
100nF
C0313
1μF
C0314
100nF
1IN
3EN
5
OUT 4
BP
2GND
U0302
SGM2019-ADJYN5G/TR
C0317
33pF
R0306
10K
+
C0311
470μF
1EN
2IN
3GND
4
OUT
5ADJ
U0301
MIC29302WU
C0312
100nF
C0310
100nF
+
C0309
470μF
R0301
100K
1%
R0307
47K
1%
R0302
51K
R0303
330R
Q0301
DTC043ZEBTL
R0311
100K
R0309 0R
+
C0325
470μF
1EN
2IN
3GND
4
OUT
5ADJ
U0304
MIC29302WU
C0326
100nF
C0324
100nF
+
C0323
470μF
R0314
75K
1%
R0318
47K
1%
R0313
51K
R0315
330R
Q0304
DTC043ZE
[3,5,14]
VBAT
[3,5,14]
VBAT
VBAT
VDD_1V8
VDD_3.3V
[4,5,14] DC_5V
[4] CODEC_POWER_EN
[4,5,14] DC_5V
VBAT
[4] VBAT_EN
[4,5,14] DC_5V
[3,4,6,11,13,14] VDD_EXT
[4,5,14] DC_5V
VDD3V3
[5,7,8] VDD_1V8

TITLE
PROJECT
Lorry XU
Woody WU
CHECKED BY
DRAWN BY
OF
A
65432
1
SHEET
A
B
C
D
123456
D
C
B
Quectel Wireless Solutions
SIZE VER
146
1.0
DATE 2019/12/5
EG21-G
A2
Reference Design
(U)SIM and UART Designs
UART Translation - Transistor Solution
UART Translation - IC Solution
Notes:
(U)SIM Interface
1. There are two translation solutions: transistor solution and IC solution,
3. The transistor circuit solution is not suitable for applications with high baud rates exceeding 460Kbps.
The 1nF capacitors C0402 and C0403 can improve the signal quality.
2. The power supply voltage of VCCA should not exceed that of VCCB.
Notes:
1. U401 is recommended to be used to offer good ESD protection,
2. It is recommended to connect the (U)SIM card connector's GND to the module's USIM_GND.
3. The pull-up resistor R0401 can improve anti-jamming capability,
4. R0407～R0409 are used for debugging,
5. C0401 capacitance should be less than 1μF.
4. The RTS and DTR transistor circuits are similar to that of RXD interface.
If the ground is complete on customers' PCB, USIM_GND can be connected to PCB ground directly.
and the parasitic capacitance should not be more than 15pF.
and should be placed close to the (U)SIM card connector.
6. For more information about the layout, please refer to
For more information about TXS0108E, please refer to the datasheet from TI.
The CTS, RI and DCD transistor circuits are similar to that of TXD interface.
and C0404～C0406 are used for filtering interference of EGSM900.
and should be placed close to the (U)SIM card connector.
and IC solution is recommended to be selected.
Quectel_EG21-G_Hardware_Design.
Q0401
2SC4617TLQ
Q0402
2SC4617TLQ
R0406
10K
R0405
10K
R0403
10K
R0404
10K
C0401 100nF
1
GND
2
VPP
3
I/O
4CLK
5RST
6VCC
78 PRESENCE
J0401
(U)SIM card connector
1
2
3
4 5 6
U0401 ESDA6V8AV6
R0402
51K
C0405
33pF
C0406
33pF
C0404
33pF
R0407 0R
R0408 0R
R0409 0R
R0401
15K
C0407
100nF
R0411
120K
R0410
10K
C0408 100nF
6A5
7A6
8A7
9A8
10 OE
5A4
4A3
19
VCCB
20
B1
18
B2
14
B6
13
B7
12
B8
11
GND
3A2
2VCCA
1A1
17
B3
16
B4
15
B5
U0402
TXS0108E
C0403
1nF
C0402
1nF
[4,6] RXD [3,6]
RXD_EG21-G
VDD_EXT
VDD_EXT
[4,6] TXD [3,6]
TXD_EG21-G
VDD_EXTVDD_MCU
[3]
USIM_GND
VDD_EXTUSIM_VDD
[3] USIM_RST
[3] USIM_CLK
[3] USIM_DATA
USIM_VDD
[3] USIM_PRESENCE
VDD_EXT
VDD_EXT VDD_MCU
[3,6] TXD_EG21-G
[3,6] RXD_EG21-G
[3] RI_EG21-G
[3] DTR_EG21-G
[4,6]
TXD
[4,6]
RXD
[4]
DTR
[4]
RI
[4]
CTS
[4]
RTS
[3] CTS_EG21-G
[3] RTS_EG21-G
[3] DCD_EG21-G [4]
DCD

TITLE
PROJECT
Lorry XU
Woody WU
CHECKED BY
DRAWN BY
OF
A
65432
1
SHEET
A
B
C
D
123456
D
C
B
Quectel Wireless Solutions
SIZE VER
147
1.0
DATE 2019/12/5
EG21-G
A2
Reference Design
Audio Codec Design (ALC5616)
1. ALC5616 power-on sequence: DBVDD/I2C pull-up power/AVDD/DACREF/CPVDD -> MICVDD -> software initialization.
Notes:
2. ALC5616 power-off sequence: close codec function by software -> MICVDD -> DBVDD/I2C pull-up power/AVDD/DACREF/CPVDD.
3. EG21-G will automatically initialize the codec via I2C interface after it is turned on successfully, so all power supplies for the codec need to be powered on before that.
4. Pin AGND and DGND of ALC5616 are connected together through 0R resisitor R0703.
5. The maximum output power of the codec is 30mW when the headphone driver with 32Ω load is used.
2IN1P/DMC_DAT
3IN2P
4IN2N/JD2
5
DACREF 6
AVDD
7AGND
10
LOUTR/N
11
CPN2
12
CPP2
13
CPN1
14
CPP1
15
CPVDD
16
CPVPP
18
CPVREF
19
CPVEE
20
HPO_L
21 ADCDAT1
22 DACDAT1
23 LRCK1
26
SCL
27
SDA
28 GPIO1/IRQ1
29
DBVDD
30
DCVDD
31
MICVDD
32 MICBIAS1
8
VREF2
24 BCLK1
1JD1
9
LOUTL/P
17
HPO_R
25 MCLK
33 DGND
U0501
ALC5616
C0504
4.7μF
C0505
4.7μF
C0506
100nF
R0503 0R
C0502
4.7μF
C0503
100nF
C05112.2μF C0512100nF C05074.7μF C0508
100nF
C0510
2.2μF
C0514 2.2μF
C0516 2.2μF
C0513 4.7μF R0507
0R
R0516 NM_10K
R0517
4.7K
R0518
4.7K
C0528 4.7μF
C0523 2.2μF
C0524 2.2μF
R0509 0R
R0511 0R
R0513 0R
R0515 0R
C0526
NM
C0525
NM
C0527
NM
C0515 2.2μF
C0517 2.2μF
R0514
1K
R0506
1.5K
R0505
1K
R0508
1.5K
C0519
10μF
R0502 0R
C0518 1μF
C0520 1μF
C0521 1μF
C0522 1μF
R0510 0R
R0512 0R
R0501
0R
R0504
0R
C0509NM_33pF
C0501
NM_33pF
R0519 0R
R0520 0R
VDD_3.3V VDD_1V8
VDD_3.3V
[3,8]
I2C_SDA
[3,8]
I2C_SCL
VDD_1V8
VDD_1V8
[3,8] CODEC_PCM_OUT
[3,8] CODEC_PCM_IN
[3,8] CODEC_PCM_CLK
[3,8] CODEC_PCM_SYNC
[7] MIC+
[7] MIC-
[8,9]
SPK_P
[8,9]
SPK_N
MICBIAS
[8,9] MIC_P
[8,9] MIC_N
MICBIAS
[7]
MIC+
[7]
MIC-
VDD_1V8
[8,9]
SPK_R
[8,9]
SPK_L

1.0
EG21-G
PROJECT TITLE
A2
Reference Design
2019/12/5
DATE814
VER
SIZE
Quectel Wireless Solutions
B
C
D
6543 21
D
C
B
A
SHEET
1
23
4
5
6
A
OF
DRAWN BY
CHECKED BY
Woody WU
Lorry XU
Power on reset
Differential signals, and are connected to handset and audio power amplifier.
Left and right channels, and are connected to headset.
Delay Circuit
Audio Codec Design (TLV320AIC3104)
1. TLV320AIC3104 power-on sequence: IOVDD -> AVDD/DRVDD -> DVDD -> software initialization.
Notes:
2. The RC delay circuit, which is assembled with C0621 and R0608, is used to ensure that the power-on time difference between AVDD and DVDD is within 5ms.
4. EG21-G will automatically initialize the codec via I2C interface after it is turned on successfully,
3. The RESET pin must be driven at low level for at least 10ns after all power supplies for TLV320AIC3104 are at their specified values.
5. The AGND and DGND of TLV320AIC3104 are connected together through 0R resisitor R0703 in Sheet 7.
so all power supplies for the codec need to be powered on before that.
6.The maximum output power of the codec is 15mW when the surround stereo headphone driver with 32Ω load is used, and is 30mW when the surround stereo
headphone driver with 16Ω load is used.
1
MCLK 2
BCLK 3
WCLK
4
DIN
5
DOUT
6
DVSS
7
IOVDD
8
SCL 9
SDA
10 MIC1LP/LINE1LP
11 MIC1LM/LINE1LM
12 MIC1RP/LINE1RP
13 MIC1RM/LINE1RM
14 MIC2L/LINE2L/MICDET
15 MICBIAS
16 MIC2R/LINE2R
17
AVSS1
18
DRVDD
19 HPLOUT 20 HPLCOM
21
DRVSS
22 HPRCOM 23 HPROUT
24
DRVDD
25
AVDD
26
AVSS2
27 LEFT_LOP 28 LEFT_LOM 29 RIGHT_LOP 30 RIGHT_LOM
31
RESET
32
DVDD
33
GND
U0601
TLV320AIC3104
C0619 100nF
C0618 100nF
R0614
1.5K
R0616
1.5K
C0613
2.2μF
C0605
100nF
C0611
10uF
C0606
1μF
C0607
100nF
C0608
1μF
C0610
1μF
C0614
100nF
C0615
1μF
R0613 0R
C0616
100nF
C0617
1μF
C0622 1μF
C0623 1μF
R0607 10K
R0605 0R
R0604 0R
R0601 0R
R0603 0R
C0612
100nF
C0603
NM
C0601
NM
C0602
NM
C0609
100nF
R0609
1K
R0612
1K
C0620
10μF
R0610
4.7K
R0611
4.7K
R0617
10K
G
SD
Q0601
Si2333DS-T1-E3
C0621
10nF
R0608
100K
Q0602
DTC043ZEBTL
R0615 NM_0R
C0624 22μF
C0604 22μF
R0606 NM_0R
R0602 0R
R0618 0R
R0619 0R
R0620 0R
R0621 0R
[7,9] MIC_P
[7,9] MIC_N
MICBIAS_3104
[3,7] I2C_SCL
[3,7] I2C_SDA
VDD_3.3V
VDD_1V8
[7,9]
SPK_P
[7,9]
SPK_N
DVDD
[3,7] CODEC_PCM_CLK
[3,7] CODEC_PCM_SYNC
[7,9]
SPK_R
[7,9]
SPK_L
[5,7,8] VDD_1V8 [8]
DVDD
[5,7,8] VDD_3.3V
[8]
DVDD
[5,7,8] VDD_1V8
[3,7] CODEC_PCM_OUT
[3,7] CODEC_PCM_IN

PROJECT TITLE
Lorry XU
Woody WU
CHECKED BY
DRAWN BY
OF
A
65432
1
SHEET
A
B
C
D
123456
D
C
B
Quectel Wireless Solutions
SIZE VER
149
1.0
DATE 2019/12/5
EG21-G
A2
Reference Design
Handset Application
Earphone Application
Close to earphone interface
Notes:
Audio Interfaces
CTIA OMTP
R0702/R0705
R0701/R0704 M
M
NM
NM
1. The analog output only drives earphone and headset. For larger power loads such as speakers, an audio power amplifier should be added in the design.
2. In handset application, both the MIC and SPK signal traces need to be routed as differential pairs.
3. In earphone application, the MIC signal traces need to be routed as differential pairs.
4. All MIC and SPK signal traces should be routed with total grounding and far away from noise such as clock and DC-DC signals, etc.
5. ALC5616 and TLV320AIC3104 cannot be used simultaneously in audio codec design.
4
1
3
2
J0701
D0701
ESD9X5.0ST5G
D0702
C0702
33pF
C0704
33pF
C0705
10pF
C0703
10pF
C0706
33pF
C0701
10pF
C0709
10pF
C0710
33pF
C0711
10pF
C0712
33pF
C0708
33pF
C0707
10pF
C0713
10pF
C0714
33pF
C0715
4.7μF
D0703
PESD5V0S1BL
D0704
R0703 0R
R-0805
1
2
3
4
5
J0702
C0716
10pF
C0717
33pF
D0705
ESD9X5.0ST5G
R0702 NM_0R
R0701 0R
R0704 0R
R0705 NM_0R
D0706
PESD5V0S1BL
C0718
10pF
C0719
33pF
D0707
PESD5V0S1BL
C0720
10pF
C0721
33pF
F0701 0R
F0702 0R
F0704 0R
F0703 0R
[7,8] SPK_P
[7,8,9] MIC_P
[7,8,9] MIC_N
[7,8,9] MIC_N
[7,8] SPK_N
[7,8] SPK_R
[7,8] SPK_L
[7,8,9] MIC_P
[7,8,9]
MIC_P

TITLE
PROJECT
Lorry XU
Woody WU
CHECKED BY
DRAWN BY
OF
A
65432
1
SHEET
A
B
C
D
123456
D
C
B
Quectel Wireless Solutions
SIZE VER
1410
1.0
DATE 2019/12/5
EG21-G
A2
Reference Design
RF and GNSS Designs
Main Antenna Circuit Diversity Antenna Circuit
GNSS Antenna Circuit
Notes:
1. It is recommended to use PI type main/Rx-diversity antenna circuit, thus ensuring convenient subsequent debugging.
2. The diversity reception function is ON by default. If diversity antenna is not used, there is a need to use AT command to turn off diversity reception. For more details of the AT command, please refer to
3. If an active antenna is selected for the GNSS antenna, a VDD power supply circuit is required; if a passive antenna is selected, the power supply circuit does not needs to be mounted.
Active Antenna
4. The impedance of the RF signal traces must be controlled as 50Ω when routing.
Passive Antenna
The power supply VDD of GNSS needs to be selected according to the requirements of the active antenna.
Quectel_EG21-G_Hardware_Design.
C0801
NM
R0801 0R
J0801
C0802
NM C0803
NM
R0802 0R
J0802
C0804
NM
L801
47nH
C805
0.1μF
R803
10R
C808 100pF
J804
C810
NM
C809
NM
R0805 0R
[3]
ANT_MAIN [3]
ANT_DIV
[3]
ANT_GNSS
VDD

TITLE
PROJECT
Lorry XU
Woody WU
CHECKED BY
DRAWN BY
OF
A
65432
1
SHEET
A
B
C
D
123456
D
C
B
Quectel Wireless Solutions
SIZE VER
1411
1.0
DATE 2019/12/5
EG21-G
A2
Reference Design
To minimize crosstalk, the reset trace must be at least 20mil
R916 should be placed close to AR8033.
The traces of the resistor must be away from other
and the trace width needs to be at least 25mil.
EMI filter is reserved.
If LED pins are not used, please keep C0920/C0923/C0924=470pF.
SGMII_MDIO_DAT should be connected to the USIM2_VDD
MODE 2
MODE 1
MODE 0
MODE 3
Ethernet PHY Design
PHY_AD2
PHY_AD1
PHY_AD0
traces (especially the clock and MDI interface traces),
The two capacitors should be selected according to the actual
load capacitance of crystal and the board-level test results.
Close to AR8033
Notes:
1. In the following description, the SGMII data signal refers to the SGMII TX and RX differencial pair, and the SGMII control signal refers to the SGMII_MDIO_CLK, SGMII_MDIO_DATA, EPHY_RST_N and EPHY_INT_N.
3. Keep the maximum trace length of SGMII data signal less than 10 inches and keep the length difference between TX and RX signals less than 20mil.
4. The differential impedance of SGMII data signal is 100Ω±10%, and the reference ground of the area should be complete.
EXT_INT_SEL
5. Make sure the trace spacing between SGMII RX and TX signals is at least 3 times of the trace width, and is the same to the adjacent signal traces.
6. Module and AR8033 are recommended to be designed on the same PCB. The peripheral circuit layout of Ethernet PHY chip AR8033 should be designed on a
7. RJ45, network transformer, AR8033, and the SGMII interface should be placed as close as possible.
beside the module with a 1.5kΩ pull-up resistor.
away from other signal traces.
L0901, C0913 and C0914 need to be placed close to Pin 3.
2. SGMII data and control signals should be strictly surrounded with ground and kept away from RF, analog, clock and DC-DC signals etc.
four-layer PCB, and the second layer should be total grounded as the AR8033 reference GND.
1MDC
2RSTN
3LX
4VDD33
5INT
6XTLO
7XTLI
8AVDDL
9RBIAS
10 VDDH_REG
11 TRXP0
12 TRXN0
13 AVDDL 14 TRXP1 15 TRXN1 16 AVDD33 17 TRXP2 18 TRXN2 19 AVDDL 20 TRXP3 21 TRXN3 22 NC 23 LED_ACT 24 LED_1000
25
CLK_25M
26
LED_10_100
27
RXD3
28
RXD2
29
VDDIO_REG
30
RXD1
31
RXD0
32
RX_DV
33
RX_CLK
34
TX_EN
35
GTX_CLK
36
TXD0
37
TXD1 38 TXD2 39 TXD3 40
WOL_INT 41
SD 42
SON 43
SOP 44
AVDDL 45
SIN 46
SIP 47
DVDDL 48
MDIO 49
GND
U901
AR8033-AL1B-R
R903
NM_100K
C910 NM_1μF
R916
2.37K 1%
R908 10K
R906 NM_10K
C921
0.1μF
C925
0.1μF
C926
0.1μF
C911
10μF
C927
1μF
C928
0.1μF
FB902
BLM15AX700SN1D
C922
1μF
C916
0.1μF
C915
100pF
1
XTAL
2GND 3
XTAL
4GND
Y901
25MHz C917
10pF
C918
10pF
C924 NM/470pF
C923 NM/470pF
C919
NM
C920
NM/470pF
D901
GREEN
R915 510R
R901 0R
C908 0.1μF
C909 0.1μF
R904 0R
R907 0R
+
C904
100μF
C902
33pF
C901
10pF
C903
100nF
C912
0.1μF
FB901
BLM15AX700SN1D
R905 NM_10K
L901
4.7μH
C913
10μF
C914
0.1μF
C905
0.1μF
R914 10K
R909 10K
R913 10K
R910 10K
R911 10K
R912 10K
R917 10K
R918 10K
R902
1.5K
C906
2.2μF
C907
0.1μF
[3] EPHY_RST_N
[3] EPHY_INT_N
AVDD_1V1
[11]
VDD33_SGMII
[3]
SGMII_TX_M
[3]
SGMII_RX_P
[3]
SGMII_RX_M
[3]
SGMII_TX_P
[11] VDD33_SGMII
[11] VDDH_2V5
[12] TRXP0
[12] TRXN0
[12]
TRXP1
[12]
TRXN1
[12]
TRXP2
[12]
TRXN2
[12]
TRXP3
[12]
TRXN3
[12]
LED_ACT
[12]
LED_1000
[3] SGMII_MDIO_DATA
[3] SGMII_MDIO_CLK
[11] VDD33_SGMII
CLK_25M
[11] VDD33_SGMII [5,13]
VDD3V3
[3,4,5,6,13,14] VDD_EXT
[11]
VDDH_2V5
[11]
AVDD_1V1
[11] DVDD_1V1
[11]
DVDD_1V1
[11] AVDD_1V1
[11]
VDDH_2V5
[3]
USIM2_VDD
AVDD_1V1
[11]
AVDD_1V1
[11] AVDD_1V1