Realtek Ameba-D RTL872 D Series User manual

UM0400
Ameba-D User Manual
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: [phone]. Fax: [phone]
www.realtek.com

Ameba-D User Manual
User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
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Ameba-D User Manual
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TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document are trademarks/registered trademarks
of their respective owners.
USING THIS DOCUMENT
Though every effort has been made to ensure that this document is current and accurate, more information may have become available
subsequent to the production of this guide.

Ameba-D User Manual
User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
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Contents
Contents......................................................................................................................................................................................4
List of Tables..............................................................................................................................................................................12
List of Figures ............................................................................................................................................................................17
Conventions ..............................................................................................................................................................................22
1Product Overview...............................................................................................................................................................23
1.1 General Description.............................................................................................................................................................23
1.2 System Architecture ............................................................................................................................................................23
2Memory Organization.........................................................................................................................................................25
2.1 Introduction.........................................................................................................................................................................25
2.2 KM4 Memory Map and Register Boundary Addresses........................................................................................................25
2.3 KM0 Memory Map and Register Boundary Addresses........................................................................................................26
2.4 KM4 Embedded SRAM.........................................................................................................................................................27
2.5 KM0 Embedded SRAM.........................................................................................................................................................27
2.6 KM4 Extension SRAM ..........................................................................................................................................................27
2.7 Retention SRAM ..................................................................................................................................................................27
2.8 SPI Flash Memory ................................................................................................................................................................27
2.9 PSRAM .................................................................................................................................................................................27
3Memory Protection Unit (MPU)..........................................................................................................................................28
3.1 Register Map .......................................................................................................................................................................28
3.2 Register Field Description....................................................................................................................................................28
3.2.1 MPU_TYPE ....................................................................................................................................................................28
3.2.2 MPU_CTRL ....................................................................................................................................................................29
3.2.3 MPU_RNR.....................................................................................................................................................................30
3.2.4 MPU_RBAR ...................................................................................................................................................................30
3.2.5 MPU_RLAR....................................................................................................................................................................31
3.2.6 MPU_RBAR_A<n>.........................................................................................................................................................32
3.2.7 MPU_RLAR_A<n> .........................................................................................................................................................32
3.2.8 MPU_MAIR0 .................................................................................................................................................................33
3.2.9 MPU_MAIR1 .................................................................................................................................................................34
3.3 Memory Attribute Indirection Register Attributes (MAIR_ATTR) .......................................................................................34
3.3.1 Outer.............................................................................................................................................................................35
3.3.2 Inner .............................................................................................................................................................................35
4Nested Vectored Interrupt Controller (NVIC)......................................................................................................................36
4.1 Features...............................................................................................................................................................................36
4.2 NVIC Diagram.......................................................................................................................................................................36
4.3 NVIC Table ...........................................................................................................................................................................36
4.4 NVIC Register Description....................................................................................................................................................38
4.4.1 ISER0 and ISER1 ............................................................................................................................................................39
4.4.2 ICER0 and ICER1 ...........................................................................................................................................................40
4.4.3 ISPR0 and ISPR1............................................................................................................................................................40
4.4.4 ICPR0 and ICPR1 ...........................................................................................................................................................40

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4.4.5 IABR0 and IABR1...........................................................................................................................................................40
4.4.6 IPR0 ~ IPR14..................................................................................................................................................................40
4.4.7 STIR...............................................................................................................................................................................40
5CPU System Tick (SysTick) Timer.........................................................................................................................................42
5.1 Features...............................................................................................................................................................................42
5.2 Functional Description.........................................................................................................................................................42
5.3 Register Description ............................................................................................................................................................42
5.3.1 SYST_CSR ......................................................................................................................................................................42
5.3.2 SYST_RVR......................................................................................................................................................................43
5.3.3 SYST_CVR......................................................................................................................................................................43
5.3.4 SYST_CALIB ...................................................................................................................................................................44
6Pad Control and Pinmux .....................................................................................................................................................45
6.1 Features...............................................................................................................................................................................45
6.2 Functional Description.........................................................................................................................................................45
6.2.1 Pad Types......................................................................................................................................................................45
6.2.2 Pad Pull Resistor Control ..............................................................................................................................................46
6.2.3 Pad Schmitt Trigger ......................................................................................................................................................47
6.2.4 Pad Driving Strength.....................................................................................................................................................47
6.2.5 Pad Shut Down .............................................................................................................................................................47
6.2.6 I2C Open-drain Mode ....................................................................................................................................................47
6.2.7 Audio Pad .....................................................................................................................................................................47
6.3 Pin Multiplexing Function....................................................................................................................................................48
6.4 Register −PADCTRL .............................................................................................................................................................49
7Inter Processor Communication (IPC) .................................................................................................................................51
7.1 Features...............................................................................................................................................................................51
7.2 Functional Description.........................................................................................................................................................51
7.2.1 Architecture Block Diagram..........................................................................................................................................51
7.2.2 Core-to-Core Interrupt ..................................................................................................................................................51
7.2.3 Hardware Semaphore...................................................................................................................................................52
7.3 IPC Registers ........................................................................................................................................................................53
7.3.1 IPCx_IER........................................................................................................................................................................53
7.3.2 IPCx_IDR .......................................................................................................................................................................54
7.3.3 IPCx_IRR........................................................................................................................................................................54
7.3.4 IPCx_ICR........................................................................................................................................................................54
7.3.5 IPC0_CPUID...................................................................................................................................................................55
7.3.6 IPCx_ISR ........................................................................................................................................................................55
7.3.7 IPC0_SEM......................................................................................................................................................................55
7.3.8 IPCx_IER_R....................................................................................................................................................................56
7.3.9 IPC_USR ........................................................................................................................................................................57
8General Purpose Input/Output (GPIO)................................................................................................................................58
8.1 Introduction.........................................................................................................................................................................58
8.1.1 General Product Description.........................................................................................................................................58
8.1.2 Features........................................................................................................................................................................58
8.2 Functional Description.........................................................................................................................................................58
8.2.1 Data and Control Flow..................................................................................................................................................59
8.2.2 Interrupts......................................................................................................................................................................61
8.3 Registers ..............................................................................................................................................................................69
8.3.1 Bus Interface.................................................................................................................................................................69
8.3.2 Register Memory Map..................................................................................................................................................70

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8.3.3 Register and Field Descriptions.....................................................................................................................................71
8.4 Programming the GPIO........................................................................................................................................................85
8.4.1 Software Registers........................................................................................................................................................85
8.4.2 Programming Considerations .......................................................................................................................................85
9Direct Memory Access Controller (DMAC) ..........................................................................................................................86
9.1 Product Overview ................................................................................................................................................................86
9.1.1 General Product Description.........................................................................................................................................86
9.1.2 Basic Definitions ...........................................................................................................................................................88
9.1.3 Features........................................................................................................................................................................90
9.2 Functional Description.........................................................................................................................................................92
9.2.1 Setup/Operation of DMA Transfers ..............................................................................................................................92
9.2.2 Block Flow Controller and Transfer Type ......................................................................................................................92
9.2.3 Handshaking Interface .................................................................................................................................................93
9.2.4 Basic Interface Definitions ............................................................................................................................................93
9.2.5 Memory Peripherals .....................................................................................................................................................94
9.2.6 Handshaking Interface –Peripheral is Not Flow Controller..........................................................................................94
9.2.7 Handshaking Interface –Peripheral Is Flow Controller ..............................................................................................100
9.2.8 Setting up Transfers....................................................................................................................................................102
9.2.9 Flow Control Configurations .......................................................................................................................................120
9.2.10 Peripheral Burst Transaction Requests.......................................................................................................................121
9.2.11 Generating Requests for the AHB Master Bus Interface ............................................................................................125
9.2.12 Arbitration for AHB Master Interface .........................................................................................................................127
9.2.13 Scatter/Gather............................................................................................................................................................128
9.2.14 Endianness..................................................................................................................................................................130
9.2.15 AHB Transfer Error Handling ......................................................................................................................................130
9.3 Registers ............................................................................................................................................................................131
9.3.1 Register Memory Map................................................................................................................................................131
9.3.2 Registers and Field Descriptions .................................................................................................................................136
9.4 Programming the DMAC....................................................................................................................................................170
9.4.1 Register Access ...........................................................................................................................................................171
9.4.2 Illegal Register Access.................................................................................................................................................171
9.4.3 DMA Transfer Types ...................................................................................................................................................171
9.4.4 Programing Example ..................................................................................................................................................176
9.4.5 Programming a Channel.............................................................................................................................................178
9.4.6 Disabling a Channel Prior to Transfer Completion......................................................................................................192
9.4.7 Defined-Length Burst Support on DMAC ....................................................................................................................193
10 General Timers..............................................................................................................................................................194
10.1 Basic Timer.....................................................................................................................................................................194
10.1.1 Introduction ................................................................................................................................................................194
10.1.2 Features......................................................................................................................................................................194
10.1.3 Block Diagram ............................................................................................................................................................194
10.1.4 Functional Description................................................................................................................................................194
10.2 Pulse Mode Timer ..........................................................................................................................................................195
10.2.1 Introduction ................................................................................................................................................................195
10.2.2 Features......................................................................................................................................................................195
10.2.3 Block Diagram ............................................................................................................................................................196
10.2.4 Functional Description................................................................................................................................................196
10.3 PWM Mode Timer..........................................................................................................................................................198
10.3.1 Introduction ................................................................................................................................................................198
10.3.2 Features......................................................................................................................................................................198
10.3.3 Block Diagram ............................................................................................................................................................199

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10.3.4 Functional Description................................................................................................................................................199
10.4 Registers.........................................................................................................................................................................206
10.4.1 TIM0/TIM1/TIM2/TIM3 Registers ..............................................................................................................................206
10.4.2 TIM4 Registers............................................................................................................................................................209
10.4.3 TIM5 Registers............................................................................................................................................................213
10.5 Design Implementation..................................................................................................................................................227
10.5.1 Introduction ................................................................................................................................................................227
10.5.2 Synchronous Data from Fast Clock to Slow Clock.......................................................................................................228
10.6 Operation Flow ..............................................................................................................................................................228
10.6.1 Upcounting Mode.......................................................................................................................................................228
10.6.2 Pulse Mode .................................................................................................................................................................229
10.6.3 PWM Mode.................................................................................................................................................................229
10.6.4 Input Capture Mode ...................................................................................................................................................230
11 Real-time Clock (RTC) ....................................................................................................................................................231
11.1 Product Overview ..........................................................................................................................................................231
11.1.1 Introduction ................................................................................................................................................................231
11.1.2 Features......................................................................................................................................................................231
11.1.3 Block Diagram ............................................................................................................................................................231
11.1.4 RTC Clock Select Diagram ...........................................................................................................................................232
11.2 Functional Description ...................................................................................................................................................232
11.2.1 Clock and Prescaler.....................................................................................................................................................232
11.2.2 32K Auto-trigger Calibration Circuit ...........................................................................................................................233
11.2.3 Programmable Alarm .................................................................................................................................................234
11.2.4 Write Protection .........................................................................................................................................................234
11.2.5 Digital Calibration.......................................................................................................................................................234
11.2.6 Day Threshold Program ..............................................................................................................................................235
11.3 Registers.........................................................................................................................................................................235
11.3.1 RTC Time Register (RTC_TR) .......................................................................................................................................235
11.3.2 RTC Control Register (RTC_CR) ...................................................................................................................................235
11.3.3 RTC Initialization and Status Register (RTC_ISR) ........................................................................................................237
11.3.4 RTC Prescaler Register (RTC_PRER) ............................................................................................................................238
11.3.5 RTC Calibration Register (RTC_CALIBR) ......................................................................................................................238
11.3.6 RTC Alarm 1 Register Low (RTC_ALMR1L) ..................................................................................................................239
11.3.7 RTC Alarm 1 Register High (RTC_ALMR1H) ................................................................................................................239
11.3.8 RTC Write Protection Register (RTC_WPR) .................................................................................................................240
11.3.9 RTC 32K Auto-calibration Register (RTC_CLKACALR)..................................................................................................240
11.4 Operation Flow ..............................................................................................................................................................241
11.4.1 Initialize the Calendar.................................................................................................................................................241
11.4.2 Configure Alarm..........................................................................................................................................................241
11.4.3 Configure Calibration..................................................................................................................................................241
11.4.4 Daylight Saving Time ..................................................................................................................................................242
12 Watchdog Timer (WDT).................................................................................................................................................243
12.1 Introduction ...................................................................................................................................................................243
12.2 Features .........................................................................................................................................................................243
12.3 Registers.........................................................................................................................................................................243
13 Inter-integrated Circuit (I2C) Interface ...........................................................................................................................245
13.1 Introduction ...................................................................................................................................................................245
13.2 Functional Description ...................................................................................................................................................245
13.2.1 Overview.....................................................................................................................................................................245
13.2.2 I2C Terminology ..........................................................................................................................................................246

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13.2.3 I2C Behavior ................................................................................................................................................................247
13.2.4 I2C Protocols................................................................................................................................................................248
13.2.5 Tx FIFO Management and START, STOP and RESTART Generation ............................................................................252
13.2.6 Multiple Master Arbitration .......................................................................................................................................254
13.2.7 Clock Synchronization.................................................................................................................................................255
13.2.8 Operation Modes........................................................................................................................................................255
13.2.9 IC_CLK Frequency Configuration.................................................................................................................................257
13.2.10 Programmable SDA Hold Time................................................................................................................................259
13.2.11 DMA Controller Interface........................................................................................................................................259
13.2.12 Low Power Mode ....................................................................................................................................................260
13.3 Registers.........................................................................................................................................................................261
13.3.1 Register Memory Map................................................................................................................................................261
13.3.2 Registers and Field Descriptions .................................................................................................................................262
14 Universal Asynchronous Receiver/Transmitter (UART) .................................................................................................284
14.1 Introduction ...................................................................................................................................................................284
14.1.1 Features......................................................................................................................................................................284
14.1.2 Block Diagram ............................................................................................................................................................284
14.2 Register ..........................................................................................................................................................................285
14.2.1 IER...............................................................................................................................................................................286
14.2.2 IIR................................................................................................................................................................................286
14.2.3 LCR..............................................................................................................................................................................287
14.2.4 MCR ............................................................................................................................................................................288
14.2.5 LSR ..............................................................................................................................................................................289
14.2.6 MSR ............................................................................................................................................................................289
14.2.7 SCR..............................................................................................................................................................................290
14.2.8 STSR ............................................................................................................................................................................291
14.2.9 RBR .............................................................................................................................................................................291
14.2.10 THR..........................................................................................................................................................................291
14.2.11 MISCR......................................................................................................................................................................292
14.2.12 IRDA_SIR_TX_PW_CTRL ..........................................................................................................................................293
14.2.13 IRDA_SIR_RX_PW_CTRL..........................................................................................................................................293
14.2.14 BAUD_MON ............................................................................................................................................................293
14.2.15 DBG_UART ..............................................................................................................................................................294
14.2.16 REG_RX_PATH_CTRL ...............................................................................................................................................294
14.2.17 REG_MON_BAUD_CTRL ..........................................................................................................................................295
14.2.18 REG_MON_BAUD_STS ............................................................................................................................................295
14.2.19 REG_MON_CYC_NUM.............................................................................................................................................295
14.2.20 REG_RX_BYTE_CNT .................................................................................................................................................296
14.2.21 FCR ..........................................................................................................................................................................296
14.3 Design Implementation..................................................................................................................................................297
14.3.1 Baud Rate Calculation ................................................................................................................................................297
14.3.2 Clock Structure of Rx Path ..........................................................................................................................................298
14.3.3 Irda_sir_encoder/decoder ..........................................................................................................................................299
14.3.4 Auto-flow Control .......................................................................................................................................................300
14.3.5 Interrupt Control.........................................................................................................................................................300
14.3.6 DMA Flow Control ......................................................................................................................................................301
15 Infrared Radiation (IR)...................................................................................................................................................302
15.1 Overall Description ........................................................................................................................................................302
15.1.1 Introduction ................................................................................................................................................................302
15.1.2 Features......................................................................................................................................................................303
15.2 Architecture ...................................................................................................................................................................303

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15.2.1 Scaler ..........................................................................................................................................................................304
15.2.2 Glitch Filter .................................................................................................................................................................304
15.2.3 Interrupt .....................................................................................................................................................................304
15.3 Registers.........................................................................................................................................................................304
15.3.1 IR Clock Control Register.............................................................................................................................................305
15.3.2 IR Tx Registers ............................................................................................................................................................305
15.3.3 IR Rx Registers ............................................................................................................................................................308
15.3.4 IR Version Register......................................................................................................................................................312
15.4 IR Application Note ........................................................................................................................................................312
15.4.1 RCU Application..........................................................................................................................................................312
15.4.2 Receiver Application ...................................................................................................................................................313
16 Key-Scan........................................................................................................................................................................314
16.1 Overall Description ........................................................................................................................................................314
16.1.1 Application Scenario...................................................................................................................................................314
16.1.2 Features......................................................................................................................................................................314
16.2 Functional Description ...................................................................................................................................................314
16.2.1 Block Diagram ............................................................................................................................................................314
16.2.2 Work Principle ............................................................................................................................................................315
16.2.3 FIFO Mechanism .........................................................................................................................................................318
16.2.4 Clock Configuration ....................................................................................................................................................318
16.2.5 Shadow Key Problem ..................................................................................................................................................319
16.3 Registers.........................................................................................................................................................................321
16.3.1 KS_CLK_DIV ................................................................................................................................................................321
16.3.2 KS_TIM_CFG0 .............................................................................................................................................................322
16.3.3 KS_TIM_CFG1 .............................................................................................................................................................322
16.3.4 KS_CTRL ......................................................................................................................................................................322
16.3.5 KS_FIFO_CFG ..............................................................................................................................................................323
16.3.6 KS_COL_CFG ...............................................................................................................................................................323
16.3.7 KS_ROW_CFG .............................................................................................................................................................324
16.3.8 KS_DATA_NUM ..........................................................................................................................................................324
16.3.9 KS_DATA .....................................................................................................................................................................325
16.3.10 KS_IMR....................................................................................................................................................................325
16.3.11 KS_ICR .....................................................................................................................................................................326
16.3.12 KS_ISR .....................................................................................................................................................................326
16.3.13 KS_ISR_RAW ...........................................................................................................................................................327
16.3.14 KS_DUMMY.............................................................................................................................................................327
17 Audio Codec (AC) ..........................................................................................................................................................329
17.1 Introduction ...................................................................................................................................................................329
17.2 Diagram..........................................................................................................................................................................329
17.3 Key Features...................................................................................................................................................................330
17.3.1 Analog Part.................................................................................................................................................................330
17.3.2 Digital Part..................................................................................................................................................................330
17.4 Specifications .................................................................................................................................................................331
17.4.1 DAC Path.....................................................................................................................................................................331
17.4.2 ADC Path.....................................................................................................................................................................332
17.5 Application and Implementation ...................................................................................................................................333
17.5.1 Audio Output ..............................................................................................................................................................333
17.5.2 Audio Input .................................................................................................................................................................334
17.6 Registers.........................................................................................................................................................................337
17.6.1 Analog Part.................................................................................................................................................................337
17.6.2 Digital Part..................................................................................................................................................................341

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17.6.3 DAC_EQ ......................................................................................................................................................................360
17.6.4 ADC_EQ ......................................................................................................................................................................370
18 Audio Codec Controller (ACC)........................................................................................................................................381
18.1 Introduction ...................................................................................................................................................................381
18.2 Features .........................................................................................................................................................................381
18.3 Architecture ...................................................................................................................................................................381
18.3.1 Block Diagram ............................................................................................................................................................381
18.3.2 Data Part ....................................................................................................................................................................382
18.3.3 Control Part ................................................................................................................................................................387
18.3.4 ACC Clock....................................................................................................................................................................388
18.4 Registers.........................................................................................................................................................................388
18.4.1 SPORT Control Registers .............................................................................................................................................388
18.4.2 SI Control Registers.....................................................................................................................................................393
19 Serial Peripheral Interface (SPI).....................................................................................................................................395
19.1 Product Overview ..........................................................................................................................................................395
19.1.1 Block Diagram ............................................................................................................................................................395
19.1.2 Features......................................................................................................................................................................395
19.2 Functional Description ...................................................................................................................................................396
19.2.1 Overview.....................................................................................................................................................................396
19.2.2 Transfer Modes...........................................................................................................................................................400
19.2.3 Operation Modes........................................................................................................................................................400
19.2.4 DMA Controller Interface............................................................................................................................................404
19.3 Registers.........................................................................................................................................................................404
19.3.1 Register Memory Map................................................................................................................................................404
19.3.2 Registers and Field Descriptions .................................................................................................................................406
20 Liquid Crystal Display Controller (LCDC) ........................................................................................................................421
20.1 Overall Description ........................................................................................................................................................421
20.1.1 Introduction ................................................................................................................................................................421
20.1.2 Features......................................................................................................................................................................421
20.1.3 LCD Application Scenario............................................................................................................................................421
20.2 Architecture ...................................................................................................................................................................422
20.2.1 Block Diagram ............................................................................................................................................................422
20.2.2 MCU Interface ............................................................................................................................................................424
20.2.3 RGB Interface..............................................................................................................................................................427
20.2.4 LED Control .................................................................................................................................................................430
20.2.5 Pinmux........................................................................................................................................................................436
20.2.6 Supported Resolution .................................................................................................................................................436
20.3 Registers.........................................................................................................................................................................438
20.3.1 Global Control Registers .............................................................................................................................................439
20.3.2 Interrupt and Status Registers....................................................................................................................................441
20.3.3 RGB Control Registers.................................................................................................................................................444
20.3.4 MCU Control Registers ...............................................................................................................................................446
20.3.5 LED Control Registers .................................................................................................................................................449
20.3.6 Image Control Registers .............................................................................................................................................451
20.4 Programming the LCDC..................................................................................................................................................451
20.4.1 RGB DMA Auto-mode .................................................................................................................................................451
20.4.2 MCU DMA Trigger-mode............................................................................................................................................452
20.4.3 MCU I/O Mode ...........................................................................................................................................................452
21 Quadrature Decoder (Q-Decoder) .................................................................................................................................453

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21.1 Overall Description ........................................................................................................................................................453
21.1.1 Introduction ................................................................................................................................................................453
21.1.2 Features......................................................................................................................................................................453
21.1.3 Application Scenario...................................................................................................................................................453
21.2 Architecture ...................................................................................................................................................................454
21.2.1 Q-Decoder Block Diagram ..........................................................................................................................................454
21.2.2 Position Measurement ...............................................................................................................................................455
21.2.3 Velocity Measurement................................................................................................................................................459
21.3 Registers.........................................................................................................................................................................460
21.3.1 Global Control Registers .............................................................................................................................................460
21.3.2 Position Measurement Registers................................................................................................................................463
21.3.3 Velocity Measurement Registers ................................................................................................................................465
21.3.4 Interrupt Registers......................................................................................................................................................468
22 Inter-IC Sound (I2S)........................................................................................................................................................472
22.1 Introduction ...................................................................................................................................................................472
22.2 Features .........................................................................................................................................................................472
22.3 Interface.........................................................................................................................................................................472
22.4 Functional Description ...................................................................................................................................................473
22.4.1 Signal Lines .................................................................................................................................................................473
22.4.2 Operation Mode .........................................................................................................................................................474
22.4.3 Serial Data Standard...................................................................................................................................................475
22.4.4 Clock Type...................................................................................................................................................................476
22.4.5 Memory Block.............................................................................................................................................................478
22.4.6 FIFO Allocation ...........................................................................................................................................................478
22.5 Registers.........................................................................................................................................................................482
22.5.1 Control Register (IS_CTL) ............................................................................................................................................483
22.5.2 Tx Page Pointer Register (IS_TX_PAGE_PTR)..............................................................................................................484
22.5.3 Rx Page Pointer Register (IS_RX_PAGE_PTR) .............................................................................................................484
22.5.4 Page Size and Sample Rate Setting Register (IS_SETTING).........................................................................................485
22.5.5 Tx Interrupt Enable Register (IS_TX_MASK_INT) ........................................................................................................485
22.5.6 Tx Interrupt Status Register (IS_TX_STATUS_INT) ......................................................................................................486
22.5.7 Rx Interrupt Enable Register (IS_RX_MASK_INT)........................................................................................................487
22.5.8 Rx Interrupt Status Register (IS_RX_STATUS_INT)......................................................................................................488
22.5.9 Tx Page Own Bit Register (IS_TX_PAGE_OWNx) ........................................................................................................489
22.5.10 Rx Page Own Bit Register (IS_RX_PAGE_OWNx) ....................................................................................................489
22.5.11 Version ID (IS_VERSION_ID) ....................................................................................................................................489
Abbreviations ..........................................................................................................................................................................490
Revision History.......................................................................................................................................................................494

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List of Tables
Fig 1-1 System architecture ...............................................................................................................................................................23
Fig 4-1 NVIC diagram..........................................................................................................................................................................36
Fig 6-1 Pad diagram ...........................................................................................................................................................................45
Fig 6-2 Selecting an alternate function on Ameba-D .........................................................................................................................49
Fig 7-1 IPC system architecture..........................................................................................................................................................51
Fig 7-2 IPC interrupt request..............................................................................................................................................................52
Fig 7-3 IPC hardware semaphore mechanism ...................................................................................................................................52
Fig 8-1 Block diagram.........................................................................................................................................................................58
Fig 8-2 Control RTL block diagram .....................................................................................................................................................59
Fig 8-3 Read back of external gpio_ext_portXdata timing................................................................................................................61
Fig 8-4 Interrupt RTL block diagram...................................................................................................................................................62
Fig 8-5 Debounce RTL diagram ..........................................................................................................................................................62
Fig 8-6 Debounce timing with asynchronous reset Flip-Flops ...........................................................................................................63
Fig 8-7 Synchronization and edge detect interrupt generation when GPIO_INT_BOTH_EDGE=0 ....................................................64
Fig 8-8 Interrupt edge detection and interrupt clear timing when GPIO_SYNC_PA_INTERRPUTS = 1 (metastability included).......64
Fig 8-9 Interrupt edge detection and interrupt clear timing when GPIO_SYNC_PA_INTERRPUTS = 0 (metastability removed) ......65
Fig 8-10 Write to interrupt clear register, coincident with detection of new interrupt ....................................................................66
Fig 8-11 Synchronization and edge detect interrupt generation when GPIO_INT_BOTH_EDGE=0 ..................................................66
Fig 8-12 Interrupt edge detection and interrupt clear timing when GPIO_SYNC_PA_INTERRPUTS = 1 and
GPIO_INT_BOTH_EDGE=1 (metastability included) .................................................................................................................67
Fig 8-13 Interrupt edge detection and interrupt clear timing when GPIO_SYNC_PA_INTERRPUTS = 0 and
GPIO_INT_BOTH_EDGE=1 (metastability Removed)................................................................................................................68
Fig 8-14 Level-sensitive interrupt RTL diagram..................................................................................................................................68
Fig 8-15 Active-low level-sensitive interrupt generation timing........................................................................................................69
Fig 8-16 Relationship between APB and APB slave data widths........................................................................................................69
Fig 9-1 Block diagram of DMAC .........................................................................................................................................................86
Fig 9-2 Peripheral-to-Peripheral DMA transfer on the same AHB layer ............................................................................................87
Fig 9-3 Peripheral-to-Memory DMA transfer on separate AHB layers ..............................................................................................88
Fig 9-4 DMA Transfer Hierarchy for Non-Memory Peripherals .........................................................................................................89
Fig 9-5 DMA transfer hierarchy for memory......................................................................................................................................89
Fig 9-6 Hardware handshaking interface ...........................................................................................................................................95
Fig 9-7 Burst transaction –pclk = hclk ...............................................................................................................................................96
Fig 9-8 Back-to-Back burst transactions –hclk = 2*per_clk...............................................................................................................97
Fig 9-9 Single transaction...................................................................................................................................................................98
Fig 9-10 Burst followed by Back-to-Back single transactions.............................................................................................................98
Fig 9-11 Early-Terminated burst transaction .....................................................................................................................................98
Fig 9-12 Burst transaction ignored during active single transaction .................................................................................................99
Fig 9-13 Generation of dma_req and dma_single by source .............................................................................................................99
Fig 9-14 Hardware handshaking interface .......................................................................................................................................101
Fig 9-15 Burst transaction followed by single transaction that terminates block ...........................................................................101
Fig 9-16 Single transaction followed by burst transaction that terminates block ...........................................................................102
Fig 9-17 Breakdown of Block Transfer .............................................................................................................................................104
Fig 9-18 Channel FIFO contents at times indicated in Fig 9-17........................................................................................................104
Fig 9-19 Breakdown of block transfer for DMAH_CH_FIFO_DEPTH = 8 ..........................................................................................105
Fig 9-20 Breakdown of block transfer where max_abrst = 2, Case 1...............................................................................................106
Fig 9-21 Channel FIFO contents at times indicated in Fig 9-20........................................................................................................106
Fig 9-22 Breakdown of block transfer where max_abrst = 2, Case 2...............................................................................................107

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Fig 9-23 Channel FIFO contents at times indicated in Fig 9-22........................................................................................................107
Fig 9-24 Breakdown of block transfer..............................................................................................................................................108
Fig 9-25 Source FIFO contents at time indicated in Fig 9-24............................................................................................................109
Fig 9-26 Source FIFO contents where watermark level is dynamically adjusted.............................................................................109
Fig 9-27 Block transfer to destination..............................................................................................................................................110
Fig 9-28 Block transfer up to time ‘t4’ .............................................................................................................................................112
Fig 9-29 Source, DMAC channel and destination FIFOs at time ‘t4’ in Fig 9-26...............................................................................112
Fig 9-30 FIFO status after early-terminated burst ...........................................................................................................................113
Fig 9-31 Data loss when pre-fetching is enabled .............................................................................................................................114
Fig 9-32 Timing exception on dma_finish to source peripheral ......................................................................................................115
Fig 9-33 Case of no data loss when pre-fetching is enabled............................................................................................................116
Fig 9-34 Source enters single transaction region when destination asserts dma_last[1] ...............................................................117
Fig 9-35 Case where source does not enter single transaction region when destination asserts dma_last[1]...............................117
Fig 9-36 Data loss when data pre-fetching is disabled.....................................................................................................................119
Fig 9-37 Transaction request through peripheral interrupt.............................................................................................................120
Fig 9-38 Flow control configurations ...............................................................................................................................................121
Fig 9-39 Case 1 watermark levels where SSI.DMATDLR = 2.............................................................................................................122
Fig 9-40 Case 2 watermark levels where SSI.DMATDLR = 6.............................................................................................................123
Fig 9-41 SSI receive FIFO ..................................................................................................................................................................124
Fig 9-42 Arbitration flow for master bus interface ..........................................................................................................................127
Fig 9-43 Example of destination scatter transfer.............................................................................................................................129
Fig 9-44 Source gather when SGR.SGI = 0x1 ....................................................................................................................................129
Fig 9-45 Multi-block transfer using linked lists when DMAH_CHx_STAT_SRC set to true...............................................................172
Fig 9-46 Multi-block transfer using linked lists when DMAH_CHx_STAT_SRC set to false ..............................................................173
Fig 9-47 Mapping of block descriptor (LLI) in memory to channel registers when DMAH_CHx_STAT_SRC set to true ..................173
Fig 9-48 Mapping of block descriptor (LLI) in memory to channel registers when DMAH_CHx_STAT_SRC set to false .................173
Fig 9-49 Flowchart for DMA programming example .......................................................................................................................177
Fig 9-50 Multi-block with linked address for source and destination..............................................................................................181
Fig 9-51 Multi-block with linked address for source and destination where SARx and DARx between successive blocks are
contiguous..............................................................................................................................................................................181
Fig 9-52 DMA transfer flow for source and destination linked list address.....................................................................................182
Fig 9-53 Multi-block DMA transfer with source and destination address auto-reloaded ...............................................................183
Fig 9-54 DMA transfer flow for source and destination address auto-reloaded .............................................................................184
Fig 9-55 Multi-block DMA transfer with source address auto-reloaded and linked list destination address .................................186
Fig 9-56 DMA transfer flow for source address auto-reloaded and linked list destination address ...............................................187
Fig 9-57 Multi-block DMA transfer with source address auto-reloaded and contiguous destination address ...............................189
Fig 9-58 DMA transfer flow for source address auto-reloaded and contiguous destination address.............................................189
Fig 9-59 Multi-block DMA transfer with linked list source address and contiguous destination address.......................................191
Fig 9-60 DMA transfer flow for source address auto-reloaded and contiguous destination address.............................................192
Fig 10-1 Block diagram.....................................................................................................................................................................194
Fig 10-2 TIM4 block diagram............................................................................................................................................................196
Fig 10-3 Statistic pulse width mode diagram (positive edge of TRGI is active for capture).............................................................197
Fig 10-4 Statistic pulse number mode diagram (positive edge of TRGI is active for capture, ARR=E6)...........................................198
Fig 10-5 PWM timer block diagram .................................................................................................................................................199
Fig 10-6 Counter timing diagram with prescaler division change from 1 to 2.................................................................................200
Fig 10-7 Counter timing diagram with prescaler division change from 1 to 4.................................................................................201
Fig 10-8 Counter timing diagram (internal clock divided by 1)........................................................................................................202
Fig 10-9 Counter timing diagram (internal clock divided by 2)........................................................................................................202
Fig 10-10 Counter timing diagram (internal clock divided by 4)......................................................................................................202
Fig 10-11 Counter timing diagram (internal clock divided by N) .....................................................................................................203
Fig 10-12 Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded).........................................................203
Fig 10-13 Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) ...............................................................204
Fig 10-14 Edge-aligned PWM waveforms (ARR=8, CCxP=0) ............................................................................................................205

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Fig 10-15 One-pulse mode timing....................................................................................................................................................205
Fig 10-16 Block diagram...................................................................................................................................................................227
Fig 10-17 Synchronous data diagram...............................................................................................................................................228
Fig 11-1 RTC block diagram..............................................................................................................................................................231
Fig 11-2 RTC prescale diagram.........................................................................................................................................................232
Fig 11-3 RTC clock select diagram....................................................................................................................................................232
Fig 11-4 Calibration block diagram ..................................................................................................................................................233
Fig 11-5 xtal_req_32k block diagram...............................................................................................................................................233
Fig 13-1 Block diagram of I2C ...........................................................................................................................................................246
Fig 13-2 Master/Slave and Transmitter/Receiver relationships ......................................................................................................247
Fig 13-3 Data transfer on the I2C bus...............................................................................................................................................248
Fig 13-4 START and STOP conditions ...............................................................................................................................................249
Fig 13-5 7-bit address format...........................................................................................................................................................249
Fig 13-6 10-bit address format.........................................................................................................................................................249
Fig 13-7 Master-Transmitter protocol .............................................................................................................................................250
Fig 13-8 Master-Receiver protocol ..................................................................................................................................................251
Fig 13-9 START BYTE transfer...........................................................................................................................................................251
Fig 13-10 General call address format .............................................................................................................................................251
Fig 13-11 NULL DATA transfer format..............................................................................................................................................252
Fig 13-12 IC_DATA_CMD register content.......................................................................................................................................252
Fig 13-13 Master transmitter —Tx FIFO empties/STOP generation ...............................................................................................252
Fig 13-14 Master receiver —Tx FIFO empties/STOP generation ....................................................................................................253
Fig 13-15 Master transmitter —Restart bit of IC_DATA_CMD is set ..............................................................................................253
Fig 13-16 Master receiver —Restart bit of IC_DATA_CMD is set....................................................................................................253
Fig 13-17 Master transmitter —Stop bit of IC_DATA_CMD set/Tx FIFO not empty .......................................................................253
Fig 13-18 Master receiver —Stop bit of IC_DATA_CMD set/Tx FIFO not empty ............................................................................254
Fig 13-19 Multiple master arbitration..............................................................................................................................................254
Fig 13-20 Multi-Master clock synchronization.................................................................................................................................255
Fig 13-21 I2C 8-bit FIFO content with transfer control register .......................................................................................................260
Fig 14-1 UART block diagram ...........................................................................................................................................................284
Fig 14-2 Clock structure of KM0 log UART Rx path ..........................................................................................................................298
Fig 14-3 Clock structure of KM0 LUART Rx path ..............................................................................................................................299
Fig 14-4 Clock structure of KM4 UART0 Rx path..............................................................................................................................299
Fig 14-5 Relationship between IrDA signal and UART signal ...........................................................................................................300
Fig 14-6 Signal connection in auto-flow control mode ....................................................................................................................300
Fig 14-7 DMA interface timing diagram...........................................................................................................................................301
Fig 14-8 DMA interface timing diagram...........................................................................................................................................301
Fig 15-1 IR signal model ...................................................................................................................................................................302
Fig 15-2 IR Tx flow............................................................................................................................................................................302
Fig 15-3 IR Rx flow............................................................................................................................................................................303
Fig 15-4 IR block diagram.................................................................................................................................................................303
Fig 15-5 Tx output level....................................................................................................................................................................313
Fig 16-1 Key-Scan block diagram.....................................................................................................................................................314
Fig 16-2 Typical application setup with external keypad.................................................................................................................315
Fig 16-3 Key-Scan flow .....................................................................................................................................................................316
Fig 16-4 Key-Scan timing..................................................................................................................................................................317
Fig 16-5 Difference of FIFO items between two work modes .........................................................................................................317
Fig 16-6 FIFO structure.....................................................................................................................................................................318
Fig 16-7 Clock domain diagram........................................................................................................................................................319
Fig 16-8 4*3 keypad example ..........................................................................................................................................................320
Fig 16-9 Shadow key condition ........................................................................................................................................................320
Fig 16-10 Correct three-key condition .............................................................................................................................................321
Fig 17-1 Audio codec diagram..........................................................................................................................................................329

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Fig 17-2 Cap-less mode connection with headphone jack...............................................................................................................333
Fig 17-3 Differential mode connection with headphone jack..........................................................................................................334
Fig 17-4 Single-end mode connection with headphone jack...........................................................................................................334
Fig 17-5 Line-in mode connection....................................................................................................................................................335
Fig 17-6 Analog MIC single-end mode connection ..........................................................................................................................335
Fig 17-7 Analog MIC differential mode connection .........................................................................................................................335
Fig 17-8 Digital MIC mono mode connection ..................................................................................................................................336
Fig 17-9 Digital MIC stereo mode connection..................................................................................................................................336
Fig 17-10 Mono PDM format ...........................................................................................................................................................336
Fig 17-11 Stereo PDM format ..........................................................................................................................................................337
Fig 17-12 I2S acting as PDM..............................................................................................................................................................337
Fig 18-1 Ameba-D ACC + AC architecture ........................................................................................................................................381
Fig 18-2 ACC block diagram .............................................................................................................................................................382
Fig 18-3 I2S audio data format .........................................................................................................................................................385
Fig 18-4 Left-Justified data format...................................................................................................................................................386
Fig 18-5 PCM mode B data format...................................................................................................................................................386
Fig 18-6 PCM mode B-N data format...............................................................................................................................................386
Fig 18-7 PCM mode A data format ..................................................................................................................................................386
Fig 18-8 PCM mode A-N data format...............................................................................................................................................387
Fig 18-9 SI write timing ....................................................................................................................................................................387
Fig 18-10 SI read timing ...................................................................................................................................................................388
Fig 18-11 ACC clock architecture .....................................................................................................................................................388
Fig 19-1 SPI block diagram ...............................................................................................................................................................395
Fig 19-2 SPI Serial Format (SCPH = 0)...............................................................................................................................................397
Fig 19-3 SPI Serial Format Continuous Transfers (SCPH = 0 and SS toggling) ..................................................................................397
Fig 19-4 SPI Serial Format Continuous Transfers (SCPH = 0 and SS not-toggling) ...........................................................................397
Fig 19-5 SPI Serial Format (SCPH = 1)...............................................................................................................................................398
Fig 19-6 SPI Serial Format Continuous Transfers (SCPH = 1)............................................................................................................398
Fig 19-7 Maximum sclk_out/ssi_clk Ratio........................................................................................................................................399
Fig 19-8 SPI Configured as master device ........................................................................................................................................401
Fig 19-9 Effects of round trip routing delays on sclk_out signal ......................................................................................................401
Fig 20-1 MCU I/F + LCM with GRAM ................................................................................................................................................422
Fig 20-2 RGB I/F + LCM without GRAM............................................................................................................................................422
Fig 20-3 LCDC block diagram............................................................................................................................................................422
Fig 20-4 Two data paths...................................................................................................................................................................423
Fig 20-5 MCU I/O mode application scenario ..................................................................................................................................423
Fig 20-6 DMA mode application scenario ........................................................................................................................................424
Fig 20-7 MCU interface ....................................................................................................................................................................424
Fig 20-8 MCU I/F command setting timing parameters ..................................................................................................................425
Fig 20-9 MCU I/F data writing timing parameters ...........................................................................................................................425
Fig 20-10 MCU I/F read command timing parameters ....................................................................................................................425
Fig 20-11 MCU VSYNC mode timing ................................................................................................................................................426
Fig 20-12 MCU TE mode timing .......................................................................................................................................................426
Fig 20-13 MCU TE mode frame synchronization .............................................................................................................................426
Fig 20-14 8080 I/F 8-bit output........................................................................................................................................................427
Fig 20-15 8080 I/F 16-bit output......................................................................................................................................................427
Fig 20-16 RGB interface ...................................................................................................................................................................428
Fig 20-17 RGB timing........................................................................................................................................................................428
Fig 20-18 RGB DE mode timing ........................................................................................................................................................429
Fig 20-19 RGB I/F 6-bit output .........................................................................................................................................................429
Fig 20-20 RGB I/F 16-bit output .......................................................................................................................................................430
Fig 20-21 LED interface ....................................................................................................................................................................431
Fig 20-22 LED control timing............................................................................................................................................................432

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Fig 20-23 LED control diagram.........................................................................................................................................................433
Fig 20-24 LED color mapping: single color and single channel ........................................................................................................433
Fig 20-25 LED color capping: single color and two channels ...........................................................................................................434
Fig 20-26 LED color mapping: two colors and single channel..........................................................................................................434
Fig 20-27 LED color mapping: two colors and two channels ...........................................................................................................435
Fig 20-28 LED color mapping: three colors and single channel .......................................................................................................435
Fig 20-29 LED color mapping: three colors and two channels.........................................................................................................436
Fig 21-1 Q-Decoder application scenario.........................................................................................................................................453
Fig 21-2 Quadrature signal...............................................................................................................................................................454
Fig 21-3 Q-Decoder block diagram ..................................................................................................................................................454
Fig 21-4 Quadrature decoder phase state .......................................................................................................................................455
Fig 21-5 Position count state when CNT_SC = 0 ..............................................................................................................................455
Fig 21-6 Position count state when CNT_SC = 1 ..............................................................................................................................456
Fig 21-7 Position counter reset on index pulse (forward direction) ................................................................................................456
Fig 21-8 Position counter reset on index pulse (reverse direction).................................................................................................456
Fig 21-9 IDX_INV = 0, position counter reset on (PHA, PHB) = (1, 0) ...............................................................................................457
Fig 21-10 IDX_INV = 1, position counter reset on (PHA, PHB) = (1, 0) .............................................................................................457
Fig 21-11 Auto-index mechanism when IDX_INV = 0 ......................................................................................................................458
Fig 21-12 Auto-index mechanism when IDX_INV = 1 ......................................................................................................................458
Fig 21-13 Rotation count when RC_MOD = 1 ..................................................................................................................................459
Fig 21-14 Velocity measurement unit timing flow...........................................................................................................................460
Fig 22-1 I2S mono/stereo audio-out interface configuration...........................................................................................................472
Fig 22-2 I2S 5.1 channel audio-out interface configuration .............................................................................................................473
Fig 22-3 Signal lines in I2S data format.............................................................................................................................................473
Fig 22-4 Transmitter as the master..................................................................................................................................................474
Fig 22-5 Receiver as the master.......................................................................................................................................................474
Fig 22-6 Controller as the master ....................................................................................................................................................475
Fig 22-7 I2S Philips standard.............................................................................................................................................................475
Fig 22-8 Left-justified standard........................................................................................................................................................476
Fig 22-9 Right-justified standard......................................................................................................................................................476
Fig 22-10 I2S clock tree.....................................................................................................................................................................477
Fig 22-11 Memory block ..................................................................................................................................................................478
Fig 22-12 FIFO allocation of mono channel (sample bit = 16-bit)....................................................................................................479
Fig 22-13 FIFO allocation of mono channel (sample bit = 32-bit)....................................................................................................479
Fig 22-14 FIFO allocation of stereo channel (sample bit = 16-bit) ...................................................................................................480
Fig 22-15 FIFO allocation of stereo channel (sample bit = 24-bit) ...................................................................................................480
Fig 22-16 FIFO allocation of stereo channel (sample bit = 32-bit) ...................................................................................................481
Fig 22-17 FIFO allocation of 5.1 channel (sample bit = 16-bit) ........................................................................................................481
Fig 22-18 FIFO allocation of 5.1 channel (sample bit = 24-bit) ........................................................................................................482
Fig 22-19 FIFO allocation of 5.1 channel (sample bit = 32-bit) ........................................................................................................482

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List of Figures
Fig 1-1 System architecture ...............................................................................................................................................................23
Fig 4-1 NVIC diagram..........................................................................................................................................................................36
Fig 6-1 Pad diagram ...........................................................................................................................................................................45
Fig 6-2 Selecting an alternate function on Ameba-D .........................................................................................................................49
Fig 7-1 IPC system architecture..........................................................................................................................................................51
Fig 7-2 IPC interrupt request..............................................................................................................................................................52
Fig 7-3 IPC hardware semaphore mechanism ...................................................................................................................................52
Fig 8-1 Block diagram.........................................................................................................................................................................58
Fig 8-2 Control RTL block diagram .....................................................................................................................................................59
Fig 8-3 Read back of external gpio_ext_portXdata timing................................................................................................................61
Fig 8-4 Interrupt RTL block diagram...................................................................................................................................................62
Fig 8-5 Debounce RTL diagram ..........................................................................................................................................................62
Fig 8-6 Debounce timing with asynchronous reset Flip-Flops ...........................................................................................................63
Fig 8-7 Synchronization and edge detect interrupt generation when GPIO_INT_BOTH_EDGE=0 ....................................................64
Fig 8-8 Interrupt edge detection and interrupt clear timing when GPIO_SYNC_PA_INTERRPUTS = 1 (metastability included).......64
Fig 8-9 Interrupt edge detection and interrupt clear timing when GPIO_SYNC_PA_INTERRPUTS = 0 (metastability removed) ......65
Fig 8-10 Write to interrupt clear register, coincident with detection of new interrupt ....................................................................66
Fig 8-11 Synchronization and edge detect interrupt generation when GPIO_INT_BOTH_EDGE=0 ..................................................66
Fig 8-12 Interrupt edge detection and interrupt clear timing when GPIO_SYNC_PA_INTERRPUTS = 1 and
GPIO_INT_BOTH_EDGE=1 (metastability included).................................................................................................................67
Fig 8-13 Interrupt edge detection and interrupt clear timing when GPIO_SYNC_PA_INTERRPUTS = 0 and
GPIO_INT_BOTH_EDGE=1 (metastability Removed)................................................................................................................68
Fig 8-14 Level-sensitive interrupt RTL diagram..................................................................................................................................68
Fig 8-15 Active-low level-sensitive interrupt generation timing........................................................................................................69
Fig 8-16 Relationship between APB and APB slave data widths........................................................................................................69
Fig 9-1 Block diagram of DMAC .........................................................................................................................................................86
Fig 9-2 Peripheral-to-Peripheral DMA transfer on the same AHB layer ............................................................................................87
Fig 9-3 Peripheral-to-Memory DMA transfer on separate AHB layers ..............................................................................................88
Fig 9-4 DMA Transfer Hierarchy for Non-Memory Peripherals .........................................................................................................89
Fig 9-5 DMA transfer hierarchy for memory......................................................................................................................................89
Fig 9-6 Hardware handshaking interface ...........................................................................................................................................95
Fig 9-7 Burst transaction –pclk = hclk ...............................................................................................................................................96
Fig 9-8 Back-to-Back burst transactions –hclk = 2*per_clk...............................................................................................................97
Fig 9-9 Single transaction...................................................................................................................................................................98
Fig 9-10 Burst followed by Back-to-Back single transactions.............................................................................................................98
Fig 9-11 Early-Terminated burst transaction .....................................................................................................................................98
Fig 9-12 Burst transaction ignored during active single transaction .................................................................................................99
Fig 9-13 Generation of dma_req and dma_single by source .............................................................................................................99
Fig 9-14 Hardware handshaking interface .......................................................................................................................................101
Fig 9-15 Burst transaction followed by single transaction that terminates block ...........................................................................101
Fig 9-16 Single transaction followed by burst transaction that terminates block ...........................................................................102
Fig 9-17 Breakdown of Block Transfer .............................................................................................................................................104
Fig 9-18 Channel FIFO contents at times indicated in Fig 9-17........................................................................................................104
Fig 9-19 Breakdown of block transfer for DMAH_CH_FIFO_DEPTH = 8 ..........................................................................................105
Fig 9-20 Breakdown of block transfer where max_abrst = 2, Case 1...............................................................................................106
Fig 9-21 Channel FIFO contents at times indicated in Fig 9-20........................................................................................................106
Fig 9-22 Breakdown of block transfer where max_abrst = 2, Case 2...............................................................................................107

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Fig 9-23 Channel FIFO contents at times indicated in Fig 9-22........................................................................................................107
Fig 9-24 Breakdown of block transfer..............................................................................................................................................108
Fig 9-25 Source FIFO contents at time indicated in Fig 9-24............................................................................................................109
Fig 9-26 Source FIFO contents where watermark level is dynamically adjusted.............................................................................109
Fig 9-27 Block transfer to destination..............................................................................................................................................110
Fig 9-28 Block transfer up to time ‘t4’ .............................................................................................................................................112
Fig 9-29 Source, DMAC channel and destination FIFOs at time ‘t4’ in Fig 9-26...............................................................................112
Fig 9-30 FIFO status after early-terminated burst ...........................................................................................................................113
Fig 9-31 Data loss when pre-fetching is enabled .............................................................................................................................114
Fig 9-32 Timing exception on dma_finish to source peripheral ......................................................................................................115
Fig 9-33 Case of no data loss when pre-fetching is enabled............................................................................................................116
Fig 9-34 Source enters single transaction region when destination asserts dma_last[1] ...............................................................117
Fig 9-35 Case where source does not enter single transaction region when destination asserts dma_last[1]...............................117
Fig 9-36 Data loss when data pre-fetching is disabled.....................................................................................................................119
Fig 9-37 Transaction request through peripheral interrupt.............................................................................................................120
Fig 9-38 Flow control configurations ...............................................................................................................................................121
Fig 9-39 Case 1 watermark levels where SSI.DMATDLR = 2.............................................................................................................122
Fig 9-40 Case 2 watermark levels where SSI.DMATDLR = 6.............................................................................................................123
Fig 9-41 SSI receive FIFO ..................................................................................................................................................................124
Fig 9-42 Arbitration flow for master bus interface ..........................................................................................................................127
Fig 9-43 Example of destination scatter transfer.............................................................................................................................129
Fig 9-44 Source gather when SGR.SGI = 0x1 ....................................................................................................................................129
Fig 9-45 Multi-block transfer using linked lists when DMAH_CHx_STAT_SRC set to true...............................................................172
Fig 9-46 Multi-block transfer using linked lists when DMAH_CHx_STAT_SRC set to false ..............................................................173
Fig 9-47 Mapping of block descriptor (LLI) in memory to channel registers when DMAH_CHx_STAT_SRC set to true ..................173
Fig 9-48 Mapping of block descriptor (LLI) in memory to channel registers when DMAH_CHx_STAT_SRC set to false .................173
Fig 9-49 Flowchart for DMA programming example .......................................................................................................................177
Fig 9-50 Multi-block with linked address for source and destination..............................................................................................181
Fig 9-51 Multi-block with linked address for source and destination where SARx and DARx between successive blocks are
contiguous..............................................................................................................................................................................181
Fig 9-52 DMA transfer flow for source and destination linked list address.....................................................................................182
Fig 9-53 Multi-block DMA transfer with source and destination address auto-reloaded ...............................................................183
Fig 9-54 DMA transfer flow for source and destination address auto-reloaded .............................................................................184
Fig 9-55 Multi-block DMA transfer with source address auto-reloaded and linked list destination address .................................186
Fig 9-56 DMA transfer flow for source address auto-reloaded and linked list destination address ...............................................187
Fig 9-57 Multi-block DMA transfer with source address auto-reloaded and contiguous destination address ...............................189
Fig 9-58 DMA transfer flow for source address auto-reloaded and contiguous destination address.............................................189
Fig 9-59 Multi-block DMA transfer with linked list source address and contiguous destination address.......................................191
Fig 9-60 DMA transfer flow for source address auto-reloaded and contiguous destination address .............................................192
Fig 10-1 Block diagram.....................................................................................................................................................................194
Fig 10-2 TIM4 block diagram............................................................................................................................................................196
Fig 10-3 Statistic pulse width mode diagram (positive edge of TRGI is active for capture).............................................................197
Fig 10-4 Statistic pulse number mode diagram (positive edge of TRGI is active for capture, ARR=E6)...........................................198
Fig 10-5 PWM timer block diagram .................................................................................................................................................199
Fig 10-6 Counter timing diagram with prescaler division change from 1 to 2.................................................................................200
Fig 10-7 Counter timing diagram with prescaler division change from 1 to 4.................................................................................201
Fig 10-8 Counter timing diagram (internal clock divided by 1)........................................................................................................202
Fig 10-9 Counter timing diagram (internal clock divided by 2)........................................................................................................202
Fig 10-10 Counter timing diagram (internal clock divided by 4)......................................................................................................202
Fig 10-11 Counter timing diagram (internal clock divided by N) .....................................................................................................203
Fig 10-12 Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded).........................................................203
Fig 10-13 Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) ...............................................................204
Fig 10-14 Edge-aligned PWM waveforms (ARR=8, CCxP=0) ............................................................................................................205

List of Figures
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19
Fig 10-15 One-pulse mode timing....................................................................................................................................................205
Fig 10-16 Block diagram...................................................................................................................................................................227
Fig 10-17 Synchronous data diagram...............................................................................................................................................228
Fig 11-1 RTC block diagram..............................................................................................................................................................231
Fig 11-2 RTC prescale diagram.........................................................................................................................................................232
Fig 11-3 RTC clock select diagram....................................................................................................................................................232
Fig 11-4 Calibration block diagram ..................................................................................................................................................233
Fig 11-5 xtal_req_32k block diagram...............................................................................................................................................233
Fig 13-1 Block diagram of I2C ...........................................................................................................................................................246
Fig 13-2 Master/Slave and Transmitter/Receiver relationships ......................................................................................................247
Fig 13-3 Data transfer on the I2C bus...............................................................................................................................................248
Fig 13-4 START and STOP conditions ...............................................................................................................................................249
Fig 13-5 7-bit address format...........................................................................................................................................................249
Fig 13-6 10-bit address format.........................................................................................................................................................249
Fig 13-7 Master-Transmitter protocol .............................................................................................................................................250
Fig 13-8 Master-Receiver protocol ..................................................................................................................................................251
Fig 13-9 START BYTE transfer...........................................................................................................................................................251
Fig 13-10 General call address format .............................................................................................................................................251
Fig 13-11 NULL DATA transfer format..............................................................................................................................................252
Fig 13-12 IC_DATA_CMD register content.......................................................................................................................................252
Fig 13-13 Master transmitter —Tx FIFO empties/STOP generation ...............................................................................................252
Fig 13-14 Master receiver —Tx FIFO empties/STOP generation ....................................................................................................253
Fig 13-15 Master transmitter —Restart bit of IC_DATA_CMD is set ..............................................................................................253
Fig 13-16 Master receiver —Restart bit of IC_DATA_CMD is set....................................................................................................253
Fig 13-17 Master transmitter —Stop bit of IC_DATA_CMD set/Tx FIFO not empty .......................................................................253
Fig 13-18 Master receiver —Stop bit of IC_DATA_CMD set/Tx FIFO not empty ............................................................................254
Fig 13-19 Multiple master arbitration..............................................................................................................................................254
Fig 13-20 Multi-Master clock synchronization.................................................................................................................................255
Fig 13-21 I2C 8-bit FIFO content with transfer control register .......................................................................................................260
Fig 14-1 UART block diagram ...........................................................................................................................................................284
Fig 14-2 Clock structure of KM0 log UART Rx path ..........................................................................................................................298
Fig 14-3 Clock structure of KM0 LUART Rx path ..............................................................................................................................299
Fig 14-4 Clock structure of KM4 UART0 Rx path..............................................................................................................................299
Fig 14-5 Relationship between IrDA signal and UART signal ...........................................................................................................300
Fig 14-6 Signal connection in auto-flow control mode ....................................................................................................................300
Fig 14-7 DMA interface timing diagram...........................................................................................................................................301
Fig 14-8 DMA interface timing diagram...........................................................................................................................................301
Fig 15-1 IR signal model ...................................................................................................................................................................302
Fig 15-2 IR Tx flow............................................................................................................................................................................302
Fig 15-3 IR Rx flow............................................................................................................................................................................303
Fig 15-4 IR block diagram.................................................................................................................................................................303
Fig 15-5 Tx output level....................................................................................................................................................................313
Fig 16-1 Key-Scan block diagram.....................................................................................................................................................314
Fig 16-2 Typical application setup with external keypad.................................................................................................................315
Fig 16-3 Key-Scan flow .....................................................................................................................................................................316
Fig 16-4 Key-Scan timing..................................................................................................................................................................317
Fig 16-5 Difference of FIFO items between two work modes .........................................................................................................317
Fig 16-6 FIFO structure.....................................................................................................................................................................318
Fig 16-7 Clock domain diagram........................................................................................................................................................319
Fig 16-8 4*3 keypad example ..........................................................................................................................................................320
Fig 16-9 Shadow key condition ........................................................................................................................................................320
Fig 16-10 Correct three-key condition .............................................................................................................................................321
Fig 17-1 Audio codec diagram..........................................................................................................................................................329

Ameba-D User Manual
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20
Fig 17-2 Cap-less mode connection with headphone jack...............................................................................................................333
Fig 17-3 Differential mode connection with headphone jack..........................................................................................................334
Fig 17-4 Single-end mode connection with headphone jack...........................................................................................................334
Fig 17-5 Line-in mode connection....................................................................................................................................................335
Fig 17-6 Analog MIC single-end mode connection ..........................................................................................................................335
Fig 17-7 Analog MIC differential mode connection .........................................................................................................................335
Fig 17-8 Digital MIC mono mode connection ..................................................................................................................................336
Fig 17-9 Digital MIC stereo mode connection..................................................................................................................................336
Fig 17-10 Mono PDM format ...........................................................................................................................................................336
Fig 17-11 Stereo PDM format ..........................................................................................................................................................337
Fig 17-12 I2S acting as PDM..............................................................................................................................................................337
Fig 18-1 Ameba-D ACC + AC architecture ........................................................................................................................................381
Fig 18-2 ACC block diagram .............................................................................................................................................................382
Fig 18-3 I2S audio data format .........................................................................................................................................................385
Fig 18-4 Left-Justified data format...................................................................................................................................................386
Fig 18-5 PCM mode B data format...................................................................................................................................................386
Fig 18-6 PCM mode B-N data format...............................................................................................................................................386
Fig 18-7 PCM mode A data format ..................................................................................................................................................386
Fig 18-8 PCM mode A-N data format...............................................................................................................................................387
Fig 18-9 SI write timing ....................................................................................................................................................................387
Fig 18-10 SI read timing ...................................................................................................................................................................388
Fig 18-11 ACC clock architecture .....................................................................................................................................................388
Fig 19-1 SPI block diagram ...............................................................................................................................................................395
Fig 19-2 SPI Serial Format (SCPH = 0)...............................................................................................................................................397
Fig 19-3 SPI Serial Format Continuous Transfers (SCPH = 0 and SS toggling) ..................................................................................397
Fig 19-4 SPI Serial Format Continuous Transfers (SCPH = 0 and SS not-toggling) ...........................................................................397
Fig 19-5 SPI Serial Format (SCPH = 1)...............................................................................................................................................398
Fig 19-6 SPI Serial Format Continuous Transfers (SCPH = 1)............................................................................................................398
Fig 19-7 Maximum sclk_out/ssi_clk Ratio........................................................................................................................................399
Fig 19-8 SPI Configured as master device ........................................................................................................................................401
Fig 19-9 Effects of round trip routing delays on sclk_out signal ......................................................................................................401
Fig 20-1 MCU I/F + LCM with GRAM ................................................................................................................................................422
Fig 20-2 RGB I/F + LCM without GRAM............................................................................................................................................422
Fig 20-3 LCDC block diagram............................................................................................................................................................422
Fig 20-4 Two data paths...................................................................................................................................................................423
Fig 20-5 MCU I/O mode application scenario ..................................................................................................................................423
Fig 20-6 DMA mode application scenario ........................................................................................................................................424
Fig 20-7 MCU interface ....................................................................................................................................................................424
Fig 20-8 MCU I/F command setting timing parameters ..................................................................................................................425
Fig 20-9 MCU I/F data writing timing parameters ...........................................................................................................................425
Fig 20-10 MCU I/F read command timing parameters ....................................................................................................................425
Fig 20-11 MCU VSYNC mode timing ................................................................................................................................................426
Fig 20-12 MCU TE mode timing .......................................................................................................................................................426
Fig 20-13 MCU TE mode frame synchronization .............................................................................................................................426
Fig 20-14 8080 I/F 8-bit output........................................................................................................................................................427
Fig 20-15 8080 I/F 16-bit output......................................................................................................................................................427
Fig 20-16 RGB interface ...................................................................................................................................................................428
Fig 20-17 RGB timing........................................................................................................................................................................428
Fig 20-18 RGB DE mode timing ........................................................................................................................................................429
Fig 20-19 RGB I/F 6-bit output .........................................................................................................................................................429
Fig 20-20 RGB I/F 16-bit output .......................................................................................................................................................430
Fig 20-21 LED interface ....................................................................................................................................................................431
Fig 20-22 LED control timing............................................................................................................................................................432