Renesas 8V19N49 Series User manual

Guide
R31UH0005EU0100 Rev.1.0 Page 1
Jun 3, 2021 © 2021 Renesas Electronics
This document provides board-level hardware design guidelines for the 8V19N49x family products (see table).
The hardware design guidelines are similar for this product family. In this document, the 8V19N490 device is used
for demonstration purposes.
Contents
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Power Rails . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.1 Bypass Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.2 Power Supply Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3. Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1 2nd Order Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2 3rd Order Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.3 Loop Filter Calculation Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.3.1 Loop Filter for VCXO PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.3.2 Loop Filter for VCO PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4. Input Output Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1 Input Termination for Reference Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2 Output Terminations for QCLK and QREF Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2.1 LVPECL Type Driver Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2.2 LVDS Type Driver Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2.3 DC Coupling Interface for QREF Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5. Schematic Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 1. 8V19N49x Family
Part Number VCO Frequency (GHz)
8V19N490, 8V19N490A, 8V19N490B, 8V19N492 ~2.94912
8V19N490-19 ~1.966
8V19N490-24, 8V19N491-24 ~2.4576
8V19N491-36 ~3.6864
8V19N492-39 ~3.93216
8V19N49x Hardware Design

R31UH0005EU0100 Rev.1.0 Page 2
Jun 3, 2021
8V19N49x Hardware Design Guide
1. Overview
As indicated, this document provides board-level hardware design guidelines for the 8V19N49x product family.
The document also recommends power rail handling, loop filter calculation, and input/output termination. A
general schematic example is shown in Figure 1. A more detailed version is available upon request.
Figure 1. 8V19N490 Schematic Example
2. Power Rails
2.1 Bypass Capacitors
Bypass capacitors are required to filter out the system noise from switching power supplies and switching signal
interference from other parts of the system. Figure 1 shows examples of bypass capacitors on the schematic. A
PCB layout example is also available upon request. The type of bypass capacitor will depend on the noise level
and noise frequencies in the system environment. The synthesizer output driver switching can also cause power
rail noise. These noises can also interfere with other parts of the circuit or cause spur on other output channels.
The bypass capacitor values are usually in the range of 0.01uF to 0.1uF; however, other values can be used.
Typical capacitor sizes are 0603, 0402, or 0201 with low ESR. The dielectric types typically are X5R or X7R. The
smaller size allows the capacitor to be placed close to the power pin and reduces the trace length. Some capacitor
vendors such as AVX provide online tools and models to provide the frequency response of the capacitors.
Figure 2 to Figure 5 show the frequency response of various value capacitors provided by the capacitor supplier
AVX. The frequency response plot shows that the smaller value capacitor can filter out high frequency noise and a
larger value capacitor can filter out lower frequency noise. Typical power supply switching frequency can be
Place on the Top Layer
Layout Note: Place the bypass
capacitors (0201) next to the power
pins
VCO-VC
Place close to
the DUT
Close to
the pin
VCXO-VC
Place close to DUT Pins Place close
toVCXO Pins 1
Close to the
pins if
possible
VCXO=122.88 MHz
LVPECL
1R%XLOWLQ7HUPLQDWLRQ
/9'66W\OH7HUPLQDWLRQ'&FRXSOLQJ([DPSOH
1R%XLOWLQ
7HUPLQDWLRQ
/9'66W\OH7HUPLQDWLRQ$&FRXSOLQJ([DPSOH
&/.[Q&/.[,QSXWLQWHU DFH([DPSOH
'L HUHQWLDO6LJQDO
6DPHFLUFXLWFDQEHGXSOLFDWHG RU
&/.Q&/.LQSXW
Loop Filter values shown here are
example only. Other values can also
be used. It depends on the system
loop band width requirementn.
/9'66W\OH7HUPLQDWLRQ$&FRXSOLQJH[DPSOH RURKPODE
HTXLSPHQWPRQLWRULQJHJSKDVHQRLVHPHDVXUHPHQW
Keep this trace from noisy source
Keep this trace from
noisy source
VDD_LCF(Clean)
LVPECL Termination Example
There are many way to
terminate LVPECL driver
There are many way to
terminate LVPECL driver
VDD1
VDD_SYNC
VDD_QCLKB
VDD_QREFB
VDD_QCLKD
VDD_QREFD
VDD_QCLKE
VDD_SPI
VDD_CP2
VDD_LCV
VDD_QREFC
VDD_QCLKC
VDD_LCF
VDD_QCLKA
VDD_QREFA
VDD3
VCC_VCXO
VCC_VCXO
VDD
VREG_3.3V
VDD_SPI
LFV
SDAT
nINT
nCS
SCLK
LOCK
LFV
Q_VCXO
nQ_VCXO
Q_VCXO
nQ_VCXO
R16
2.8K, 1%
Zo = 50
R51
50
U5
VCXO_5mmx7mm_6pin_long_pad
VCONT
1
OE
2
GND
3Q4
nQ 5
VCC 6
R18
100
R7 1k
C3
100p
C5
0.1u
C28
0.1u
C19
100p
C13
0.1u
TP1
C9
100p
C17
High Impedance
+
-
R22
33k
R12
10K
C14
C4
0.1u
C29
0.1u
R15
10K
High Impedance Input
+
-
Zo = 50
C15
C32
0.1u
C31
33p
U1
IDT8V19N490
nQCLKB0 A1
QCLKB0 A2
VDD_QCLKB A3
nQREF_B0 A4
QREF_B0 A5
nQCLK_B1 B1
QCLKB1 B2
VDD_QREFB B3
nQREF_B1 B4
QREF_B1 B5 VDD_CP
B6 nOSC
B7 VDD_OSC
B8 QCLK_A1
B9 nQCLK_A1
B10
LFV
A6 OSC
A7 GND_A8
A8 QCLK_A0
A9 nQCLKA0
A10
GND_C1 C1
GND_C2 C2
GND_C3 C3
VDD_QREFD C4
SELSV C5 GND_C6
C6 X1
C7 nINT
C8 QCLK_A2
C9 nQCLK_A2
C10
nQCLK_D D1
QCLK_D D2
VDD_CLLKD D3
nQREF_D D4
QREF_D D5 GND_D6
D6 X2
D7 GND_D8
D8 VDD_QREFA
D9 VDD_CLKA
D10
GND_E1 E1
GND_E2 E2
VCC_SPI E3
nCS E4
SCLK E5 GND_E6
E6 GND_E7
E7 SDAT
E8 QREF_A2
E9 nQREF_A2
E10
nQREF_C0 F1
QREF_C0 F2
EXT_SYS F3
CLK3 F4
CLK2 F5 CLK1
F6 CLK0
F7 RES_CAL
F8 QREF_A1
F9 nQREF_A1
F10
nQREF_C1 G1
QREF_C1 G2
VDD_INP G3
nQCLK3 G4
nQCLK2 G5 nQCLK1
G6 nCLK0
G7 LOCK
G8 QREF_A0
G9 nQREF_A0
G10
VDD_CLKC H1
VDD_QREF_C H2
GND_H3 H3
GND_H4 H4
GND_H5 H5 GND_H6
H6 VDD_SYNC
H7 GND_H8
H8 GND_H9
H9 GND_H10
H10
nQCLK_C0 J1
QCLLK_C0 J2
GND_J3 J3
VDD_LCV J4
CR0 J5 GND_J6
J6 GND_J7
J7 GND_J8
J8 QCLK_E1
J9 nQCLK_E1
J10
nQCLK_C1 K1
QCLK_C1 K2
GND_K3 K3
VDD_LCF K4
LFFR K5 LFF
K6 VDD_CPF
K7 VDD_QCLKE
K8 QCLK_E0
K9 nQCLK_E0
K10
Zo
R8
10K
C11
J1
R10
5.1K
C7
100p
C16
0.1u
R14
10K
Zo
R24
np (49.9)
C38
0.1uF
C8
0.1u
C22
0.1u
JP1
LVDS Driver
R11
5.1K
R53
50
C12
0.1u
C24
0.1u
C37
1u
C35
4.7n
C30
0.1u
C23
0.1u
C39
100pF
C27
100p
R5
100
C10
0.1u
C2
0.1u
R13
2 x Zo
C18
0.1u
R19
np (49.9)
C6
0.1u
Zo = 50
C20
0.1u
R20 51k
R9
100
C26
4.7u
C21
0.1u
Zo = 50
J2
C34
27n
C1
0.1u
R52
50
QREFD0_N
QCLKE0_N
QCLKE1_P
QCLKB0_N
QCLKB1_P
LFF
CLK1
QREFA1_N
QCLKA2_P
QREFA2_N
QREFA2_P
QREFA0_P
QREFA0_N
QCLKE1_N
QCLKE0_P
QREFA1_P
QCLKC0_N
QCLKA0_P
QCLKA0_N
QCLKC0_P
QCLKA1_N
QCLKA1_P
QCLKA2_N
nCLK2
CLK2
CLK3
nCLK3
QCLKB1_N
QCLKB0_P
QCLKD0_N
QCLKD0_P
QREFB1_N
QREFB1_P
QREFB0_N
QREFB0_P
QREFD0_P
QREFC0_N
QREFC0_P
nCLK1
CLK0
QREFC1_N
QREFC1_P
LFFR
MCLK_P
MCLK_N
RES_CAL EXT_SYS
VC
OE
QCLKx
nQCLKx
QCLKx
nQCLKx
QCLKA0
nQCLKA0
nCLK0

R31UH0005EU0100 Rev.1.0 Page 3
Jun 3, 2021
8V19N49x Hardware Design Guide
approximately 50KHz to 2MHz. Switching noise from other parts of the system can be varied. A combination of
various values are suggested to cover low frequency and high frequency noise.
To minimize ESR between power pins and the bypass capacitors, Renesas suggests at least one bypass cap per
power pin and to place these capacitors as close as possible to the power pins. Thicker trace widths between the
bypass capacitor and power pin can also help reduce the ESR.
Figure 2. Example of a 100nF Bypass Capacitor Frequency Response
Figure 3. Example of a 10nF Bypass Capacitor Frequency Response

R31UH0005EU0100 Rev.1.0 Page 4
Jun 3, 2021
8V19N49x Hardware Design Guide
Figure 4. Example of Larger Value (4.7uF) Bypass Capacitor Frequency Response
Figure 5. Example of Smaller Value (100pF) Bypass Capacitor Frequency Response

R31UH0005EU0100 Rev.1.0 Page 5
Jun 3, 2021
8V19N49x Hardware Design Guide
2.2 Power Supply Isolation
Analog power rails require cleaner power to optimize the jitter performance of PLLs. Most parts in the N49x family
contain built-in LDOs. An external ultra-low noise LDO may not be required but it is recommended for reducing
power supply noise for noise-sensitive power lines such as VDD_LCF and the external VCXO. An LDO with a
noise level of less than 6uVrms from 10Hz to100kHz is recommended. This ultra-low noise LDO is mainly for the
external VCXO that does not have a built-in LDO, and this affects the performance of 100Hz to 100kHz region.
It is suggested to isolate the analog power rail from other high-noise power rails. The isolation can be
implemented through an RC low pass filter. The larger RC component values can reduce the cutoff frequency
further and clean up lower frequency noise. For the VDDO output supplies, to reduce output frequency
interference, the power rails between the output banks that operate at different output frequencies can be isolated
using separate LDOs or using 1 to 2 ohm resistors if they share the same power source. Additional smaller value
capacitors (e.g., 100pF) in parallel with the existing 0.1uF near the power pins can provide additional higher
frequency noise filtering.
3. Loop Filter
3.1 2nd Order Loop Filter
This section provides design guidelines for a 2nd order loop filter for PLL. A typical 2nd order loop filter is displayed
in Figure 6. In addition, a step-by-step calculation is provided to determine Rs, Cs, and Cp values. The required
parameters for this part are also provided. A software tool for calculating the loop filter values is also available.
Figure 6. Typical 2nd Order Loop Filter
1. Determine the desired loop bandwidth, fc. The fc must satisfy the following condition:
Where,
Fpd is phase-detector input frequency.
2. Calculate Rs.
Where,
Icp is charge pump current.
Kvco is VCO gain.
Cp
Charge Pump Driv er
Rs
Loop Filter Return
Cs
20
fc
Fpd

R31UH0005EU0100 Rev.1.0 Page 6
Jun 3, 2021
8V19N49x Hardware Design Guide
N is effective feedback divider.
Fvco is vco frequency.
Fpd is the phase detector input frequency.
3. Calculate Cs.
Where,
α is ratio between loop bandwidth and the zero frequency at zero, α = fc / fz, recommend α to be greater than
3.
fz is frequency at zero.
4. Calculate Cp.
Where,
fp is frequency at pole.
β is ratio between frequency at pole and loop bandwidth, β = fp/fc, recommend β greater than 3.
5. Verify maximum Phase Margin, PM.
Where,
The PM should be greater than 50 degrees.
3.2 3rd Order Loop Filter
This section provides design guidelines for a 3rd order loop filter. A typical 3rd order loop filter is displayed in
Figure 7.
Fpd
Fvco
N
)
*2
1
arctan( b
b
PM  

R31UH0005EU0100 Rev.1.0 Page 7
Jun 3, 2021
8V19N49x Hardware Design Guide
Figure 7. Typical 3rd Order Loop Filter
The Rs, Cs, and Cp can be the actual value used in the 2nd order loop filter. The following equation helps
determine the 3rd order loop filter R3 and C3.
1. Pick an R3 value. Suggest R3 ~ 1.5xRs
Where,
γ is ratio between the 1st pole frequency and the 2nd pole frequency. Suggest γ greater than 3.
2. The Timing Commander software tool is provided to calculate the loop filter component values. To use the
spread sheet, user can enters the follow parameters:
fc, Fpd, fvco, α and β
The software tool will provide the component values, Rs, Cs, and Cp as result. The tool will also calculate
maximum phase margin for verification.
The 3rd order loop filter, R3 and C3, are also calculated using the actual 2nd order loop filter components values.
3.3 Loop Filter Calculation Examples
3.3.1 Loop Filter for VCXO PLL
3.3.1.1 Second Order Loop Filter for the VCXO PLL
This section provides calculation examples for the VCXO PLL loop filter value. The 8V19N490 VCXO phase lock
loop block diagram is displayed in Figure 8. A 2nd order loop filter for VCXO is shown in Figure 9. In this example,
the reference CLK input frequency = 30.72MHz and a VCXO with output frequency of 122.88MHz is used.
Figure 8. 8V19N490 VCXO PLL Block Diagram
Rs
C3
Cs
R3
Charge Pump Driv er VCO Control Input
Loop Filter Return
Cp

R31UH0005EU0100 Rev.1.0 Page 8
Jun 3, 2021
8V19N49x Hardware Design Guide
Figure 9. Typical 2nd Order Loop Filter
To calculate loop filter component values for loop bandwidth Fc = 40Hz with the reference CLK input frequency
equals to 30.72MHz, set the input pre-divider Pv = 256. The phase detector input frequency Fpd = 0.12MHz. This
satisfies the condition of Fpd / Fc >> 20.
The VCXO frequency Fvcxo = 122.88MHz, the effective feedback divider.
N = Mv = Fvcxo / Fpd = 1024
Rs can be calculated from the equation,
Rs = 33k ohm
Kvco VCO gain can be found or derived from the VCXO datasheet. The VCO gain can also be measured from lab
experiments. In this example, we use Kvco = 10kHz/V.
The 8V19N490 charge pump current can be programmed from 50uA to 1.6mA. In this example, assume the
charge pump current is programmed to Icp = 800uA.
Cs can be calculated from the following equation,
For α = 8, Cs is calculated to be 0.99uF. Cs greater than this value can be used to ensure that the α is greater than
12. For example, the actual chosen value can be 1uF from a standard capacitor value.
Cp can be calculated from the following equation,
For β = 4, Cp = 31nF. Less than this value can be used for Cp to assure that the β is greater than 4 (e.g., actual
chosen value Cp can be 27nF).
Rs
VCXO-VCLVF
Cs
Cp

R31UH0005EU0100 Rev.1.0 Page 9
Jun 3, 2021
8V19N49x Hardware Design Guide
3.3.1.2 Third Order Loop Filter for the VCXO PLL
This section provides design guidelines for a 3rd order loop filter for the 8V19N490 VCXO PLL. A general 3rd
order loop filter is displayed in Figure 10.
Figure 10. Typical 3rd Order Loop Filter
The Rs, Cs, and Cp are chosen standard values from the 2nd order loop filter. In this example, the chosen values
are Rs = 33KOhm, Cs = 1uF, and Cp = 27nF. The following equation can help determine the 3rd order loop filter,
R3 and C3.
1. Choose an R3 value. Suggest R3 ~ 1.5xRs to ~2.5xRs or greater (e.g, R3 = 51KHz is used in this example).
C3 can be calculated using the following equation:
2. Pick γ = 4 in this example.
C3 is calculated to be 4.37nF. A closest standard capacitor value can be used.
Tabl e 2 shows some VCXO PLL Loop Filter examples for different VCXO frequencies. Other values can also be
used to meet other specific conditions and requirements.
Table 2. Loop Filter Examples
VCXO Frequency[1] 122.88MHz 30.72MHz
VCXO Made/Model Examples Epson,VG4513CA/CB
Epson VG3225EFN*
Crystek CVPD922
Crystek CHPD950
Crystek CVPD-037
Rakon RVX7050M
TXC
Vectron
Epson, TXC, Rakon
Typical VCXO Gain, Kvco 10k Hz/V 2.5k Hz/V
Loop Bandwidth, Fc ~40Hz ~40Hz
PDF, Phase Detector Input Frequency 120kHz 960kHz
Feedback Divider (N or Mv) 1024 32
Charge Pump Current Setting
(Can be slightly Adjusted to change
the loop band width)
800uA 800uA
Rs 33k Ohm 1k Ohm
Cs 1uF 10uF
Cp 27nF 330nF
LFV VCXO-VC
R3
Cp
Rs
C3
Cs

R31UH0005EU0100 Rev.1.0 Page 10
Jun 3, 2021
8V19N49x Hardware Design Guide
3.3.2 Loop Filter for VCO PLL
The 8V19N490 VCO phase lock loop diagram is displayed in Figure 11. The Fvco frequency is 2.94912GHz. In
this example, the 2949.12MHz VCO is used. A 2nd order loop filter for the VCO is shown in Figure 12.
Figure 11. VCO PLL Block Diagram
Figure 12. 2nd Order Loop Filter for the VCO
The board-level VCO 2nd order loop filter works in conjunction with the internal circuitries. A traditional loop filter
calculation method may not be accurate. After simulation and actual experiment, an example of external two-pole
loop filter value is provided in Tabl e 3.
R3 51k Ohm 1.8k Ohm
C3 4.7nF 33nF
1. Other VCXO frequencies can also be used with proper loop filter and parameter setting. Below are examples of VCXO order information:
* 122.88MHz - Epson VG3225EFN 122.88M-CJHHBA
* 245.76MHz - Epson VG3225ENN 245.76M-CJHHMA
* 491.52MHz - Epson VG3225ENN 491.52M-CJGHSA
Table 2. Loop Filter Examples (Cont.)
Cz
Cp
Rz
LFF
LFFR

R31UH0005EU0100 Rev.1.0 Page 11
Jun 3, 2021
8V19N49x Hardware Design Guide
4. Input Output Interface
4.1 Input Termination for Reference Clock Input
The 8V19N490 reference clock input CLK/nCLK is a high-impedance differential receiver. The inverting input
nCLK has weak bias to 1.2V. The input can accept signals from a standard 3.3V LVPECL or an LVDS driver
directly without AC coupling. The board-level termination at the CLK/nCLK input is determined by the driver type.
Figure 13 and Figure 14 provide examples of input interface without AC coupling. Figure 15 and Figure 16 provide
examples of input driven by a differential driver with AC coupling. This section discusses only few examples; other
termination topologies can also be used if desired.
Figure 13. Input Termination Example – 8V19N490 Reference Clock Input CLK/nCLK, Driven by a 3.3V LVPECL Driver
Table 3. VCO PLL 2nd Order Loop Filter Recommendation
VCXO used in the 1st PLL 122.88MHz 30.72MHz
PDF, Phase detector input frequency
with doubler on
245.76MHz 61.44MHz
Feedback divider 12 48
Suggest Charge pump current setting ~ 3.2ma (typical)
Suggest range setting
600ua to 6.4ma
~3.2ma (typical)
Suggest range setting
600ua to 6.4ma
Rs 100 Ohm
Suggest range
(100 to 1k Ohm)
400 Ohm
Suggest range
(100 to 1k Ohm)
Cs 100nF 100nF
Cp ~ 40pF ~ 40pF
Clock Input
CLK
nCLK
VCC=3.3V
R4
82.5
R2
82.5
R3
133
R1
133
VCC=3.3V
Zo = 50
Zo = 50
LVPECL Driv er
VCC=3.3V

R31UH0005EU0100 Rev.1.0 Page 12
Jun 3, 2021
8V19N49x Hardware Design Guide
Figure 14. Input Termination Example – 8V19N490 Reference Clock Input CLK/nCLK Driven by a 3.3V LVDS Driver
Figure 15. 8V19N490 Reference Clock Input CLK/nCLK AC Coupling Termination Example 1
Figure 16. 8V19N490 Reference Clock Input CLK/nCLK AC Coupling Termination Example 2
VCC=3.3V
Zo = 50
Zo = 50
LVDS Driv er
VCC=3.3V
R1
100
Clock Input
CLK
nCLK
VCC=3.3V
Clock Input
CLK
nCLK
R4
10K
R2
10K
R3
5.1K
R1
5.1K
VCC=3.3V
C1
C2
DifferentialSignal
Zo
Zo
R5
2 x Zo
VCC=3.3V
Clock Input
CLK
nCLK
C1
C2
DifferentialSignal
Zo
Zo
R5
Zo
R4 10K
R3 5.1K
R5
Zo
VCC=3.3V

R31UH0005EU0100 Rev.1.0 Page 13
Jun 3, 2021
8V19N49x Hardware Design Guide
4.2 Output Terminations for QCLK and QREF Drivers
The output stage of the 8V19N490 QCLK drivers can be configured to an LVPECL or LVDS style driver.
4.2.1 LVPECL Type Driver Terminations
When the output is configured to an LVPECL style driver, the driver is open-emitter type and requires a pull-down
resistor for the DC current path in order for the output to switch. A standard LVPECL driver termination is
displayed in Figure 17. There are many ways to terminate the LVEPCL driver. Figure 18 to Figure 21 show several
examples of LVPECL style driver termination.
Figure 17. Standard LVEPCL 750mV Driver Termination
Figure 18. LVPECL 750mV Termination Example 1
VCC=3.3V
High Input Impedance
CLK
nCLK
R4
50
R2
50
Zo = 50
Zo = 50
LVPECL Driv er
VCC=3.3V
VTT
VTT=VCC-2V=1.3
VCC=3.3V
R4
82.5
R2
82.5
R3
133
R1
133
VCC=3.3V
Zo = 50
Zo = 50
VCC=3.3V
LVPECL Driv er
High Input Impedance
CLK
nCLK

R31UH0005EU0100 Rev.1.0 Page 14
Jun 3, 2021
8V19N49x Hardware Design Guide
Figure 19. LVPECL 750mV Termination Example 2
Figure 20. LVPECL Driver DC Coupling Termination for the Receiver with built-in 100 ohm termination
Figure 21. LVPECL Driver AC Coupling Termination for the Receiver with Built-in Termination
VCC=3.3V
R4
50
R2
50
Zo = 50
Zo = 50
VCC=3.3V
LVPECL Driv er
R2
50
C1
0.1uF(optional)
High Input Impedance
CLK
nCLK
50 Ohm
50 Ohm
8V79S680
IN
nIN
VT
VCC=3.3V
Zo = 50
Zo = 50
VCC=3.3V
LVPECL Driv er
R2
120 to 240
R1
120 to 240
Zo = 50
Zo = 50
VCC=3.3V
LVPECL Driv er
R2
120 to 240
R1
120 to 240
50 Ohm
50 Ohm
8V79S680
IN
nIN
VT
VCC=3.3V
C1
C2
R4 10K
R3 5.1K
VCC=3.3V

R31UH0005EU0100 Rev.1.0 Page 15
Jun 3, 2021
8V19N49x Hardware Design Guide
4.2.2 LVDS Type Driver Terminations
An LVDS type driver does not require board-level pull-down resistors. A typical termination with DC coupling for an
LVDS type driver is displayed in Figure 22. A termination with AC coupling example is shown in Figure 23.
Figure 22. Typical LVDS Style Driver Termination
Figure 23. 8V19N490 LVDS Driver Driving a Receiver with Built-in Termination (e.g., 8V79S680/8V79S683
CLK/nCLK Input)
4.2.3 DC Coupling Interface for QREF Driver
The 8V19N49x QREF driver can be programmed to be an LVPECL or LVDS style driver. When programmed to an
LVPECL style driver, the output is an open-emitter type driver and can be terminated in a similar way as the
LVPECL termination (i.e., 50 Ohm to VTT or equivalence). When the QREF driver is programmed to an LVDS
style driver, the driver can be terminated as an LVDS driver (i.e., 100Ohm across). The output signals are not
quite same as standard LVPECL or LVDS. The amplitude can be programmed to different amplitude levels,
250mV, 500mV, 750mV, and 1000mV. The DC offset is about ~2V for both LVPECL and LVDS driver. 2V DC offset
is close the standard LVPECL signal; however, 8V19N490 LVDS DC offset is about 2V which is not standard. In
some applications, the receiver requires lower DC offset level with DC coupling interface. This section provides
several termination solution examples to shift down the DC offset to level using the DC coupling interface.
4.2.3.1 Receiver with High Input Impedance (No Built-in Termination)
Figure 24 shows an example of a DC coupling interface. In this example, the receiver is high-input impedance
without a built-in termination. The 8V19N490 driver is programmed to be an LVPECL style driver with 750mV
amplitude. The DC offset level is shifted down to approximately 1.2V and the amplitude is reduced to 400mV,
which is same signal of a standard LVDS level.
VCC=3.3V
Zo = 50
Zo = 50
LVDS Driv er
VCC=3.3V
R1
100
Dif f erential Receiv er
CLK
nCLK
50 Ohm
50 Ohm
8V79S680
IN
nIN
VT
VCC=3.3V
C1
C2
Zo
Zo
R4 10K
R3 5.1K
LVDS Driv er
VCC=3.3V
VCC=3.3V

R31UH0005EU0100 Rev.1.0 Page 16
Jun 3, 2021
8V19N49x Hardware Design Guide
Figure 24. LVPECL 750mV to LVDS Receiver with High Input Impedance
Figure 25. Simulation Waveforms at the Receiver Pins
3.3V LVPECL
R6
56
3.3V or 2.5V
3.3V
R2
133
R1
133
R4
27
3.3V*(R3+R5)/(R1+R3+R5) = 1.3V
3.3V
LVDS
+
-
Zo = 50
R5
56
R1//(R3+R5) = 50 ohm
Zo = 50
R3
27
OSCILLOSCOPE
Design file: UNNA M E D0.TLN Designer: M ing Lim
HyperLynx V7.7
Date: Thursday Sep. 11, 2008 Tim e: 11:50:39
Cursor 1, Voltage = 1.3916V, Tim e = 2.491ns
Cursor 2, Voltage = 855.4mV, Tim e = 6.982ns
Delta Voltage = 536.1m V, Delta Tim e = 4.491ns
S how Lates t W aveform = Y E S
400.0
600.0
800.0
1000.0
1200.0
1400.0
1600.0
1800.0
2000.0
2200.0
0.00 2.000 4.000 6.000 8.000
Tim e (ns)
V ol t ag e -mV -
V [RD(C0).1 (at pin)]
V [RS(B1).2 (at pin)]

R31UH0005EU0100 Rev.1.0 Page 17
Jun 3, 2021
8V19N49x Hardware Design Guide
4.2.3.2 Receiver with Built-in Termination
Figure 26 shows a receiver with built-in termination. The recommended termination for the non built-in is not
feasible. The DC coupling interface example to shift down the DC offset level is displayed in Figure 27.
Figure 26. Receiver with Built-in 100 ohm
Figure 27. DC Coupling Example for Receiver with Built-in Termination
Figure 28. Simulation Waveform at the Receiver
50 Ohm
R4
100
50 Ohm
8V19N490 LVEPCL
750mV
3.3V
R1 43
100
R2 43
R3
100
Receiver w ith
Built-in 100 Ohm
across

R31UH0005EU0100 Rev.1.0 Page 18
Jun 3, 2021
8V19N49x Hardware Design Guide
4.2.3.3 Receiver with Built-in Termination and DC Bias
This section provides a DC coupling termination interface example to shift down the DC offset level for 8V19N490
driver. In this example, the receiver has built-in termination and built-in DC bias of 0.5V. The DC offset is required
to shift close to this level.
Figure 29. Interface to Receiver with Built-in Termination and Built-in DC Bias
The value of the component is shown in Tabl e 4.
VDDO = 3.3V. The QREF output is set to LVPECL style driver and the amplitude is set to 750mV.
Figure 30. Simulation Waveform at the Receiver
Table 4. Component Values
Component References Component Values
R1 100 Ohm
R2 100 Ohm
R3 100 Ohm
R4 100 Ohm
R5 200 Ohm
R6 200 Ohm
50 Ohm
R1
R3
LV PECL
0.5V
R5
Rec e v ie r
w ith Built-in
termination
and Built-in
Bias
50 Ohm
R2
R4
50 Ohm
50 Ohm
IN
nIN
VT
R6
N490 QREF
VDDO

R31UH0005EU0100 Rev.1.0 Page 19
Jun 3, 2021
8V19N49x Hardware Design Guide
5. Schematic Diagrams
The following schematic diagrams are available from request:
▪ 8V19N490 EVB schematic
▪ 8V19N490 EVB board layout
6. Revision History
Revision Date Description
1.0 Jun 3, 2021 Initial release.

Corporate Headquarters
TOYOSU FORESIA, 3-2-24 Toyosu,
Koto-ku, Tokyo 135-0061, Japan
www.renesas.com
Contact Information
For further information on a product, technology, the most
up-to-date version of a document, or your nearest sales
office, please visit:
www.renesas.com/contact/
Trademarks
Renesas and the Renesas logo are trademarks of Renesas
Electronics Corporation. All trademarks and registered
trademarks are the property of their respective owners.
IMPORTANT NOTICE AND DISCLAIMER
RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL
SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING
REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND
OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED,
INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible
for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3)
ensuring your application meets applicable standards, and any other safety, security, or other requirements. These
resources are subject to change without notice. Renesas grants you permission to use these resources only for
development of an application that uses Renesas products. Other reproduction or use of these resources is strictly
prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property.
Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims,
damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject
to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources
expands or otherwise alters any applicable warranties or warranty disclaimers for these products.
(Rev.1.0 Mar 2020)
© 2021 Renesas Electronics Corporation. All rights reserved.