Rohm LAPIS Semiconductor ML7404 Series Guide

Dear customer
LAPIS Semiconductor Co., Ltd. ("LAPIS Semiconductor"), on the 1st day of October,
2020, implemented the incorporation-type company split (shinsetsu-bunkatsu) in which
LAPIS established a new company, LAPIS Technology Co., Ltd. (“LAPIS
Technology”) and LAPIS Technology succeeded LAPIS Semiconductor’s LSI business.
Therefore, all references to "LAPIS Semiconductor Co., Ltd.", "LAPIS Semiconductor"
and/or "LAPIS" in this document shall be replaced with "LAPIS Technology Co., Ltd."
Furthermore, there are no changes to the documents relating to our products other than
the company name, the company trademark, logo, etc.
Thank you for your understanding.
LAPIS Technology Co., Ltd.
October 1, 2020

ML7404 Family LSIs
Hardware Design Manual
Issue Date: Oct, 5th, 2018
FEXL7404DG-03

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Hardware Design Manual
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Notes
1) The information contained herein is subject to change without notice.
2) Although LAPIS Semiconductor is continuously working to improve product reliability and quality,
semiconductors can break down and malfunction due to various factors. Therefore, in order to prevent personal
injury or fire arising from failure, please take safety measures such as complying with the derating characteristics,
implementing redundant and fire prevention designs, and utilizing backups and fail-safe procedures. LAPIS
Semiconductor shall have no responsibility for any damages arising out of the use of our Products beyond the
rating specified by LAPIS Semiconductor.
3) Examples of application circuits, circuit constants and any other information contained herein are provided only to
illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account
when designing circuits for mass production.
4) The technical information specified herein is intended only to show the typical functions of the Products and
examples of application circuits for the Products. No license, expressly or implied, is granted hereby under any
intellectual property rights or other rights of LAPIS Semiconductor or any third party with respect to the
information contained in this document; therefore LAPIS Semiconductor shall have no responsibility whatsoever
for any dispute, concerning such rights owned by third parties, arising out of the use of such technical information.
5) The Products are intended for use in general electronic equipment (i.e. AV/OA devices, communication, consumer
systems, gaming/entertainment sets) as well as the applications indicated in this document.
6) The Products specified in this document are not designed to be radiation tolerant.
7) For use of our Products in applications requiring a high degree of reliability (as exemplified below), please
contact and consult with a LAPIS Semiconductor representative: transportation equipment (i.e. cars, ships, trains),
primary communication equipment, traffic lights, fire/crime prevention, safety equipment, medical systems, servers,
solar cells, and power transmission systems.
8) Do not use our Products in applications requiring extremely high reliability, such as aerospace equipment, nuclear
power control systems, and submarine repeaters.
9) LAPIS Semiconductor shall have no responsibility for any damages or injury arising from non-compliance with the
recommended usage conditions and specifications contained herein.
10) LAPIS Semiconductor has used reasonable care to ensure the accuracy of the information contained in this
document. However, LAPIS Semiconductor does not warrant that such information is error-free and LAPIS
Semiconductor shall have no responsibility for any damages arising from any inaccuracy or misprint of such
information.
11) Please use the Products in accordance with any applicable environmental laws and regulations, such as the RoHS
Directive. For more details, including RoHS compatibility, please contact a ROHM sales office. LAPIS
Semiconductor shall have no responsibility for any damages or losses resulting non-compliance
with any applicable laws or regulations.
12) When providing our Products and technologies contained in this document to other countries, you must abide by
the procedures and provisions stipulated in all applicable export laws and regulations, including without limitation
the US Export Administration Regulations and the Foreign Exchange and Foreign Trade Act.
13) This document, in part or in whole, may not be reprinted or reproduced without prior consent of LAPIS
Semiconductor.
Copyright 2018 LAPIS Semiconductor Co., Ltd.
2-4-8 Shinyokohama, Kouhoku-ku,
Yokohama 222-8575, Japan
http://www.lapis-semi.com/en/

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Introduction
This hardware design manual contains hardware information that should be referenced when
designing ML7404 family devices (Hereafter ML7404). And also contains the measurement
conditions and example of measurement results of RF characteristics.
Target product：
ML7404
The following related manual is available and should be referenced as needed
ML7404 data sheet
All other company and products names are the trademarks or registered trademarks of the respective
companies.

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Notation
Classification Notation Description
Numeric value 0xnn Represents a hexadecimal number.
0bnnnn Represents a binary number.
Address 0xnnnn_nnnn Represents a hexadecimal number. (indicates 0xnnnnnnnn)
Unit word, W 1 word = 32 bits
byte, B 1 byte = 8 bits
Mega, M 106
Kilo, K (uppercase) 210=1024
Kilo, k (lowercase) 103=1000
Milli, m 10-3
Micro, µ10-6
Nano, n 10-9
Second, s (lowercase) Second
Terminology "H" level Signal level on the high voltage side; indicates the voltage level of
VIH and VOH as defined in electrical characteristics.
"L" level Signal level on the low voltage side; indicates the voltage level of
VIL and VOL as defined in electrical characteristics.
Register description
Read/write attribute: R indicates read-enabled; W indicates write-enabled.
MSB: Most significant bit in an 8-bit register (memory)
LSB: Least significant bit in an 8-bit register (memory)

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Table of Contents
INTRODUCTION.............................................................................................................................................II
NOTATION ..................................................................................................................................................... III
TABLE OF CONTENTS ................................................................................................................................ IV
1. PLACING DECOUPLING CAPACITORS .............................................................................................. 1
2. CLOCK INPUT......................................................................................................................................... 3
2.1. CRYSTAL OSCILLATOR CIRCUIT ........................................................................................................... 3
2.1.1. Circuit component values for crystal oscillator circuit ................................................................ 3
2.1.2. Notes on the crystal oscillator circuit configuration .................................................................... 4
2.2. TCXO CIRCUIT (ML7404)................................................................................................................... 5
2.3. FREQUENCY TOLERANCE OF INPUT CLOCK ........................................................................................ 5
3. PLL LOOP FILTER .................................................................................................................................. 7
4. VCO ........................................................................................................................................................... 8
4.1. ADJUSTING COMPONENT VALUES FOR VCO TANK .............................................................................. 9
4.2. NOTE ON THE VCO TANK CIRCUIT .................................................................................................... 10
5. RF MATCHING COMPONENT VALUES .............................................................................................11
5.1. ANTENNA TX AND RX DIRECT TIE MATCHING CIRCUIT....................................................................11
6. NOTES ON SELECTING EXTERNAL PARTS (RECOMMENDATIONS)........................................ 12
7. NOTES ON BOARD ARTWORKS (RECOMMENDATIONS)............................................................. 12
7.1. GND ................................................................................................................................................. 12
8. STANDARD ............................................................................................................................................ 13
8.1. ARIB STD-T108 .............................................................................................................................. 13
9. CIRCUIT FOR RF CHARACTERISTIC MEASUREMENT (920MHZ) ................................................. 14
10. BILL OF MATERIALS ....................................................................................................................... 15
10.1. 494.998MHZ................................................................................................................................. 15
10.2. 920MHZ........................................................................................................................................ 17
10.3. APPLICATION CIRCUIT ...........................................
エラー!ブックマークが定義されていません。
REVISION HISTORY .................................................................................................................................... 20

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1. Placing decoupling capacitors
Place decoupling capacitors between each power pins and GND as shown in Figure 1.1.
Figure 1.1 Power Supply Block Diagram
*[1] The supply voltage for the PA_OUT pin (#20) should be provided the DC bias through the inductor (L3)
REG_PA(#21)
VDD_PA(#22)
VDD_REG(#1)
Including backside GND
GND
REG_OUT(#3)
PA_OUT(#20)
VBG(#2)
PA
VDD
REG_CORE(#4)
VB_EXT(#31)
VDD_VCO(#32)
VDD_CP(#27)
VDD_RF(#25)
Each decoupling capacitors as close to an LSI pin as possible.
PA regulator
VDDIO(#9)
1.5V regulator
Logic circuit
0.1µF
0.1µF
1000pF
1000pF
1000pF
0.1µF
L3*[1]
1000pF
0.1µF
1μF
0.01uF
1µF
0.1uF

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Notes the following when placing decoupling capacitors:
1. The VDD and GND traces should be wider than other signal line traces to reduce the resister element.
2. Decoupling capacitor should be placed as close to an LSI pin as possible.
3. The smaller capacitor should be closer to an LSI pin than other capacitors.
4. VDDIO (#9), VDD_PA (#22), VDD_REG (#1) pins connected to the VDD share the trace.
5. A 1 µF decoupling capacitor should be placed to the REG_CORE (#4) pin to stabilize 1.5V regulator.
6. The VBG (#2) pin is a reference voltage output pin of band-gap reference circuit. Placing a 0.1μF
multilayer ceramic capacitor to the VBG (#2) pin to reduce the noise from the band-gap reference
circuit.

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2. Clock Input
2.1.Crystal Oscillator circuit
Figure 2.1 shows a configuration example of the crystal oscillator circuit. Capacitors should be connected to XIN
(#5) and XOUT (#6) pins to stabilize 36MHz crystal oscillator circuit. To determine the component values, the
oscillator circuit evaluation on your designing board is required, since the stray capacitor of the board will be
influenced.
Amplitude level, oscillation margin, frequency accuracy and oscillator circuit start-up time should be considered
and evaluated.
Figure 2.1.1 Crystal Oscillator circuit configurations
2.1.1. Circuit component values for crystal oscillator circuit
It is recommended to ask your oscillator manufacturer to evaluate the matching component values on the
assembled board. The following tables show the matching component values with LAPIS Semiconductor RF
board as reference.
Table 2.1.1 Representative matching component values
ManufacturerOscillator Type Frequency
(MHz)
Equivalent
series resister
Max(Ω)
Load
capacitor
(pF)
Component
Values
Operating Condition
(+/-10ppm)
C4
(pF)
C5
(pF)
R11
(Ω)
Power supply
voltage range
VDDIO(V)
Temperature range
( ℃)
NDK NX2016SA
(EXS00A-CS07050) 36 T.B.D. 6 T.B.D. T.B.D. T.B.D. 1.8 to 3.6 T.B.D.
EPSON T.B.D. 36 T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. 1.8 to 3.6 T.B.D.
YOKETAN T.B.D. 36 T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. 1.8 to 3.6 T.B.D.
[Note] These component values appropriate for use on the LAPIS Semiconductor’s RF board. It is not guaranteed to
obtain same result on your specific board.
[Note] The frequency tolerance of reference clock must be within +/-2.5ppm in order to correspond to IEEE802.15.4k.
TCXO should be used.
XIN(#5)
C4
X’tal
XOUT(#6)
C5
R0_5

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2.1.2. Notes on the crystal oscillator circuit configuration
Note the following when designing the crystal oscillator circuit.
1. The capacitors value of C4 and C5 depends on the crystal oscillator specification.
2. C1 and C2 should be placed as close as possible to the XIN (#5) and the XOUT (#6) pins to suppress
parasitic LCR and stabilize the oscillator.
3. Do not place the crystal oscillator circuit across other signal lines.
4. Do not trace signal lines where large current flow around the crystal oscillator circuit.
5. For the oscillator circuit capacitors, make sure the potential of the ground points is always equal to that
of the GND. Do not connect the capacitors to GNDs where large current flow.
6. Do not take oscillation signals from the oscillator circuit.

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2.2.TCXO circuit (ML7404)
Please use a TCXO that satisfy the following specification.
Output load: 10kΩ//10pF
Output level: 0.8Vpp to 1.5Vpp
Frequency accuracy: below ±10ppm
The ML7404 has integrated bias circuit and the DC bias is applied to the TCXO (#6) pin. A 0.1uF capacitor
should be placed on the TCXO line as following.
In ML7404, #5 pin is N.C. pin, then it should be open.
Figure 2.2.1 External oscillator circuit (TCXO) configurations
2.3.Frequency tolerance of Input Clock
Table 2.1.1Relationship between Use case and frequency tolerance of reference clock
Use case Unit
1 2 3 4 5 6 7
Sigfox Yes Yes Yes No Yes No No
IEEE802.15.4k Yes Yes No Yes No Yes No
IEEE802.15.4g
(ARIB STD T-108) Yes No Yes Yes No No Yes
Recommended clock
source
Frequency tolerance[1]
(36MHz)
TCXO
±3
TCXO
±3
TCXO/XO
±20
TCXO
±3
TCXO/XO
±20
TCXO
±3
TCXO/XO
±20
ppm
[1] Frequency tolerance is indicated by the sum of the following 3 items.
A. Initial frequency tolerance
B. Frequency/Temperature characteristics
C. Long-term Frequency stability
It is possible to compensate the item A(Initial frequency tolerance) by adjusting the frequency of transmission /
reception in ML7404. When adjusting the initial frequency tolerance for each set, the frequency tolerance
required for reference clock source is only the sum of B and C.
TCXO
36MHz 0.1uF TCXO(#6)
Bias
N.C.(#5)

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●Example of an adjustment flow for initial frequency tolerance
The example of an adjustment flow in the case of measuring the frequency of a transmitted signal and
compensating initial frequency tolerance is shown below. In addition, for details, refer to the “LSI Adjustment
items and Adjustment method” - “TRX FrequencyAdjustment” of data sheet (FEDL7404-0X).
START
END
TX_ON issue
[RF_STATUS: B0 0x0B]
Confirm TX frequency error
(using spectrum analyzer)
Adjust TRX frequency
FREQ_ADJ_SIGN([FREQ_ADJ_H: B1 0x42(7)])
FREQ_ADJ [9:0]([FREQ_ADJ_H/L: B1 0x42(1-0)/0x43])
Set TX frequency
[TX_FREQ_I/FH/FM/FL: B1 0x1B/1C/1D/1F]

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3. PLL loop filter
Figure 3.1 shows a configuration example of the PLL loop filter circuit . C3 and R3 values depend on the data
rate to satisfy phase noise feature. The recommend values are listed in Table 3.1.
It is recommended to select the components with flat temperature characteristics and temperature coefficient is
managed. Capacitors, do not select high dielectric type and semiconductor type, so there is low accuracy and
non-linear temperature characteristics.
In order to prevent noise, the loop filter components (C3, R3 and C2) should be placed as close to the LP (#26)
pin as possible, recommends within 5 mm. Do not trace signal lines that become a noise source like a reference
clock line, around the loop filter.
Figure 3.1 PLL loop filter circuit configurations
Table 3.1 Representative component values for the loop filter
[Note] These component values appropriate for use on the LAPIS Semiconductor’s RF board. It is not
guaranteed to obtain same result on your specific board.
315~960MHz
C2 68pF
C3 1000pF
R3 6.2kΩ
R101 N.M.
LP(#26)
C2
R3
C3
R101

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4. VCO
Figure 4.1 shows a configuration example of the VCO tank circuit. VCO oscillator frequency calculated as
follows:
LC
F
π
2
1
=
The L in the above equation will be the sum of the inductor L1, the line inductance of the PCB and the internal
inductance of the ML7404. And the C will be the sum of the capacitor C1, the line capacitor of the PCB and the
internal capacitor (including calibration capacitor) of the ML7404. Table 4.1 shows the typical value of internal
capacitor.
Figure 4.1 VCO tank circuit configurations
Table 4.1: Internal capacitor value
VCO_CAL[6:0](B0, 0x6E) Internal capacitor value[pF]
0x00 2.94pF
0x40 2.46pF
0x7F 1.97pF
conditions：LP(#26) pin voltage（VCO tuning voltage）=0.75V
IND1(#28)
Variable capacitor
Amplifier
C1
L1
IND2(#30)
Variable capacitor
for calibration

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4.1.Adjusting component values for VCO tank
Adjustment procedure of the VCO tank componentｓis as below:
1. Execute the VCO calibration with the following condition.
Set the frequency to the center of usingfrequency range.
In the idle state with the room temperature.
2. Adjust the L1 and C1 values so that the calibration value obtained by [VCO_CAL] register (B0 0x6E)
becomes close to “64”(Decimal).
Reducing one or both L1 and C1 values if decreasing the VCO_CAL value.
Increasing one or both L1 and C1 values if increasing the VCO_CAL value.
[Note] In order to lock the PLL, the VCO_CAL value is required to be in the range from 1 to 126 (decimal) under
all conditions.
The frequency range that PLL can lock, VCO phase noise and the temperature feature depend on the L1, C1
values. It is recommended to evaluate these characteristics when L1 and C1 values is fixed.
Table 4.1.1 Representative component values for operating frequency
Target RF frequency PLL（VCO）divider
setting
VCO
oscillation
frequency
VCO tank value
L1 C1
ML7404
426MHz
divide by 2
852MHz
4.7nH
3.9pF
494.998MHz divide by 2 980MHz 3.6nH 3.3pF
868MHz
no divide
868MHz
4.7nH
3.9pF
920MHz no divide 920MHz 3.9nH 3.3pF
[Note] These component values appropriate for use on the LAPIS Semiconductor’s RF board. It is not guaranteed
to obtain same result on your specific board.

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4.2.Note on the VCO tank circuit
Note the following when designing the VCO tank cercuit.
1. In order to stable VCO oscillation, the VCO tank components (L1 and C1) should be placed as close to the
IND1 (#28) and IND2 (#30) pins as possible(within 2 mm). Since the line inductance and capacitance of
PCB will effect to the oscillation frequency. Inductor L1 Should be placed closer to IND1(#28) pin or
IND2(#30) pin of ML7404 than capacitor C1. Trace length to the L1 from IND1 (#28) pin and IND2(#30)
pin of ML7404 should be same length.
2. ML7404 maximum output power is more than50mW. As shown in the Figure 4.2.1, high output will flow
on the transmission path from PA_OUT (#20) pin. If this output affects on VCO tank circuit, it may cause
the PLL unlock. So be careful the followings:
2.1. As shown in the Figure 4.2.2, VCO tank inductor L1 and PA choke inductor L3 should be placed so that
their positional relationship becomes the 90 degrees to avoid their coupling.
2.2. L1 and L3 should be placed close to their connect pins of ML7404. They should not be placed close to
each other within 2 mm. Spacing between each inductors is recommended more than 8mm.
2.3. RF maching circuit should not be close to the L1. recommends more than 6mm.
2.4. PCB traces to the L1, C1 from VCO pins(IND1/IND2) should be symmetrical.
2.5. L1 should be placed nearer to the VCO pins(IND1/IND2)than C1.
2.6. Avoid signal line or Vdd line underneath layers of L1,C1.
Figure 4.2.1 Notes on the VCO tank circuit
Figure 4.2.2 Placement of L1 and L3
L1 and L3 should be placed so that their positional
relationship with the 90 degrees in order to avoid their
coupling.
IND1(#28)
REG_PA (#21)
PA_OUT
PA
Regulator
VC
Matching
Network
PA
L
3
～50mW
Interference from Tx signal
IND2 (#30)
L1
C1
L3
L1

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Thick line is Zo=50 ohm
ANTENNA
PA_OUT(#20)
LNA_P(#24)
REG_PA(#21)
Inductor
(L3)
LPF, suppress harmonics
5. RF matching component values
Table 5.1 shows the measured impedance of the PA_OUT (#20) pin and the LNA_P (#24) pin at operationg
frequency.These impedances are presented as a reference.
Table 5.1 Measured RF impedance
R + jX [Ω]
Tx （PA_OUT(#20) pin）
Rx （LNA_P(#24) pin）
Target Measurement
frequency
13dBm 10dBm 0dBm
ML7404 426MHz
6.5 + j9.8 4.9 + j10.1 2.0 + j11.0 11.5 - j204.3
868MHz
43.6 - j7.6
63.2 - j3.4
204.3 + j92.1
10.2 - j132.2
920MHz 48.2 - j8.8 73.0 – j14.1 259.3 – j130.3 10.6 - j130.3
[Note] These component values appropriate for use on the LAPIS Semiconductor’s RF board. It is not
guaranteed to obtain same result on your specific board.
5.1.ANTENNATx and Rx direct tie matching circuit
Figure 5.1.1 shows the Antenna maching circuit configuraltions. The REG_PA (#21) pin provides the DC bias to
the PA_OUT(#20) pin. This DC bias should be provided through the inductor (L3). Chebyshev lowpass filter is
consist of components L5~L8 and LPF1, C47~C50,to suppress harmonics.
Figure 5.1.1 Transmission matching circuit configurations

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6. Notes on selecting external parts (recommendations)
•Anntenna
It is recommended to use an antenna with the specifications shown in Table 6.1.
Select an antenna with the best directive characteristics for your specific operating, environmental and
installation condition. Since antennas are affected by installation conditions such as GND, external factors should
always be taken into account.
It is recommended to ask the manufacturer of the selected antenna for installation details in relation to various
factors, including the shape and stray capacitance of the board to be used.
Table 6.1 Antenna
Frequency band 315~450MHz / 470~510MHz /
868MHz / 920MHz band
VSWR 2.0MAX
Nominal Impedance 50Ω
•Inductors
Use inductors with high Q. It is recommended to use LQW15AN series (manufactured by Murata Manufacturing
Co. Ltd) or equivalent.
•Capacitors
Use capacitors with a CH (temperature compensating) or a B (high dielectric constant type) of temperature
characteristics. It is recommended to use capacitors of 0 ± 60 ppm/°C or less for areas that affect high frequency
characteristics. To realize lower power system it recommended to use low leak components because ML7404
has very low current consumption in sleep mode.
•Resistors
Use resistors for which the resistance variation are small when the temperature changes.
7. Notes on board artworks (recommendations)
7.1.GND
About IC’s back side GND pad, the number of through-hole to board GND plane should be placed more than 12.
And drawing GND line width should be more wide as much as possible. Almost of L2 layer should be GND plane
for double-layered board.

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8. Standard
8.1.ARIB STD-T108
In IEEE802.15.4k, in order to correspond to ARIB STD-T108, ML7404 should be used on condition of the
following.
•TX power: 10dBm
•Unit channel: 5 bundled unit channel *[2]
•Frequency range: 921MHz~924.6MHz*[3]
However, it is possible to deal with ARIB STD-T108 by changing a data rate to reduce the unit channel to be used.
ML7404 passed the electric wave attestation examination (TELEC-T245) corresponding to ARIB STD-T108 under the
following conditions.
Unit channel Modulation Data(chip) Rate Standard TX Power(Peak Power)
1 2GFSK 50kbps IEEE802.15.4g 13dBm
2 bundled 2GFSK 100kbps IEEE802.15.4g 13dBm
1 BPSK 100bps Sigfox 10dBm
2 bundled BPSK 40kcps Original 10dBm
2 bundled BPSK 50kcps Original 10dBm
5 bundled BPSK 200kcps IEEE802.15.4k 10dBm
*[2] a unit channel is 200kHz.
*[3] In case of using IEEE802.15.4k, in order to satisfy the spurious emission, ML7404 should be used 5 bundled unit
channel (Figure. 8.1). Therefore, it is necessary to perform CCA(Clear Channel Assessment) by 5 bundled unit
channel. But, actual transmitting occupied bandwidth (OBW) is 2 bundled unit channel (400kHz) or less. As a
result, channel separation can be made into 2 bundled unit channel (400kHz) (Figure 8.2).
Figure 8.1 Relationship between spurious emission and unit channel
Figure 8.2 Example of channel arrangement and CCA execution(3 times time sharing)
Input frequency of CW when CCA test.
Bandwidth for CCA (400kHz)
-800kHz -600kHz -400kHz -200kHz fc 200kHz 400kHz 600kHz 800kHz
IEEE802.15.4k OBW
(400kHz or less)
Bandwidth of 5 bundled
unit channel (1MHz)
Adjacent Channel
Spurious emission
(<-36dBm/100kHz)
Adjacent Channel
Spurious emission
(<-36dBm/100kHz)
-400kHz -200kHz fc 200kHz 400kHz
2 bundled
Unit channel
Lower side adjacent channel
(2 bundled Unit channel) Upper side adjacent channel
(2 bundled Unit channel)
Input frequency of CW when CCA test.

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9. Circuit for RF characteristic measurement (920MHz)
[Note] In case of using TCXO, XIN(#5) pin should be “open”.
C41