Rohm BD71805MWV Guide

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BD71805MWV
(Power Management IC designed for
“Freescale i.MX 6 SoloLite Processors”)
Platfrom Design Guide
November 2015
ROHM CONFIDENTIAL
Revision 1.10
Platform Design Guide
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Rev.1.10
Revision History
Revision
Number
Description
Revision
Date
0.70
Initial release
June
2015
0.90
Chapter 4
・Figure 4-1-1-1, 4-1-1-2
Added MSSEL pin in the figures.
Chapter 1
・Table 1-2
Updated document name of datasheet.
August
2015
1.00
Chapter 4
・Table 4-5-3
Updated descriptions for termination setting when it is not used.
November
2015
1.10
Chapter 2
・Fixed descriptions about default OFF rail in each Master/Slave mode.
November
2015
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Contents
Revision History.................................................................................................2
1 Introduction.....................................................................................................4
1.1 Terminology .......................................................................................................................4
1.2 Reference Documents.......................................................................................................4
2 System Features.............................................................................................5
3 General Design Considerations......................................................................7
3.1 Package Dimension of BD71805MWV ..............................................................................7
3.2 Pin Configuration ...............................................................................................................8
3.3 General Stack-up Recommendations................................................................................9
3.4 4-layer Board Stack-up......................................................................................................9
3.5 Via Guidelines....................................................................................................................9
3.6 BD71805MWV Breakout Example...................................................................................11
4 Platform Power Delivery Guidelines..............................................................15
4.1 Platform Power Delivery ..................................................................................................15
4.2 General Layout Guideline................................................................................................17
4.2.1 Overall component Placement Example .................................................................................................................17
4.2.2 Large Current Loop...................................................................................................................................................18
4.2.3 Power GND.................................................................................................................................................................19
4.2.4 VIN (Power supply for BD71805MWV analog circuit).............................................................................................19
4.2.5 Other Signal Pattern Precautions ............................................................................................................................19
4.2.6 Feedback sense line..................................................................................................................................................19
4.3 Switching regulators.........................................................................................................20
4.3.1 BUCK1........................................................................................................................................................................20
4.3.2 BUCK2........................................................................................................................................................................21
4.3.3 BUCK3........................................................................................................................................................................23
4.3.4 BUCK4........................................................................................................................................................................24
4.4 Linear VR.........................................................................................................................26
4.4.1 LDO1-3........................................................................................................................................................................26
4.4.2 VODVREF...................................................................................................................................................................27
4.4.3 SNVSCAP / VOSNVS .................................................................................................................................................28
4.5 Interfaces.........................................................................................................................29
4.5.1 I2C...............................................................................................................................................................................29
4.5.2 GPO ............................................................................................................................................................................29
4.5.3 Charger, Coulomb counter, OVP..............................................................................................................................29
4.5.4 RTC.............................................................................................................................................................................30
4.5.5 System Control signals.............................................................................................................................................30
4.5.6 MISC ...........................................................................................................................................................................30
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1 Introduction
BD71805MWV is a Power Management Integrated Circuit (PMIC) for battery-powered portable
devices. It integrates 4 Bucks, 3 LDOs, 2A single-cell linear charger, OVP, Coulomb counter, RTC, 32
kHz crystal circuitry and 3 GPOs. And it is designed to support the specific power requirement of
Freescale i.MX 6 SoloLite platforms with minimum cost requirement.
The “BD71805MWV Platform Design Guide”provides design guideline which is recommended to PCB
layer stack up, the components placement and the PCB routing. To reduce the risk that comes from
PCB layout or parts placement, the guideline is strongly recommended to be adapted to the PCB
design.
1.1 Terminology
Table 1-1-1. Acronyms, Conventions and Terminology
Term
Definition
BOM
Bill Of Materials
FET
Field Effect Transistor
I2C
Inter-Integrated Circuit
IRQ
Interrupt Request
LDO
Low Drop-Out regulator
OCP
Over Current Protection
OVP
Over Voltage Protection
PFM
Pulse-Frequency Modulation
PWM
Pulse-Width Modulation
RTC
Real-Time Clock
SoC
System-On-a-Chip
UVLO
Under Voltage-LockOut
DVS
Dynamic Voltage Scaling
1.2 Reference Documents
Table 1-1-2. Reference Documents
Document
BD71805MWV(EN)_Rev002, Aug, 2015
BD71805MWV_Reference_Schematic_REV1P00, Jun, 2015
BD71805MWV_Reference_Layout_REV1P00, Jun, 2015
BD71805MWV_REFERENCE_BOM_REV1P00, Jun, 2015
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2 System Features
BD71805MWV is used to supply the required power to the SoC and peripheral devices. Once powered
up, it can be controlled by I2C bus to determine internal settings. The following explains the features
that are incorporated in the IC.
Control mode
BD71805MWV can select control mode either by SoC or by external control input such like
button switch by MSSEL pin setting.
- MSSEL=H (Slave mode): PWRON signal is controlled by SoC.
- MSSEL=L (Master mode): PWRON signal is controlled by external control input.
Voltage Rails
■4 Buck regulators
(Slave mode)
BUCK1: Initial 1.375V, 0.800V –2.000V / 25mV step DVS, IOMAX = 2A
BUCK2: Initial 1.375V, 0.800V –2.000V / 25mV step DVS, IOMAX = 1A
BUCK3: 3.150V, 2.600V –3.350V / 50mV step programmable, IOMAX = 1A
BUCK4: 1.200V, 1.000V –2.700V / 50mV step programmable, IOMAX = 1A
(Master mode)
BUCK1: Initial 1.425V, 0.800V –2.000V / 25mV step DVS, IOMAX = 2A
BUCK2: Initial 1.200V, 0.800V –2.000V / 25mV step DVS, IOMAX = 1A
BUCK3: 3.300V, 2.600V –3.350V / 50mV step programmable, IOMAX = 1A
BUCK4: 1.800V, 1.000V –2.700V / 50mV step programmable, IOMAX = 1A
■3 LDO regulators (General purpose)
(Slave mode)
LDO1: 2.5V, 0.8V –3.3V / 50mV step programmable, IOMAX = 300mA
LDO2: 1.8V, 0.8V –3.3V / 50mV step programmable, IOMAX = 300mA
LDO3: 1.2V, 0.8V –3.3V / 50mV step programmable, IOMAX = 300mA
(Master mode)
LDO1: 1.2V, 0.8V –3.3V / 50mV step programmable, IOMAX = 300mA
LDO2: 3.3V (default OFF), 0.8V –3.3V / 50mV step programmable, IOMAX = 300mA
LDO3: 3.3V (default OFF), 0.8V –3.3V / 50mV step programmable, IOMAX = 300mA
■LDO for DDR Reference voltage
(Slave mode)
DVREF: DVREFIN/2, IOMAX = 10mA
(Master mode)
DVREF: DVREFIN/2 (default OFF), IOMAX = 10mA
■LDO for Secure Non-Volatile Storage (SNVS)
(Slave mode)
SNVSCAP: 3.0V, IOMAX = 25mA
(Master mode)
VOSNVS: 3.0V, IOMAX = 25mA
Single-cell Linear LIB Charger
Selectable Charging Voltage: 3.72V –4.34V
Programmable Charge Current: 100mA –2000mA
DCIN Over Voltage Protection
Battery Over Voltage Protection
Support Battery Supplement Mode
Battery Short Circuit Detection
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Voltage Measurement for Thermistor
CHGREF: Bias Voltage Output for External Thermistor
Embedded Coulomb Counter for Battery Fuel Gauging
15-bit ΔΣ-ADC with External Current Sense Resistor (10 mΩ, ±1%)
1sec cycle, 28-bitAccumulation
Coulomb Count while Charging/Discharging
Battery Monitoring and Alarm Output
Under VoltageAlarm while Discharging
Over Discharge Current Alarm
Over/Under Temperature Alarm
Programmable Thresholds and Time Durations
Automatic Low Voltage Mode (Battery Protection)
- 3.5V Detection:
Interrupt to Processor toAsk User Plug-in
- 3.3V Detection:
Interrupt to Processor to Indicate Battery Critically
Real Time Clock with 32.768kHz Crystal Oscillator
CLK32KOUT: 32.768kHz Clock Output (Open Drain or CMOS Output Selectable)
3 GPOs
GPO1-3 (Open Drain or CMOS Output Selectable)
Power Control I/O
PWRON: Power ON/OFF Control Input
STANDBY: Standby Input for Switching ON / STANDBY Mode
RESETINB: Reset Input to Reset Hung PMIC
POR: Power ON Reset Output
Serial Interface
I2C interface provides access to configuration registers.
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3 General Design Considerations
This chapter provides general PCB design guidelines such as BD71805MWV general parts placement.
3.1 Package Dimension of BD71805MWV
Figure 3-1-1 shows the package dimension of BD71805MWV.
Figure 3-1-1 BD71805MWV Package Dimension
BD71805
Lot Number
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3.2 Pin Configuration
Figure 3-2-1 shows the BD71805MWV pin configuration with which signals from respective blocks are
effectively routed out from PMIC to SoC, SDRAM, and other platform components.
Figure 3-2-1 Pin Configuration
35 36 37 38 39 40 41 42 43 44 45 46 47 48
14 13 12 11 10
9 8 7 6 5 4 3 2 1
30
29
28
27
26
25
24
23
22
21
20
19
18
17
51
52
53
54
55
56
58
59
57
60
61
62
63
64
16 15
32
31
33 34
49
50
LX1 PGND1 FB1 VOSNVS GND CLK32KOUT
CHGLED
SDA SCL DVDD
XOUT32K
STANDBY
FB2
PGND2
RESETINB
GND
LX2 XIN32K
PVIN2
MSSEL
GPO1
GPO2
VODVREF
DVREFIN
CPOUT
FB4
PGND4
LX4
GPO3
PVIN1
VIN
VINL2
VO2
VO1
VINL1
INTB
POR
GNDT1
FB3
PGND3
PGND3
LX3
LX3
VO3
PVIN3 PVIN3
NC
BATTM
BATTP
CHGREF
TS
VBAT VBAT
VSYS VSYS
DCIN DCIN
PVIN4
CHGGND
PVIN1
SNVSCAP PGND1 LX1
PWRON
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3.3 General Stack-up Recommendations
Type-3 and 6 layers PCB technology is used for BD71805MWV. The following general stack-up is
strongly recommended to be applied to all the routings on the PCB.
Surface plane layer are recommended to be 1.9 Mils thick copper.
Internal plane layers (2nd and 5th layers) are recommended to be 1.3 Mils thick copper.
Internal plane layers (3rd and 4th layers) are recommended to be 0.65 Mils thick copper.
It is recommended that I2C signals have reference to solid planes over the length of their routing
and do not cross plane splits. Ground is preferred as reference.
PCB should be filled with as much ground or other power rails as possible with copper. There
should not be any large areas with no metal in the board. Heat dissipation gets improved with
larger metal areas. Large metal area also reduces stray resistance and inductance.
3.4 4-layer Board Stack-up
BD71805MWV Boards uses Type 3 PCB technology. Figure 3-3-1 shows 6-Layer PCB stack-up
Figure 3-3-1 6-Layer PCB Stack-up
3.5 Via Guidelines
This section explains proper via-drill, pad, and anti-pad size.
Note: Improper drill, pad, and anti-pad size may cause some trouble on the PCB cost, reliability,
manufacturability, and electrical characteristics.
Type-3 PCB technology employs plated through-hole (PTH) vias for breakout routing. The dimension
of PTH vias may vary as necessary. Table 3-5-1 shows the recommended via dimension used for the
breakout areas of BD71805MWV. Figure 3-5-1 shows about the dimensions of via.
L1: Signals including LX, PVIN and PGND lines of DCDC
L2: GND plane
L3: Power plane (VSYS)
L4: Power plane
L5: GND plane
L6: Signals
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Table 3-5-1: Platform via Examples
Via type
Hole size
Pad size
Anti-Pad size
Plated through-hole (PTH)
12 mils
24 mils
32 mils
Figure 3-5-1: Dimension of via
Hole size
Pad size
Anti-Pad size
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3.6 BD71805MWV Breakout Example
For the breakout routing on Layer 1(Top layer) thru 6 (Bottom layer), refer to Figure 3-6-1 thru Figure
3-6-6.
Figure 3-6-1 BD71805MWV Reference Board Breakout and Parts Placement (Top Layer)
BUCK4
BUCK3
BUCK1
BUCK2
LDO1-3
VODVREF
SNVSCAP
/VOSNVS
Crystal
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Figure 3-6-2 BD71805MWV Reference Board Breakout (Layer 2)
Figure 3-6-3 BD71805MWV Reference Board Breakout (Layer 3)
GND
VSYS
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Figure 3-6-4 BD71805MWV Reference Board Breakout (Layer 4)
Figure 3-6-5 BD71805MWV Reference Board Breakout (Layer 5)
GND
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Figure 3-6-6 BD71805MWV Reference Board Breakout (Layer 6)
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4 Platform Power Delivery Guidelines
BD71805MWV is a PMIC (Power Management Integrated Circuit) that incorporates single-channel
switching regulators (Buck), Linear VRs (LDO), RTC, Single-cell Linear LIB charger and Coulomb
counter. It is essential to follow the guidelines for stable power delivery to the SoC and the system.
4.1 Platform Power Delivery
Figure 4-1-1-1 and Figure 4-1-1-2 show the voltages BD71805MWV provides to the SoC and the other
devices in the system and Table 4-1-1-1 and Table 4-1-1-2 provide the maximum current guideline for
respective voltage rail.
Table 4-1-1-1 DC-to-DC converters and Linear VRs Maximum Design Power (Slave mode)
Voltage Rail
Type
Input Voltage
Default
Output Voltage
[V]
Max
Current
[mA]
BUCK1
Buck [DVS]
PVIN1
1.375
2000
BUCK2
Buck [DVS]
PVIN2
1.375
1000
BUCK3
Buck
PVIN3
3.150
1000
BUCK4
Buck
PVIN4
1.200
1000
LDO1
LDO
VINL1
2.500
300
LDO2
LDO
VINL2
1.800
300
LDO3
LDO
VINL2
1.200
300
VODVREF
LDO
VIN
0.5*DVREFIN
10
VOSNVS
LDO
VIN
3.000
25
Table 4-1-1-2 DC-to-DC converters and Linear VRs Maximum Design Power (Master mode)
Voltage Rail
Type
Input Voltage
Default
Output Voltage
[V]
Max
Current
[mA]
BUCK1
Buck [DVS]
PVIN1
1.425
2000
BUCK2
Buck [DVS]
PVIN2
1.200
1000
BUCK3
Buck
PVIN3
3.300
1000
BUCK4
Buck
PVIN4
1.800
1000
LDO1
LDO
VINL1
1.200
300
LDO2
(default OFF)
LDO
VINL2
3.300
300
LDO3
(default OFF)
LDO
VINL2
3.300
300
VODVREF
(default OFF)
LDO
VIN
0.5*DVREFIN
10
VOSNVS
LDO
VIN
3.000
25
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Figure 4-1-1-1: BD71805MWV Power Delivery Map (Slave mode)
Figure 4-1-1-2: BD71805MWV Power Delivery Map (Master mode)
3.3V
EPD
PMIC
I2C EPD
i.MX
(i.MX6SoloLite)
PMIC
LDO_SNVS
(ON/OFF)
Core1
DVREF
LDO3
BUCK1 ARM, SOC, PU
BUCK4
HIGH, NVCC33_IO
LDO1
DDR
(LPDDR2)
WiFi
NVCC_1P2V
NVCC18_IO
SNVS
1.8V
1.425V
3.3V
1.2V
RTC
+
32kHz-OSC
Xtal
Core2
I/O
1.2V
1.8V
0.6V
(½*DVREFIN)
LIB Charger
OVP
DCIN
Power ON/OFF
Sequencer
Coulomb
Counter
3-GPO
BUCK3
SD
Touch
I/O
3.3V
3.3V
3.3V
GPO
GPO
GPO
POWER KEY
PWRON
LDO2
3.3V
R
R
3.3V
BUCK2 1.2V NVCC_DRAM
eMMC
Mode Select
MSSEL
L:GND
EPD
PMIC
I2C
EPD
PMIC
Core1
DVREF
LDO_DVREF
BUCK 1,2 ARM, SOC, PU
BUCK4
HIGH, NVCC33_IO
LDO2
DDR
(LPDDR2)
WiFi
Touch
I/O
3.15V
LDO3
NVCC18_IO
NVCC1P2V, NVCC_DRAM
SNVS
3V
1.375V
3.15V
1.8V
1.2V
RTC
+
32kHz-OSC
Xtal
Core2
I/O
1.2V
1.8V
0.6V
(½*DVREFIN)
DVREFIN
LIB Charger
OVP
DCIN
Power ON/OFF
Sequencer
Coulomb
Counter
3-GPO
LDO1 2.5V
BUCK3
SD eMMC
3.15V
3.15V
3.15V
GPO
GPO
GPO
Power ON/OFF
Control
i.MX
(i.MX6SoloLite)
POWER KEY
PWRON PMIC_ON_REQ
Mode Select
H:VSYS
MSSEL
LDO_SNVS
(Always on)
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4.2 General Layout Guideline
This section explains the guideline for Voltage Regulators. High current voltage rails must be carefully
laid out to avoid unwanted noise interference from other signals and voltage drop. Especially for
switching regulators, abrupt current/ voltage change occurs around the switch-nodes, so please note
this in your layout and be sure to follow all the guidelines in this section.
4.2.1 Overall component Placement Example
Figure 4-2-1 shows the overall component-placement example.
The figure shows the components that are needed to put closely to the BD71805MWV. It is strongly
recommended that power components are put prior to any other components so that the signals do not
interfere with each other.
Figure 4-2-1: Overall component placement example
BUCK4
BUCK3
BUCK1
BUCK2
LDO1-3
VODVREF
SNVSCAP
/VOSNVS
Crystal
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4.2.2 Large Current Loop
There are 2 high pulsing current flowing loops in the buck regulator system.
Loop1:
When Tr2 turns ON, the loop starts from the input capacitor, to VIN terminal, to LX terminal, to L
(inductor), to output capacitors, and then returns to the input capacitor through GND.
Loop2:
When Tr1 turns ON, the loop starts from Tr1, to L (inductor), to output capacitors, and then returns
to Tr1 through GND.
To reduce the noise and improve the efficiency, please minimize these two loops area. Figure 4-2-2-1
shows the current loops which needs to be designed by taking care of parts placement and the
routings.
Figure 4-2-2-1: DC-to-DC Converter Large Current Loops
As Figure 4-2-2-2 shows, please route patterns which load heavy current with short and wide traces as
much as possible to suppress noise that comes from parasitic inductance on PCB and switching
operation, especially for the node’s current that changes drastically such as VIN (input voltage) and
power ground (GND).
Figure 4-2-2-2: Example of parts placement and routing in the top layer of a buck regulator (BUCK1)
Cin L
VIN
Vout
①
②Cout
①
Tr2
Tr1
LX
GND
PGND1
PVIN1
LX1
CIN
COUT
L
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4.2.3 Power GND
Power grounds of DC-to-DC Converters (PGNDx) are noisy ground due to current loops indicated in
the previous section. Thus, power grounds should take large area as much as possible to keep
impedance low and reduce the swing ground voltage level.
4.2.4 VIN (Power supply for BD71805MWV analog circuit)
VIN should not connect with plane VSYS directly to avoid external noise from PVINx due to common
impedance. Also, please place a capacitor near this pin as much as possible to stabilize input power.
Figure 4-2-4: Layout for VIN
4.2.5 Other Signal Pattern Precautions
Make sure to leave adequate space between noisy lines of voltage rail and serial interface (I2C).
4.2.6 Feedback sense line
Feedback Sense terminals (FBx) are used for voltage rails to send out the accurate voltage. In order
for output voltage of each VRs to avoid voltage drop caused by the large current and the parasitic
impedance, please make sure that the feedback sense lines are independently routed from the point
near output capacitors.
VSYS
BD71805MWV
4.7uF
PTH
VIN
(Top layer)
(Inner layer)
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4.3 Switching regulators
4.3.1 BUCK1
BUCK1 is a high-efficiency single buck regulator with integrated FET that converts the VSYS voltage to
a regulated voltage. This VR can dynamically change its output voltage setting using the I2C interface.
BUCK1 output voltage range is from 0.8V to 2.0V (25mV/ step).
4.3.1.1 Schematic Example
Figure 4-3-1-1 BUCK1 Schematic Example
4.3.1.2 Schematic checklist
Table4-3-1-2 BUCK1 schematic checklist
Pin Names
Dir.
Notes (Unit of parts size : inch)
Check
BUCK1
PVIN1[1:0]
I
Connect to VSYS.
As decoupling capacitor, use one 4.7μF.
Select the input capacitor with capacitance≧1.4uF when DC voltage is 5.0V.
<The recommended spec of capacitor is shown below.>
1. Size: 0402, capacitance: 4.7uF± 20%, tolerance: 10V
PGND1[1:0]
I
Connect to Power GND.
LX1[1:0]
O
Connect one 2.2uH ±20% inductor to LX1[1:0].
As output capacitors, use one 10uF capacitors.
<The recommended spec of capacitor is shown below.>
1. Size: 0402, capacitance: 10uF± 20%, tolerance: 6.3V
FB1
I
Connect to BUCK1 output voltage which is regulated by the DC/DC converter of
BD71805MWV.
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