NXP Semiconductors LPC546 Series User manual

UM10912
LPC546xx User manual
Rev. 1.7 — 14 April 2017 User manual
Document information
Info Content
Keywords LPC546xx, ARM Cortex-M4, 32-bit microcontroller, LCD, Ethernet AVB,
SPIFI, SCT/PWM, USB Host, USB device, CAN FD, I2C, I2S, EEPROM,
Flash, EMC, SDRAM controller, DMIC, SDIO interface, SD card interface,
LCD controller, eCRP
Abstract LPC546xx User Manual

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LPC546xx User manual
Revision history
Rev Date Description
1.7 20170414 LPC546xx User manual.
Modifications: •Added Figure 13 “Legacy image boot process flowchart” and Figure 14 “Single Enhanced image
and Dual Enhanced image boot process flowchart”.
1.6 20170331 LPC546xx User manual.
Modifications: •Deleted the remark from bits 2 and 3 in Table 108 “EMC system control register (EMCSYSCTRL,
main syscon: offset 0x444) bit description”
Remark: The state of this bit is preserved through a software reset, and only a POR or a BOD
event will reset it to its default value.
•Updated Table 1006 “Pointer to ISP parameter array”.
For byte offset 1: 1: I2C of Flexcomm 1 and 4: SPI of Flexcomm 3.
•Updated Table 164 “ISP pin assignments”. In USART mode: FC0_TXDPIO0_30; FCO_RXD
PIO0_29.
•Updated bit 29, LOWPRIO description text of Table 1022 “ADC Conversion Sequence A Control
register (SEQA_CTRL, offset 0x08) bit description”.
•Updated Table 963 “I2C / SPI command summary”: Command identifier of Write RAM is 0xB0.
•Updated Table 992 “I2C / SPI ISP write RAM command packet”: changed text to: The
ISP_CMD_WRITE_RAM (0xB0) command is used to erase more than one sector (from a start
sector to an end sector).
•Updated Table 993 “I2C / SPI ISP write RAM response packet”, Table 994 “I2C / SPI ISP go
command packet”, and Table 995 “I2C / SPI ISP go to RAM response packet”: Value of Command
0xB0.
1.5 20170315 LPC546xx User manual.
Modifications: •Updated remark: The SDIO function clock to the interface can be up to 50 MHZ. See Section 27.3
“Basic configuration”. Deleted text: Wake-up: Enable interrupts for waking up from deep-sleep and
deep power-down modes, enable the interrupts in the STARTER1 register. See Section 4.5.91.
•Updated: Changing clock. The cards operate at a maximum of 25 MHz (at maximum of 50 MHz in
high-speed mode and speed detection using CMD6). See Section 27.8.2.1 “Initialization”.
•Updated Table 522 “Timing requirements”: SDR25 (High Speed mode).
1.4 20170307 LPC546xx User manual.
Modifications: •Changed title from LPC5460x to LPC546xx.
1.3 20170228 LPC5460x User manual.
Modifications: •Updated Table 2 “Ordering options” and Table 1 “Ordering information”. Removed references of S
parts.
•Updated Section 6.1 “Features”.
•Updated Table 108 “EMC system control register (EMCSYSCTRL, main syscon: offset 0x444) bit
description”. Removed the remark from bits 2 and 3: The state of this bit is preserved through a
software reset, and only a POR or a BOD event will reset it to its default value.

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LPC546xx User manual
1.2 20170224 LPC5460x User manual.
Modifications: •Removed all references to LPC54S60x.
•Removed all references to AES-engine and SHA.
•Updated Figure 1 “Block diagram” and Figure 2 “Main memory map”.
•Updated Table 5 “Connection of interrupt sources to the NVIC”, Table 8 “Interrupt Set-Enable
Register 1 register”, and Table 30 “Interrupt priority register 13”.
•Updated Table 38 “AHB matrix priority register 0 (AHBMATPRIO, main syscon: offset 0x010) bit
description”.
•Updated Chapter 6 “LPC5460x Boot process”.
•Updated Table 180 “DMA trigger Input mux registers (DMA_ITRIG_INMUX[0:29], offsets
[0x0E0:0x154]) bit description”.
•Updated Table 1013 “IAP Get ROM API pointer command”.
•Updated Chapter 45 “LPC5460x One-Time Programmable (OTP) memory and API”.
•Renamed table title of Table 593 “Supported cursor sizes”: was Palette data storage for STN
monochrome mode.
1.1 20170206 LPC54S60x/LPC5460x User manual.
Modifications: •Updated Table 3 “Memory usage and details”: Address range details and description for address
range: 0x8000 0000 to 0xDFFF FFFF. Static memory chip select: was 0x9000 0000 - 0x93 FFFF,
now, 0x9000 0000 – 0x93FF FFFF.
•Updated Figure 4 “Clock generation”. Removed wdt_clk.
•Updated Table 68 “System PLL clock source select register (SYSPLLCLKSEL, main syscon: offset
0x290) bit description”: Removed Watchdog Oscillator, wdt_clk.
•Updated Section 4.5.77 “FRO Control register”.
•Updated Table 113 “SDIO clock in phase and delay control register (SDIOCLKCTRL, main syscon:
offset 0x460) bit description”: Bit 7, PHASE_ACTIVE description.
•Updated Table 114 “FRO control register (FROCTRL, main syscon: offset 0x500) bit description”:
Bit 31: Reserved.
•Updated Table 855 “USB1 Data buffer start address (DATABUFSTART, offset 0x00C) bit
description”.
•Updated Figure 15 “SCT0 input multiplexing”.
•Updated Table 185 “GPIO pins available”; Added 180-pin device package.
•Updated Table 890 “PTD bit definition”. Fixed NakCnt[3:0] and Cerr[1:0] bit definitions and updated
description for MaxPacketLength[10:0] TT_MPS_Len[10:0].
•Added text: PDSLEEPCFG registers can also be used to turn analog peripherals on or off for
deep-sleep mode to Section 5.2 “General description”.
•Updated Section 5.3.2.1 “Power configuration in active mode”: The clock source for the system
clock can be selected from the FRO (default), crystal oscillator, output of the PLL, the system
oscillator, 32 kHz oscillator, or the watchdog oscillator (see Figure 4 and related registers).
Revision history …continued
Rev Date Description

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LPC546xx User manual
1.1 •Updated Section 6.1 “Features”: Added RSA API calls.
•Updated Section 6.3.2.7 “Image qualification”.
•Updated description of bit 25:16, XFERCOUNT. See Table 245 “Channel transfer configuration
registers bit description”.
•Updated Table 578 “Static Memory Read Delay registers (STATICWAITRD[0:3], address 0x4008
120C (STATICWAITRD0), 0x4008 122C (STATICWAITRD1), 0x4008 124C (STATICWAITRD2),
0x4008 126C (STATICWAITRD3)) bit description”. Changed address of STATICWAITRD0 to
0x4008 120C.
•Table 580 “Static Memory Write Delay registers (STATICWAITWR[0:3], address 0x4008 1214
(STATICWAITWR0), 0x4008 1234 (STATICWAITWR1), 0x4008 1254 (STATICWAITWR2), 0x4008
1274 (STATICWAITWR3)) bit description” Changed address of STATICWAITWR0 to 0x4008 1214.
•Updated Section 33.2 “Features”: Added text: Software support for AVB feature is available from
NXP Professional Services. See nxp.com for more details.
•Added text: USB on-chip drivers are provided via the USB Stack in SDK and LPCOpen software
packages to Section 38.1 “How to read this chapter”.
•Updated Table 939 “Power API calls”.
•Updated Section 40.4.1 “POWER_SetVoltageForFreq”. and Section 40.4.3
“CLOCK_SetupFROClocking”.
•Updated Table 942 “Chip_POWER_EnterPowerMode routine” and Table 943
“Chip_POWER_SetFROHFRate routine”.
•Updated Section 40.4.2.2 “Param1: peripherals”.
•Added a remark to Section 41.4.5.4 “ISP Write to RAM” and Section 41.4.5.5 “ISP Read Memory”.
•Deleted EEPROM from Section 41.4.5.7 “ISP Copy RAM to flash”.
•Updated Section 4.6.4.1 “PLL Features”: Removed 6 kHz to 1.5 MHz Watchdog Oscillator.
1.0 20161221 Initial revision. LPC54S60x/LPC5460x User manual.
Revision history …continued
Rev Date Description

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1.1 Introduction
The LPC546xx is a family of ARM Cortex-M4 based microcontrollers for embedded
applications featuring a rich peripheral set with very low power consumption and
enhanced debug features.
The ARM Cortex-M4 is a 32-bit core that offers system enhancements such as low power
consumption, enhanced debug features, and a high level of support block integration. The
ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture with
separate local instruction and data buses as well as a third bus for peripherals, and
includes an internal prefetch unit that supports speculative branching. The ARM
Cortex-M4 supports single-cycle digital signal processing and SIMD instructions. A
hardware floating-point processor is integrated into the core.
The LPC546xx family includes up to 512 KB of flash, 200 KB of on-chip SRAM, up to 16
kB of EEPROM memory, a quad SPI Flash Interface (SPIFI) for expanding program
memory, one high-speed and one full-speed USB host and device controller, Ethernet
AVB, LCD controller, Smart Card Interfaces, SD/MMC, CAN FD, an External Memory
Controller (EMC), a DMIC subsystem with PDM microphone interface and I2S, five
general-purpose timers, SCTimer/PWM, RTC/alarm timer, Multi-Rate Timer (MRT), a
Windowed Watchdog Timer (WWDT), ten flexible serial communication peripherals
(USART, SPI, I2S, I2C interface), 12-bit 5.0 Msamples/sec ADC, temperature sensor.
1.2 Features
•ARM Cortex-M4 CPU:
–ARM Cortex-M4 processor, running at frequencies of up to 180 MHz.
–Built-in Memory Protection Unit (MPU) supporting eight regions.
–Built-in Nested Vectored Interrupt Controller (NVIC).
–Hardware Floating Point Unit (FPU).
–Non-maskable Interrupt (NMI) input.
–Serial Wire Debug; includes serial wire trace (SWO), ETM Trace, eight (6 + 2)
breakpoints, four watchpoints, and a debug timestamp counter.
–System tick timer.
•On-Chip memory:
–Up to 512 KB on-chip flash program memory with flash accelerator and 256 byte
page erase and write.
–Up to 200 KB total SRAM consisting of 160 kB contiguous main SRAM and an
additional 32 kB SRAM on the I&D buses. 8 kB of SRAM bank intended for USB
traffic.
–16 kB of EEPROM.
UM10912
Chapter 1: LPC546xx Introductory information
Rev. 1.7 — 14 April 2017 User manual

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Chapter 1: LPC546xx Introductory information
•ROM API support:
–Flash In-Application Programming (IAP) and In-System Programming (ISP).
–ROM-based USB drivers (HID, CDC, MSC, and DFU). Supports flash updates via
USB.
–Supports booting from valid user code in flash, USART, SPI, and I2C.
–Legacy, Single, and Dual image boot.
–OTP API for programming OTP memory.
–Random Number Generator (RNG) API.
•Clock generation:
–Crystal oscillator with an operating range of 1 MHz to 25 MHz.
–Internal Free Running Oscillator (FRO) with a high-frequency of 96 MHz output,
medium-frequency of 48 MHz output, and a low-frequency of 12 MHz output,
factory trimmed for accuracy. The FRO output can optionally be used as a system
clock.
–Independent Watchdog Oscillator (WDOSC) with a frequency range of 6 kHz to 1.5
MHz.
–System PLL allows CPU operation up to the maximum CPU rate and can run from
the main oscillator, the internal FRO, the watchdog oscillator or the 32 KHz RTC
oscillator.
–Two additional PLLs for USB clock and audio subsystem.
–Independent clocks for the SPIFI interface, ADC, USBs, and the audio subsystem.
–Clock output function with divider.
–Frequency measurement unit for measuring the frequency of on-chip or off-chip
clock signal.
•Serial interfaces:
–Ten Flexcomm Interface serial peripherals. Each Flexcomm Interface can be
selected by software to be a USART, SPI, or I2C interface. Two Flexcomm
Interfaces also include an I2S interface. Each Flexcomm Interface includes a FIFO
buffer that supports USART, SPI, and I2S if supported by that Flexcomm Interface.
A variety of clocking options are available to each Flexcomm Interface and include
a shared fractional baud-rate generator.
–I2C-bus interfaces support Fast-mode and Fast-mode Plus with data rates of up to
1Mbit/s and with multiple address recognition and monitor mode. Two sets of true
I2C pads also support High Speed Mode (3.4 Mbit/s) as a slave. The slave function
is able to wake up the device from Deep-sleep and Power-down modes.
–Two ISO 7816 Smart Card Interfaces with DMA support.
–USB0 full-speed host/device controller with on-chip PHY and dedicated DMA
controller supporting crystal-less operation in device mode.
–USB1 high-speed host/device controller with on-chip high-speed PHY.
–SPIFI with XIP feature uses up to four data lines to access off-chip SPI/DSPI/QSPI
flash memory at a much higher rate than standard SPI or SSP interfaces.
–Ethernet MAC with MII/RMII interface with Audio Video Bridging (AVB) support and
dedicated DMA controller.
–Two CAN FD modules with dedicated DMA controller.

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Chapter 1: LPC546xx Introductory information
•Digital peripherals:
–DMA controller with 30 channels and up to 24 programmable request/trigger
sources and able to access all memories and DMA-capable peripherals.
–LCD Controller supporting both Super-Twisted Nematic (STN) and Thin-Film
Transistor (TFT) displays. It has a dedicated DMA controller, selectable display
resolution (up to 1024 x 768 pixels), and supports up to 24-bit true-color mode.
–External Memory Controller (EMC) provides support for asynchronous static
memory devices such as RAM, ROM and flash, in addition to dynamic memories
such as single data rate SDRAM with an SDRAM clock of up to 100 MHz.
–Secured digital input/output (SD/MMC) card interface with DMA support.
–CRC engine block can calculate a CRC on supplied data using one of three
standard polynomials with DMA support.
–Up to 171 General-Purpose Input/Output (GPIO) pins.
–GPIO registers are located on the AHB for fast access. The DMA supports GPIO
ports.
–Up to eight GPIOs can be selected as pin interrupts (PINT), triggered by rising,
falling or both input edges.
–Two GPIO grouped interrupts (GINT) enable an interrupt based on a logical
(AND/OR) combination of input states.
•Analog peripherals:
–12-bit, 12-channel, Analog-to-Digital Converter (ADC) supporting 5.0 Msamples/s.
The ADC supports two independent conversion sequences.
–Integrated temperature sensor connected to the ADC.
•Security features:
–Random number generator can be used to create keys with DMA support.
–enhanced Code Read Protection (eCRP) to protect user code.
–OTP memory for ECRP settings and user application specific data.
•DMIC subsystem includes a dual-channel PDM microphone interface with
decimators, filtering, and hardware voice activity detection. The processed output
data can be routed directly to an I2S interface if needed.
•Timers
–Five 32-bit general purpose timers/counters, with up to 4 capture inputs and 4
compare outputs, PWM mode, and external count input. Specific timer events can
be selected to generate DMA requests. The fifth timer does not have external pin
connections and may be used for internal timing operations.
–SCTimer/PWM with 8 input and 10 output functions (including capture and match).
Inputs and outputs can be routed to/from external pins and internally to/from
selected peripherals. Internally, the SCTimer/PWM supports 16 match/captures, 16
events, and 16 states.
–24-bit Multi-Rate Timer (MRT) module with four channels each capable of
generating repetitive interrupts at different, programmable frequencies.

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Chapter 1: LPC546xx Introductory information
–32-bit Real-time clock (RTC) with 1 s resolution running in the always-on power
domain. A timer in the RTC can be used for wake-up from all low power modes
including deep power-down, with 1 ms resolution. The RTC is clocked by the
32.768 kHz oscillator.
–Multiple-channel multi-rate 24-bit timer (MRT) for repetitive interrupt generation at
up to four programmable, fixed rates.
–Windowed Watchdog Timer (WWDT) with dedicated watchdog oscillator.
–Ultra-low power Micro-tick Timer, running from the Watchdog oscillator that can be
used to wake up the device from low power modes.
–Repetitive Interrupt Timer (RIT) for debug time-stamping and for general purpose
use.
•Power-saving modes and wake-up:
–Integrated PMU (Power Management Unit) to minimize power consumption.
–Reduced power modes: sleep, deep-sleep, power-down, and deep power-down.
–Wake-up from deep-sleep and power-down modes via activity on the USART, SPI,
and I2C peripherals when operating as slaves.
–Wake-up from sleep, deep-sleep, power-down, and deep power-down modes
using the RTC alarm.
–The Micro-tick Timer can wake-up the device from any reduced power mode by
using the watchdog oscillator when no other on-chip resources are running.
–Power-On Reset (POR).
–Brown-Out Detect (BOD) with separate thresholds for interrupt and forced reset.
•Single power supply 1.71 V to 3.6 V.
•JTAG boundary scan supported.
•128 bit unique device serial number for identification.
•Operating temperature range 40 °C to +105 °C.
•Available in TFBGA180 and LQFP208 packages.

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Chapter 1: LPC546xx Introductory information
1.3 Block diagram
Each Flexcomm Interface includes USART, SPI, and I2C functions. Flexcomm Interface 6
and 7 each also provide an I2S function.
Fig 1. Block diagram
DEBUG INTERFACE
ISP access
port
JTAG test and
boundary scan
interface ethernet
PHY interface LCD panel SDIO interface CAN interface
FS USB
bus or
transceiver
ARM CORTEX-M4
WITH FPU/MPU
D-code
bus system bus
I-code
bus
aaa-026740
GENERAL
PURPOSE
DMA
CONTROLLER
ETHERNET
10/100
MAC
+AVB
LCD
PANEL
INTERFACE
USB 2.0
HOST/
DEVICE
HD
SDIO CAN
FD
CAN
FD clocks
and
controls
internal
power
CLOCK GENERATION,
POWER CONTROL,
AND OTHER
SYSTEM FUNCTIONS
VOLTAGE REGULATOR
Xtalin Xtalout RST
CLK
OUT
SPIFI
ADC
inputs
D[31:0]
A[25:0]
control
GPIO
Vdd
HS USB
PHY
BOOT ROM
64 kB
SRAM
32 kB
SRAM
32 kB
SRAM
32 kB
SRAM
32 kB
12b ADC
12-CH
TEMP
SENSOR
POLYFUSE OTP
256 b
STATIC/DYNAMIC EXT
MEMORY CONTROLLER
HS USB
HOST
REGISTERS
FS USB
HOST
REGISTERS
USB RAM
INTERFACE
SRAM
8 kB
EEPROM
UP TO 16 kB
SPI FLASH
INTERFACE
SRAM
64 kB
FLASH
INTERFACE
AND
ACCELERATOR
FLASH
512 MB
HS USB
bus
HS GPIO
0-5
FS USB
DEVICE
REGISTERS
LCD
REGISTERS
DMA
REGISTERS
EMC
REGISTERS
SPIFI
REGISTERS
MULTILAYER
AHB MATRIX
SCTimer/
PWM FlexComms 0-4
-UARTs 0-4 - I2Cs 0-4
-SPI0s 0-4
CRC
ENGINE
HS USB
DEVICE
REGISTERS AUDIO SUBSYS
D-MIC,
DECIMATOR, ETC
ETHERNET
REGISTERS
CAN 1
REGISTERS
AHB TO
APB BRIDGE
AHB TO
APB BRIDGE
ASYNC AHB TO
APB BRIDGE
CAN 0
REGISTERS
SYSTEM CONTROL
APB slave group 0
SDIO
REGISTERS FlexComms 5-9
-UARTs 5-9
-SPI0s 5-9
-I2Cs 5-9 - I2Ss 0,1
I/O CONFIGURATION
Note:
- Orange shaded blocks support Gen. Purpose DMA.
- Yellow shaded blocks include dedicated DMA Ctrl.
GPIO GLOBAL INTRPTS (0, 1)
GPIO INTERRUPT CONTROL
PERIPH INPUT MUX SELECTS
2 x 32-BIT TIMERS (T0, 1)
PMU REGS (+BB, PVT)
APB slave group 1
32-BIT TIMERS (T2)
SYSTEM CONTROL (async regs)
APB slave group 2
2 x 32-BIT TIMERS (T3, 4)
OS TIMER
FLASH 0 REGISTERS
2 x SMARTCARDS
RANDOM NUMBER GEN
REAL TIME
CLOCK 32 kHz Osc
RTC ALARM RTC POWER
DOMAIN
DIVIDER
MULTI-RATE TIMER
EEPROM REGISTERS
OTP CONTROLLER
WATCHDOG
OSC WINDOWED WDT
MICRO TICK TIMER

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Chapter 1: LPC546xx Introductory information
1.4 Architectural overview
The ARM Cortex-M4 includes three AHB-Lite buses, one system bus and the I-code and
D-code buses. One bus is dedicated for instruction fetch (I-code), and one bus is
dedicated for data access (D-code). The use of two core buses allows for simultaneous
operations if concurrent operations target different devices.
A multi-layer AHB matrix connects the CPU buses and other bus masters to peripherals in
a flexible manner that optimizes performance by allowing peripherals on different slaves
ports of the matrix to be accessed simultaneously by different bus masters. More
information on the multilayer matrix can be found in Section 2.1.4. Connections in the
multilayer matrix are shown in Figure 1. Note that while the AHB bus itself supports word,
halfword, and byte accesses, not all AHB peripherals need or provide that support.
APB peripherals are connected to the AHB matrix via two APB buses using separate
slave ports from the multilayer AHB matrix. This allows for better performance by reducing
collisions between the CPU and the DMA controller, and also for peripherals on the
asynchronous bridge to have a fixed clock that does not track the system clock. Note that
APB, by definition, does not directly support byte or halfword accesses.
1.5 ARM Cortex-M4 processor
The Cortex-M4 is a general purpose 32-bit microprocessor, which offers high performance
and very low power consumption. The Cortex-M4 offers a Thumb-2 instruction set, low
interrupt latency, interruptible/continuable multiple load and store instructions, automatic
state save and restore for interrupts, tightly integrated interrupt controller, multiple core
buses capable of simultaneous accesses, and a floating point unit.
A 3-stage pipeline is employed so that all parts of the processing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.
Information about Cortex-M4 configuration options can be found in Chapter 50.
1.6 On-chip flash memory system
The LPC546xx contains up to 512 kB of on-chip flash memory. A flash memory
accelerator maximizes performance for CPU accesses. This memory may be used for
both code and data storage. Programming of the flash memory may be accomplished in
several ways. It may be programmed In System via the serial port. The application
program may also erase and/or program the flash while the application is running,
allowing a great degree of flexibility for data storage field firmware upgrades, etc.
1.7 On-chip Static RAM
The LPC546xx contains up to 200 kB of on-chip static RAM. 8 kB of SRAM is intended for
the use by high-speed USB host/device peripherals. There are 6 banks of SRAM and
each bank is placed at a separate slave port. This architecture allows the possibility for
CPU and DMA accesses to be separated in such a way that there are few or no delays for
the bus masters. It also allows separation of data for different peripherals functions, in

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Chapter 1: LPC546xx Introductory information
order to improve system performance. For example, LCD DMA can be occurring in one
SRAM while Ethernet DMA is occurring in another, all while the CPU is using the Main
SRAM for data and/or instruction access.
1.8 On-chip EEPROM
The LPC546xx contains up to 16 kB of on-chip EEPROM memory. The EEPROM is
accessible only by the CPU.

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Chapter 1: LPC546xx Introductory information
1.9 Ordering information
1.9.1 Ordering options
Table 1. Ordering information
Type number Package
Name Description Version
LPC54605J256ET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 ´ 12 ´ 0.8 mm SOT570-3
LPC54605J512ET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 ´ 12 ´ 0.8 mm SOT570-3
LPC54606J256ET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 ´ 12 ´ 0.8 mm SOT570-3
LPC54606J512BD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm SOT459-1
LPC54607J256ET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 ´ 12 ´ 0.8 mm SOT570-3
LPC54607J512ET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 ´ 12 ´ 0.8 mm SOT570-3
LPC54607J256BD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm SOT459-1
LPC54608J512ET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 ´ 12 ´ 0.8 mm SOT570-3
LPC54608J512BD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm SOT459-1
LPC54616J256ET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 ´ 12 ´ 0.8 mm SOT570-3
LPC54616J512BD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm SOT459-1
LPC54618J512ET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 ´ 12 ´ 0.8 mm SOT570-3
LPC54618J512BD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm SOT459-1
Table 2. Ordering options
Type number Package Name Flash/kB SRAM/kB FS USB HS USB Ethernet AVB Classic CAN CAN FD0/FD1 LCD GPIO
LPC54618 devices (HS/FS USB, Ethernet, CAN FD, LCD)
LPC54618J512ET180 TFBGA180 512 200 yes yes yes yes yes yes 145
LPC54618J512BD208 LQFP208 512 200 yes yes yes yes yes yes 171
LPC54616 devices (HS/FS USB, Ethernet, CAN FD)
LPC54616J256ET180 TFBGA180 256 136 yes yes yes no yes no 145
LPC54616J512BD208 LQFP208 512 200 yes yes yes no yes no 171
LPC54608 devices (HS/FS USB, Ethernet, CAN 2.0, LCD)
LPC54608J512ET180 TFBGA180 512 200 yes yes yes yes no yes 145
LPC54608J512BD208 LQFP208 512 200 yes yes yes yes no yes 171
LPC54607 devices (HS/FS USB, LCD)
LPC54607J256ET180 TFBGA180 256 136 yes yes no no no yes 145
LPC54607J512ET180 TFBGA180 512 200 yes yes no no no yes 145
LPC54607J256BD208 LQFP208 256 136 yes yes no no no yes 171
LPC54606 devices (HS/FS USB, Ethernet, CAN 2.0)
LPC54606J256ET180 TFBGA180 256 136 yes yes yes yes no no 145
LPC54606J512BD208 LQFP208 512 200 yes yes yes yes no no 171

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Chapter 1: LPC546xx Introductory information
LPC54605 devices (HS/FS USB)
LPC54605J256ET180 TFBGA180 256 136 yes yes no no no no 145
LPC54605J512ET180 TFBGA180 512 200 yes yes no no no no 145
Table 2. Ordering options …continued
Type number Package Name Flash/kB SRAM/kB FS USB HS USB Ethernet AVB Classic CAN CAN FD0/FD1 LCD GPIO

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2.1 General description
The LPC546xx incorporates several distinct memory regions. Figure 2 shows the overall
map of the entire address space from the user program viewpoint following reset.
The APB peripheral area (detailed in Figure 3) is divided into fixed 4 KB slots to simplify
addressing.
The registers incorporated into the CPU, such as NVIC, SysTick, and sleep mode control,
are located on the private peripheral bus.
2.1.1 Memory map and peripheral addressing
The ARM Cortex-M4 processor has a single 4 GB address space. The following table
shows how this space is used on the LPC546xx.
UM10912
Chapter 2: LPC546xx Memory map
Rev. 1.7 — 14 April 2017 User manual
Table 3. Memory usage and details
Address range General Use Address range details and description
0x0000 0000 to 0x1FFF FFFF On-chip
non-volatile
memory
0x0000 0000 - 0x0007 FFFF Flash memory (512 KB).
Boot ROM 0x0300 0000 - 0x0300 FFFF Boot ROM with flash services in a 64 KB
space.
SRAMX 0x0400 0000 - 0x0400 7FFF I&D SRAM bank (32 KB).
SPI Flash
Interface (SPIFI) 0x1000 0000 - 0x17FF FFFF SPIFI memory mapped access space (128 MB).
0x2000 0000 to 0x3FFF FFFF SRAM Banks 0x2000 0000 - 0x2002 7FFF SRAM banks (160 KB).
SRAM bit band
alias addressing 0x2200 0000 - 0x23FF FFFF SRAM bit band alias addressing (32 MB)
0x4000 0000 to 0x7FFF FFFF APB peripherals 0x4000 0000 - 0x4001 FFFF APB slave group 0 up to 32 peripheral
blocks of 4 KB each (128 KB).
0x4002 0000 - 0x4003 FFFF APB slave group 1 up to 32 peripheral
blocks of 4 KB each (128 KB).
0x4004 0000 - 0x4005 FFFF APB asynchronous slave group 2 up to
32 peripheral blocks of 4 KB each
(128 KB).
AHB peripherals 0x4008 0000 - 0x400B FFFF AHB peripherals (256 KB).
USB SRAM 0x4010 0000 - 0x4010 1FFC USB SRAM (8 KB)
Peripheral bit
band alias
addressing
0x4200 0000 - 0x43FF FFFF Peripheral bit band alias addressing
(32 MB)

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Chapter 2: LPC546xx Memory map
[1] Can be up to 256 MB, upper address 0x8FFF FFFF, if the address shift mode is enabled. See
EMCSYSCTRL register bit 0 (Section 4.5.71).
[2] Can be up to 128 MB, upper address 0x97FF FFFF, if the address shift mode is enabled. See
EMCSYSCTRL register bit 0 (Section 4.5.71).
2.1.2 SRAM
The Main SRAM is comprised of up to a total 160 KB of contiguous, on-chip static RAM
memory (this is in addition to SRAMX as noted in the next section below, so the total
device SRAM can be up to 200 KB). The Main SRAM is further divided to allow for more
control of power usage when less SRAM is required: SRAM0 (up to 64 KB), SRAM1 (up to
32 KB), SRAM2 (up to 32 KB), and SRAM3 (up to 32 KB). Each SRAM has a separate
clock control and power switch, see Section 4.5.19 “AHB Clock Control register 0”and
Section 4.5.84 “Power Configuration register 0”.
An additional on-chip static RAM memory is available that is not contiguous to the main
SRAM. This RAM is called SRAMX, and resides on the local buses (I-Code and D-Code)
of the Cortex-M4, and on the main bus of the Cortex-M0+. This RAM can be used, for
example, as the location for the program stack, common data, or any other use where a
separate access away from the Main SRAM has an advantage. SRAMX can be disabled
or enabled in the SYSCON block to save power. See Section 4.5.84 “Power Configuration
register 0”. Also, an additional 8 KB SRAM is available for USB operations or it can be
used as a general purpose SRAM when not used for USB.
0x8000 0000 to 0xDFFF FFFF Off-chip Memory
via the External
Memory
Controller
Four static memory chip selects:
0x8000 0000 - 0x83FF FFFF Static memory chip select 0 (up to 64
MB)[1]
0x8800 0000 - 0x8BFF FFFF Static memory chip select 1 (up to 64
MB)[2]
0x9000 0000 – 0x93FF FFFF Static memory chip select 2 (up to 64
MB)
0x9800 0000 - 0x9BFF FFFF Static memory chip select 3 (up to 64
MB)
Four dynamic memory chip selects:
0xA000 0000 - 0xA7FF FFFF Dynamic memory chip select 0 (up to
256MB)
0xA800 0000 - 0xAFFF FFFF Dynamic memory chip select 1 (up to
256MB)
0xB000 0000 - 0xB7FF FFFF Dynamic memory chip select 2 (up to
256MB)
0xB800 0000 - 0xBFFF FFFF Dynamic memory chip select 3 (up to
256MB)
0xE000 0000 to 0xE00F FFFF Cortex-M4
Private
Peripheral Bus
0xE000 0000 - 0xE00F FFFF Cortex-M4 related functions, includes
the NVIC and System Tick Timer.
Table 3. Memory usage and details
Address range General Use Address range details and description

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Chapter 2: LPC546xx Memory map
2.1.2.1 SRAM usage notes
Although always contiguous on all LPC546xx devices, SRAM0, SRAM1, SRAM2, and
SRAM3 are placed on different AHB matrix ports. This allows user programs to potentially
obtain better performance by dividing RAM usage among the ports. For example,
simultaneous access to SRAM0 by the CPU and SRAM1 by the system DMA controller
does not result in any bus stalls for either master.
Generally, data being communicated via peripherals will be accessed by the CPU at some
point, even when peripheral data is mainly being transferred via DMA. So, in order to
minimizing data read/write stalls, data buffers may be placed in RAMs on different AHB
matrix ports. For instance, if DMA is writing to one buffer on a specific AHB matrix port
while the CPU is reading data from a buffer on a different AHB matrix port, there is no stall
for either the CPU or the DMA. Sequences of data from the same peripheral could be
alternated between RAM on each port. This could be helpful if DMA fills or empties a RAM
buffer, then signals the CPU before proceeding on to a second buffer. The CPU would
then tend to access the data while the DMA is using the other RAM.
2.1.2.2 Bit-band addressing
The ARM Cortex-M4 CPU provides a bit-band addressing feature. This offers efficient bit
accesses to selected memory regions.
Bits in the address region 0x2000 0000 to 0x200F FFFF (bits addressed at addresses
0x2200 0000 to 0x23FF FFFF) include the entire main SRAM area (does not include
SRAMX which is at a lower address).
Bits in the address region 0x4000 0000 to 0x400F FFFF (bits addressed at addresses
0x4200 0000 to 0x43FF FFFF) include all AHB and APB peripherals. This space does not
include the USB RAM and the EEPROM.
Reads from bit-band addresses return the respective bit from the bit-band region. Writes
perform an atomic read-modify-write on the respective bit of the bit-band region. For
details, see the ARM Cortex-M4 technical reference manual.
To calculate a bit band address:
Bit address = (Byte offset within bit-band space * 32) + (bit number in byte * 4) + bit-band
base address
Where:
•Bit addressable RAM base address = 0x2000 0000
•AHB/APB peripheral base address = 0x4000 0000
•RAM bit-band base address = 0x2200 0000
Table 4. SRAM configuration
SRAMX SRAM0 SRAM1 SRAM2 SRAM3 USB RAM
(total SRAM = up to 200 kB)
Size Up to 32 kB Up to 64 kB Up to 32 kB Up to 32 kB Up to 32 kB 8 kB
Address
range Beginsat0x0400 0000 Begins at 0x2000 0000 Begins at 0x2001 0000 Begins at 0x2001 8000 Begins at 0x2002 0000 If present, begins at
0x4010 0000

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Chapter 2: LPC546xx Memory map
•AHB/APB peripheral bit-band base address = 0x4200 0000
•Byte offset within bit-band space: the offset within the related bit-band space (bit
addressable RAM space or AHB/APB peripheral space). For example, the offset of bit
addressable RAM address 0x201F A127 = 0x200FA127 - 0x2000 0000 =
0x000F A127
For example, the bit-band address of bit 5 of RAM address 0x201FA127 =
((0x201FA127 - 0x2000 0000) * 32) + 5 * 4) + 0x2200 0000 = 0x1F4 24E0 + 14 +
0x2200 0000 = 0x23F4 24F4.
Remark: Because bit-band operations are implemented as read-modify-write operations,
and appear on the AHB bus in that manner, some uses of bit-banding may not work as
intended. For example, if a peripheral register contains several write-one-to-clear status
flags, attempting to clear one such flag using bit-banding will actually clear all such flags
that read as a one in that register.

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Chapter 2: LPC546xx Memory map
2.1.3 Memory mapping
The overall memory map is shown in Figure 2 “Main memory map”. Details of APB
peripheral mapping are shown in Figure 3 “APB memory map”.
The private peripheral bus includes CPU peripherals such as the NVIC, SysTick, and the core control registers.
Fig 2. Main memory map
aaa-026742
Memory space
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
Boot ROM
(reserved)
(reserved)
active interrupt vectors
(EMC)
private peripheral bus
peripheral
bit-band addressing
Asynchronous
APB peripherals
APB peripherals on
APB bridge 1
APB peripherals on
APB bridge 0
SRAM bit-band
addressing
SRAM2
(up to 32 kB)
SRAM1
(up to 64 kB)
SRAMX
(32 kB)
SRAM0
(up to 64 kB)
SPIFI Flash Interface
memory mapped space
Flash memory
(up to 512 kB)
AHB
peripheral
AHB peripherals
0x4009 B000
0x4009 A000
0x4009 9000
0x4009 8000
0x4009 7000
0x4009 6000
0x4009 5000
0x4009 4000
0x4009 2000
0x4009 1000
0x4009 0000
0x4008 C000
0x4008 B000
0x4008 A000
0x4008 9000
0x4008 8000
0x4008 7000
0x4008 6000
0x4008 5000
0x4008 4000
0x4008 3000
0x4008 2000
0x4008 1000
0x4008 0000
0x4009 C000
0x4009 D000
0x4009 E000
0x400A 0000
0x400A 1000
0x400A 2000
0x4010 BFFF
0x400A 3000
0x400A 4000
0x400A 5000
0x4010 0000
0x4010 2000
0x4010 8000
0x4004 0000 see APB
memory
map figure
0x4002 0000
0x0000 0000
0x0000 00C0
0x0000 0000
0x0008 0000
0x0300 0000
0x0300 0000
0x0400 0000
0x0401 0000
0x1000 0000
0x1800 0000
0x2000 0000
0x2001 0000
0x2002 0000
0x2002 0000
0x2200 0000
0x2400 0000
0x4000 0000
0x4006 0000
0x4008 0000
0x400C 0000
0x4200 0000
0x4400 0000
0x8000 0000
0xE000 0000
0xE010 0000
0xFFFF FFFF
FS USB host registers
(reserved)
USB SRAM (8 kB)
(reserved)
HS USB host registers
EPROM (16 kB)
(reserved)
ADC
ISP-AP interface
Flexcomm 8
Flexcomm 7
Flexcomm 6
Flexcomm 5
(reserved)
CAN 1
CAN 0
SDIO
Flexcomm 9
CRC engine
(reserved)
D-Mic interface
High Speed GPIO
(reserved)
Flexcomm 4
Flexcomm 3
Flexcomm 2
Flexcomm 1
Flexcomm 0
SC Timer / PWM
FS USB device registers
LCD registers
DMA registers
EMC registers
SPIFI registers
Ethernet
HS USB device

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Chapter 2: LPC546xx Memory map
2.1.4 AHB multilayer matrix
The LPC546xx uses a multi-layer AHB matrix to connect the CPU buses and other bus
masters to peripherals in a flexible manner that optimizes performance by allowing
peripherals that are on different slave ports of the matrix to be accessed simultaneously
by different bus masters. Figure 1 shows details of the potential matrix connections.
2.1.5 Memory Protection Unit (MPU)
The Cortex-M4 processor has a memory protection unit (MPU) that provides fine grain
memory control, enabling applications to implement security privilege levels, separating
code, data and stack on a task-by-task basis. Such requirements are critical in many
embedded applications.
The MPU register interface is located on the private peripheral bus and is described in
detail in Ref. 1 “Cortex-M4 TRM”.
Fig 3. APB memory map
21
20
19-14
13
11-9
8
7-0
0x4003 6000
0x4003 5000
0x4003 4000
0x4002 D000
0x4002 C000
0x4002 9000
0x4002 8000
0x4002 0000
(reserved)
(reserved)
(reserved)
(reserved)
RIT
Flash controller
CTIMER2
APB bridge 1
19-15
14
13
12
11-10
9
8
0x4001 4000
0x4001 F000
0x4000 E000
0x4000 D000
0x4000 C000
0x4000 A000
0x4000 9000
0x4000 8000
0x4000 6000
0x4000 5000
0x4000 4000
0x4000 3000
0x4000 2000
0x4000 1000
0x4000 0000
(reserved)
MRT
(reserved)
CTIMER0
WDT
Micro-Tick
CTIMER1
APB bridge 0
7-6
5
4
3
2
1
Input muxes
GINT1
IOCON
Pin Interrupts (PINT)
(reserved)
GINT0
2Syscon
31-10
9
8
7-1
0
0x4005 FFFF
0x4004 A000
0x4004 9000
0x4004 8000
0x4004 1000
0x4004 0000
(reserved)
CTIMER3
Asynch. Syscon
(reserved)
CTIMER4
Asynchronous APB bridge
aaa-023944
EEPROM controller
OTP controller
(reserved)
20
0x4001 FFFF
0x4001 5000
21
31-22
Smart card 0
Smard card 1
22
23
0x4001 6000
(reserved)
0x4003 7000
0x4003 8000
0x4003 FFFF
25-24
RTC
0x4002 E000
12
26 RNG
31-27 (reserved)
0x4003 A000
0x4003 B000

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3.1 How to read this chapter
Available interrupt sources may vary with specific LPC546xx device types.
3.2 Features
•Nested Vectored Interrupt Controller that is an integral part of each CPU.
•Tightly coupled interrupt controller provides low interrupt latency.
•Controls system exceptions and peripheral interrupts.
•The NVIC of the Cortex-M4 supports:
–54 vectored interrupt slots.
–8 programmable interrupt priority levels with hardware priority level masking.
–Vector table offset register VTOR.
–Software interrupt generation.
•Support for NMI from any interrupt (see Section 4.5.3).
3.3 General description
The tight coupling to the NVIC to the CPU allows for low interrupt latency and efficient
processing of late arriving interrupts.
3.3.1 Interrupt sources
Table 5 lists the interrupt sources for each peripheral function. Each peripheral device
may have one or more interrupt lines to the Vectored Interrupt Controller. Each line may
represent more than one interrupt source. The interrupt number does not imply any
interrupt priority.
See Ref. 1 “Cortex-M4 TRM”for detailed descriptions of the NVIC and the NVIC registers.
UM10912
Chapter 3: LPC546xx Nested Vectored Interrupt Controller
(NVIC)
Rev. 1.7 — 14 April 2017 User manual
Table 5. Connection of interrupt sources to the NVIC
Interrupt Name Interrupt description Flags
0 WDT, BOD Windowed watchdog timer, Brownout detect WARNINT - watchdog warning
interrupt
BODINTVAL - BOD interrupt level
1 DMA DMA controller Interrupt A and interrupt B, error
interrupt
2 GINT0 GPIO group 0 Enabled pin interrupts
3 GINT1 GPIO group 1 Enabled pin interrupts
4 PIN_INT0 Pin interrupt 0 or pattern match engine slice 0 PSTAT - pin interrupt status
5 PIN_INT1 Pin interrupt 1or pattern match engine slice 1 PSTAT - pin interrupt status
6 PIN_INT2 Pin interrupt 2 or pattern match engine slice 2 PSTAT - pin interrupt status