NXP Semiconductors LPC546 Series User manual

UM10912
LPC546xx User manual
Rev. 1.7 — 14 April 2017 User manual
Document information
Info Content
Keywords LPC546xx, ARM Cortex-M4, 32-bit microcontroller, LCD, Ethernet AVB,
SPIFI, SCT/PWM, USB Host, USB device, CAN FD, I2C, I2S, EEPROM,
Flash, EMC, SDRAM controller, DMIC, SDIO interface, SD card interface,
LCD controller, eCRP
Abstract LPC546xx User Manual

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User manual Rev. 1.7 — 14 April 2017 2 of 1149
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LPC546xx User manual
Revision history
Rev Date Description
1.7 20170414 LPC546xx User manual.
Modifications: •Added Figure 13 “Legacy image boot process flowchart” and Figure 14 “Single Enhanced image
and Dual Enhanced image boot process flowchart”.
1.6 20170331 LPC546xx User manual.
Modifications: •Deleted the remark from bits 2 and 3 in Table 108 “EMC system control register (EMCSYSCTRL,
main syscon: offset 0x444) bit description”
Remark: The state of this bit is preserved through a software reset, and only a POR or a BOD
event will reset it to its default value.
•Updated Table 1006 “Pointer to ISP parameter array”.
For byte offset 1: 1: I2C of Flexcomm 1 and 4: SPI of Flexcomm 3.
•Updated Table 164 “ISP pin assignments”. In USART mode: FC0_TXDPIO0_30; FCO_RXD
PIO0_29.
•Updated bit 29, LOWPRIO description text of Table 1022 “ADC Conversion Sequence A Control
register (SEQA_CTRL, offset 0x08) bit description”.
•Updated Table 963 “I2C / SPI command summary”: Command identifier of Write RAM is 0xB0.
•Updated Table 992 “I2C / SPI ISP write RAM command packet”: changed text to: The
ISP_CMD_WRITE_RAM (0xB0) command is used to erase more than one sector (from a start
sector to an end sector).
•Updated Table 993 “I2C / SPI ISP write RAM response packet”, Table 994 “I2C / SPI ISP go
command packet”, and Table 995 “I2C / SPI ISP go to RAM response packet”: Value of Command
0xB0.
1.5 20170315 LPC546xx User manual.
Modifications: •Updated remark: The SDIO function clock to the interface can be up to 50 MHZ. See Section 27.3
“Basic configuration”. Deleted text: Wake-up: Enable interrupts for waking up from deep-sleep and
deep power-down modes, enable the interrupts in the STARTER1 register. See Section 4.5.91.
•Updated: Changing clock. The cards operate at a maximum of 25 MHz (at maximum of 50 MHz in
high-speed mode and speed detection using CMD6). See Section 27.8.2.1 “Initialization”.
•Updated Table 522 “Timing requirements”: SDR25 (High Speed mode).
1.4 20170307 LPC546xx User manual.
Modifications: •Changed title from LPC5460x to LPC546xx.
1.3 20170228 LPC5460x User manual.
Modifications: •Updated Table 2 “Ordering options” and Table 1 “Ordering information”. Removed references of S
parts.
•Updated Section 6.1 “Features”.
•Updated Table 108 “EMC system control register (EMCSYSCTRL, main syscon: offset 0x444) bit
description”. Removed the remark from bits 2 and 3: The state of this bit is preserved through a
software reset, and only a POR or a BOD event will reset it to its default value.

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User manual Rev. 1.7 — 14 April 2017 3 of 1149
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LPC546xx User manual
1.2 20170224 LPC5460x User manual.
Modifications: •Removed all references to LPC54S60x.
•Removed all references to AES-engine and SHA.
•Updated Figure 1 “Block diagram” and Figure 2 “Main memory map”.
•Updated Table 5 “Connection of interrupt sources to the NVIC”, Table 8 “Interrupt Set-Enable
Register 1 register”, and Table 30 “Interrupt priority register 13”.
•Updated Table 38 “AHB matrix priority register 0 (AHBMATPRIO, main syscon: offset 0x010) bit
description”.
•Updated Chapter 6 “LPC5460x Boot process”.
•Updated Table 180 “DMA trigger Input mux registers (DMA_ITRIG_INMUX[0:29], offsets
[0x0E0:0x154]) bit description”.
•Updated Table 1013 “IAP Get ROM API pointer command”.
•Updated Chapter 45 “LPC5460x One-Time Programmable (OTP) memory and API”.
•Renamed table title of Table 593 “Supported cursor sizes”: was Palette data storage for STN
monochrome mode.
1.1 20170206 LPC54S60x/LPC5460x User manual.
Modifications: •Updated Table 3 “Memory usage and details”: Address range details and description for address
range: 0x8000 0000 to 0xDFFF FFFF. Static memory chip select: was 0x9000 0000 - 0x93 FFFF,
now, 0x9000 0000 – 0x93FF FFFF.
•Updated Figure 4 “Clock generation”. Removed wdt_clk.
•Updated Table 68 “System PLL clock source select register (SYSPLLCLKSEL, main syscon: offset
0x290) bit description”: Removed Watchdog Oscillator, wdt_clk.
•Updated Section 4.5.77 “FRO Control register”.
•Updated Table 113 “SDIO clock in phase and delay control register (SDIOCLKCTRL, main syscon:
offset 0x460) bit description”: Bit 7, PHASE_ACTIVE description.
•Updated Table 114 “FRO control register (FROCTRL, main syscon: offset 0x500) bit description”:
Bit 31: Reserved.
•Updated Table 855 “USB1 Data buffer start address (DATABUFSTART, offset 0x00C) bit
description”.
•Updated Figure 15 “SCT0 input multiplexing”.
•Updated Table 185 “GPIO pins available”; Added 180-pin device package.
•Updated Table 890 “PTD bit definition”. Fixed NakCnt[3:0] and Cerr[1:0] bit definitions and updated
description for MaxPacketLength[10:0] TT_MPS_Len[10:0].
•Added text: PDSLEEPCFG registers can also be used to turn analog peripherals on or off for
deep-sleep mode to Section 5.2 “General description”.
•Updated Section 5.3.2.1 “Power configuration in active mode”: The clock source for the system
clock can be selected from the FRO (default), crystal oscillator, output of the PLL, the system
oscillator, 32 kHz oscillator, or the watchdog oscillator (see Figure 4 and related registers).
Revision history …continued
Rev Date Description

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LPC546xx User manual
1.1 •Updated Section 6.1 “Features”: Added RSA API calls.
•Updated Section 6.3.2.7 “Image qualification”.
•Updated description of bit 25:16, XFERCOUNT. See Table 245 “Channel transfer configuration
registers bit description”.
•Updated Table 578 “Static Memory Read Delay registers (STATICWAITRD[0:3], address 0x4008
120C (STATICWAITRD0), 0x4008 122C (STATICWAITRD1), 0x4008 124C (STATICWAITRD2),
0x4008 126C (STATICWAITRD3)) bit description”. Changed address of STATICWAITRD0 to
0x4008 120C.
•Table 580 “Static Memory Write Delay registers (STATICWAITWR[0:3], address 0x4008 1214
(STATICWAITWR0), 0x4008 1234 (STATICWAITWR1), 0x4008 1254 (STATICWAITWR2), 0x4008
1274 (STATICWAITWR3)) bit description” Changed address of STATICWAITWR0 to 0x4008 1214.
•Updated Section 33.2 “Features”: Added text: Software support for AVB feature is available from
NXP Professional Services. See nxp.com for more details.
•Added text: USB on-chip drivers are provided via the USB Stack in SDK and LPCOpen software
packages to Section 38.1 “How to read this chapter”.
•Updated Table 939 “Power API calls”.
•Updated Section 40.4.1 “POWER_SetVoltageForFreq”. and Section 40.4.3
“CLOCK_SetupFROClocking”.
•Updated Table 942 “Chip_POWER_EnterPowerMode routine” and Table 943
“Chip_POWER_SetFROHFRate routine”.
•Updated Section 40.4.2.2 “Param1: peripherals”.
•Added a remark to Section 41.4.5.4 “ISP Write to RAM” and Section 41.4.5.5 “ISP Read Memory”.
•Deleted EEPROM from Section 41.4.5.7 “ISP Copy RAM to flash”.
•Updated Section 4.6.4.1 “PLL Features”: Removed 6 kHz to 1.5 MHz Watchdog Oscillator.
1.0 20161221 Initial revision. LPC54S60x/LPC5460x User manual.
Revision history …continued
Rev Date Description

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1.1 Introduction
The LPC546xx is a family of ARM Cortex-M4 based microcontrollers for embedded
applications featuring a rich peripheral set with very low power consumption and
enhanced debug features.
The ARM Cortex-M4 is a 32-bit core that offers system enhancements such as low power
consumption, enhanced debug features, and a high level of support block integration. The
ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture with
separate local instruction and data buses as well as a third bus for peripherals, and
includes an internal prefetch unit that supports speculative branching. The ARM
Cortex-M4 supports single-cycle digital signal processing and SIMD instructions. A
hardware floating-point processor is integrated into the core.
The LPC546xx family includes up to 512 KB of flash, 200 KB of on-chip SRAM, up to 16
kB of EEPROM memory, a quad SPI Flash Interface (SPIFI) for expanding program
memory, one high-speed and one full-speed USB host and device controller, Ethernet
AVB, LCD controller, Smart Card Interfaces, SD/MMC, CAN FD, an External Memory
Controller (EMC), a DMIC subsystem with PDM microphone interface and I2S, five
general-purpose timers, SCTimer/PWM, RTC/alarm timer, Multi-Rate Timer (MRT), a
Windowed Watchdog Timer (WWDT), ten flexible serial communication peripherals
(USART, SPI, I2S, I2C interface), 12-bit 5.0 Msamples/sec ADC, temperature sensor.
1.2 Features
•ARM Cortex-M4 CPU:
–ARM Cortex-M4 processor, running at frequencies of up to 180 MHz.
–Built-in Memory Protection Unit (MPU) supporting eight regions.
–Built-in Nested Vectored Interrupt Controller (NVIC).
–Hardware Floating Point Unit (FPU).
–Non-maskable Interrupt (NMI) input.
–Serial Wire Debug; includes serial wire trace (SWO), ETM Trace, eight (6 + 2)
breakpoints, four watchpoints, and a debug timestamp counter.
–System tick timer.
•On-Chip memory:
–Up to 512 KB on-chip flash program memory with flash accelerator and 256 byte
page erase and write.
–Up to 200 KB total SRAM consisting of 160 kB contiguous main SRAM and an
additional 32 kB SRAM on the I&D buses. 8 kB of SRAM bank intended for USB
traffic.
–16 kB of EEPROM.
UM10912
Chapter 1: LPC546xx Introductory information
Rev. 1.7 — 14 April 2017 User manual

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Chapter 1: LPC546xx Introductory information
•ROM API support:
–Flash In-Application Programming (IAP) and In-System Programming (ISP).
–ROM-based USB drivers (HID, CDC, MSC, and DFU). Supports flash updates via
USB.
–Supports booting from valid user code in flash, USART, SPI, and I2C.
–Legacy, Single, and Dual image boot.
–OTP API for programming OTP memory.
–Random Number Generator (RNG) API.
•Clock generation:
–Crystal oscillator with an operating range of 1 MHz to 25 MHz.
–Internal Free Running Oscillator (FRO) with a high-frequency of 96 MHz output,
medium-frequency of 48 MHz output, and a low-frequency of 12 MHz output,
factory trimmed for accuracy. The FRO output can optionally be used as a system
clock.
–Independent Watchdog Oscillator (WDOSC) with a frequency range of 6 kHz to 1.5
MHz.
–System PLL allows CPU operation up to the maximum CPU rate and can run from
the main oscillator, the internal FRO, the watchdog oscillator or the 32 KHz RTC
oscillator.
–Two additional PLLs for USB clock and audio subsystem.
–Independent clocks for the SPIFI interface, ADC, USBs, and the audio subsystem.
–Clock output function with divider.
–Frequency measurement unit for measuring the frequency of on-chip or off-chip
clock signal.
•Serial interfaces:
–Ten Flexcomm Interface serial peripherals. Each Flexcomm Interface can be
selected by software to be a USART, SPI, or I2C interface. Two Flexcomm
Interfaces also include an I2S interface. Each Flexcomm Interface includes a FIFO
buffer that supports USART, SPI, and I2S if supported by that Flexcomm Interface.
A variety of clocking options are available to each Flexcomm Interface and include
a shared fractional baud-rate generator.
–I2C-bus interfaces support Fast-mode and Fast-mode Plus with data rates of up to
1Mbit/s and with multiple address recognition and monitor mode. Two sets of true
I2C pads also support High Speed Mode (3.4 Mbit/s) as a slave. The slave function
is able to wake up the device from Deep-sleep and Power-down modes.
–Two ISO 7816 Smart Card Interfaces with DMA support.
–USB0 full-speed host/device controller with on-chip PHY and dedicated DMA
controller supporting crystal-less operation in device mode.
–USB1 high-speed host/device controller with on-chip high-speed PHY.
–SPIFI with XIP feature uses up to four data lines to access off-chip SPI/DSPI/QSPI
flash memory at a much higher rate than standard SPI or SSP interfaces.
–Ethernet MAC with MII/RMII interface with Audio Video Bridging (AVB) support and
dedicated DMA controller.
–Two CAN FD modules with dedicated DMA controller.

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Chapter 1: LPC546xx Introductory information
•Digital peripherals:
–DMA controller with 30 channels and up to 24 programmable request/trigger
sources and able to access all memories and DMA-capable peripherals.
–LCD Controller supporting both Super-Twisted Nematic (STN) and Thin-Film
Transistor (TFT) displays. It has a dedicated DMA controller, selectable display
resolution (up to 1024 x 768 pixels), and supports up to 24-bit true-color mode.
–External Memory Controller (EMC) provides support for asynchronous static
memory devices such as RAM, ROM and flash, in addition to dynamic memories
such as single data rate SDRAM with an SDRAM clock of up to 100 MHz.
–Secured digital input/output (SD/MMC) card interface with DMA support.
–CRC engine block can calculate a CRC on supplied data using one of three
standard polynomials with DMA support.
–Up to 171 General-Purpose Input/Output (GPIO) pins.
–GPIO registers are located on the AHB for fast access. The DMA supports GPIO
ports.
–Up to eight GPIOs can be selected as pin interrupts (PINT), triggered by rising,
falling or both input edges.
–Two GPIO grouped interrupts (GINT) enable an interrupt based on a logical
(AND/OR) combination of input states.
•Analog peripherals:
–12-bit, 12-channel, Analog-to-Digital Converter (ADC) supporting 5.0 Msamples/s.
The ADC supports two independent conversion sequences.
–Integrated temperature sensor connected to the ADC.
•Security features:
–Random number generator can be used to create keys with DMA support.
–enhanced Code Read Protection (eCRP) to protect user code.
–OTP memory for ECRP settings and user application specific data.
•DMIC subsystem includes a dual-channel PDM microphone interface with
decimators, filtering, and hardware voice activity detection. The processed output
data can be routed directly to an I2S interface if needed.
•Timers
–Five 32-bit general purpose timers/counters, with up to 4 capture inputs and 4
compare outputs, PWM mode, and external count input. Specific timer events can
be selected to generate DMA requests. The fifth timer does not have external pin
connections and may be used for internal timing operations.
–SCTimer/PWM with 8 input and 10 output functions (including capture and match).
Inputs and outputs can be routed to/from external pins and internally to/from
selected peripherals. Internally, the SCTimer/PWM supports 16 match/captures, 16
events, and 16 states.
–24-bit Multi-Rate Timer (MRT) module with four channels each capable of
generating repetitive interrupts at different, programmable frequencies.

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Chapter 1: LPC546xx Introductory information
–32-bit Real-time clock (RTC) with 1 s resolution running in the always-on power
domain. A timer in the RTC can be used for wake-up from all low power modes
including deep power-down, with 1 ms resolution. The RTC is clocked by the
32.768 kHz oscillator.
–Multiple-channel multi-rate 24-bit timer (MRT) for repetitive interrupt generation at
up to four programmable, fixed rates.
–Windowed Watchdog Timer (WWDT) with dedicated watchdog oscillator.
–Ultra-low power Micro-tick Timer, running from the Watchdog oscillator that can be
used to wake up the device from low power modes.
–Repetitive Interrupt Timer (RIT) for debug time-stamping and for general purpose
use.
•Power-saving modes and wake-up:
–Integrated PMU (Power Management Unit) to minimize power consumption.
–Reduced power modes: sleep, deep-sleep, power-down, and deep power-down.
–Wake-up from deep-sleep and power-down modes via activity on the USART, SPI,
and I2C peripherals when operating as slaves.
–Wake-up from sleep, deep-sleep, power-down, and deep power-down modes
using the RTC alarm.
–The Micro-tick Timer can wake-up the device from any reduced power mode by
using the watchdog oscillator when no other on-chip resources are running.
–Power-On Reset (POR).
–Brown-Out Detect (BOD) with separate thresholds for interrupt and forced reset.
•Single power supply 1.71 V to 3.6 V.
•JTAG boundary scan supported.
•128 bit unique device serial number for identification.
•Operating temperature range 40 °C to +105 °C.
•Available in TFBGA180 and LQFP208 packages.

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Chapter 1: LPC546xx Introductory information
1.3 Block diagram
Each Flexcomm Interface includes USART, SPI, and I2C functions. Flexcomm Interface 6
and 7 each also provide an I2S function.
Fig 1. Block diagram
DEBUG INTERFACE
ISP access
port
JTAG test and
boundary scan
interface ethernet
PHY interface LCD panel SDIO interface CAN interface
FS USB
bus or
transceiver
ARM CORTEX-M4
WITH FPU/MPU
D-code
bus system bus
I-code
bus
aaa-026740
GENERAL
PURPOSE
DMA
CONTROLLER
ETHERNET
10/100
MAC
+AVB
LCD
PANEL
INTERFACE
USB 2.0
HOST/
DEVICE
HD
SDIO CAN
FD
CAN
FD clocks
and
controls
internal
power
CLOCK GENERATION,
POWER CONTROL,
AND OTHER
SYSTEM FUNCTIONS
VOLTAGE REGULATOR
Xtalin Xtalout RST
CLK
OUT
SPIFI
ADC
inputs
D[31:0]
A[25:0]
control
GPIO
Vdd
HS USB
PHY
BOOT ROM
64 kB
SRAM
32 kB
SRAM
32 kB
SRAM
32 kB
SRAM
32 kB
12b ADC
12-CH
TEMP
SENSOR
POLYFUSE OTP
256 b
STATIC/DYNAMIC EXT
MEMORY CONTROLLER
HS USB
HOST
REGISTERS
FS USB
HOST
REGISTERS
USB RAM
INTERFACE
SRAM
8 kB
EEPROM
UP TO 16 kB
SPI FLASH
INTERFACE
SRAM
64 kB
FLASH
INTERFACE
AND
ACCELERATOR
FLASH
512 MB
HS USB
bus
HS GPIO
0-5
FS USB
DEVICE
REGISTERS
LCD
REGISTERS
DMA
REGISTERS
EMC
REGISTERS
SPIFI
REGISTERS
MULTILAYER
AHB MATRIX
SCTimer/
PWM FlexComms 0-4
-UARTs 0-4 - I2Cs 0-4
-SPI0s 0-4
CRC
ENGINE
HS USB
DEVICE
REGISTERS AUDIO SUBSYS
D-MIC,
DECIMATOR, ETC
ETHERNET
REGISTERS
CAN 1
REGISTERS
AHB TO
APB BRIDGE
AHB TO
APB BRIDGE
ASYNC AHB TO
APB BRIDGE
CAN 0
REGISTERS
SYSTEM CONTROL
APB slave group 0
SDIO
REGISTERS FlexComms 5-9
-UARTs 5-9
-SPI0s 5-9
-I2Cs 5-9 - I2Ss 0,1
I/O CONFIGURATION
Note:
- Orange shaded blocks support Gen. Purpose DMA.
- Yellow shaded blocks include dedicated DMA Ctrl.
GPIO GLOBAL INTRPTS (0, 1)
GPIO INTERRUPT CONTROL
PERIPH INPUT MUX SELECTS
2 x 32-BIT TIMERS (T0, 1)
PMU REGS (+BB, PVT)
APB slave group 1
32-BIT TIMERS (T2)
SYSTEM CONTROL (async regs)
APB slave group 2
2 x 32-BIT TIMERS (T3, 4)
OS TIMER
FLASH 0 REGISTERS
2 x SMARTCARDS
RANDOM NUMBER GEN
REAL TIME
CLOCK 32 kHz Osc
RTC ALARM RTC POWER
DOMAIN
DIVIDER
MULTI-RATE TIMER
EEPROM REGISTERS
OTP CONTROLLER
WATCHDOG
OSC WINDOWED WDT
MICRO TICK TIMER

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Chapter 1: LPC546xx Introductory information
1.4 Architectural overview
The ARM Cortex-M4 includes three AHB-Lite buses, one system bus and the I-code and
D-code buses. One bus is dedicated for instruction fetch (I-code), and one bus is
dedicated for data access (D-code). The use of two core buses allows for simultaneous
operations if concurrent operations target different devices.
A multi-layer AHB matrix connects the CPU buses and other bus masters to peripherals in
a flexible manner that optimizes performance by allowing peripherals on different slaves
ports of the matrix to be accessed simultaneously by different bus masters. More
information on the multilayer matrix can be found in Section 2.1.4. Connections in the
multilayer matrix are shown in Figure 1. Note that while the AHB bus itself supports word,
halfword, and byte accesses, not all AHB peripherals need or provide that support.
APB peripherals are connected to the AHB matrix via two APB buses using separate
slave ports from the multilayer AHB matrix. This allows for better performance by reducing
collisions between the CPU and the DMA controller, and also for peripherals on the
asynchronous bridge to have a fixed clock that does not track the system clock. Note that
APB, by definition, does not directly support byte or halfword accesses.
1.5 ARM Cortex-M4 processor
The Cortex-M4 is a general purpose 32-bit microprocessor, which offers high performance
and very low power consumption. The Cortex-M4 offers a Thumb-2 instruction set, low
interrupt latency, interruptible/continuable multiple load and store instructions, automatic
state save and restore for interrupts, tightly integrated interrupt controller, multiple core
buses capable of simultaneous accesses, and a floating point unit.
A 3-stage pipeline is employed so that all parts of the processing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.
Information about Cortex-M4 configuration options can be found in Chapter 50.
1.6 On-chip flash memory system
The LPC546xx contains up to 512 kB of on-chip flash memory. A flash memory
accelerator maximizes performance for CPU accesses. This memory may be used for
both code and data storage. Programming of the flash memory may be accomplished in
several ways. It may be programmed In System via the serial port. The application
program may also erase and/or program the flash while the application is running,
allowing a great degree of flexibility for data storage field firmware upgrades, etc.
1.7 On-chip Static RAM
The LPC546xx contains up to 200 kB of on-chip static RAM. 8 kB of SRAM is intended for
the use by high-speed USB host/device peripherals. There are 6 banks of SRAM and
each bank is placed at a separate slave port. This architecture allows the possibility for
CPU and DMA accesses to be separated in such a way that there are few or no delays for
the bus masters. It also allows separation of data for different peripherals functions, in