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CircuitDescription
2-4
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Moreover,theregistersoftheFMsynthesizercan beoperated directlyfor real timesound generation,allowing,for
example,utilization ofvarious sound effectswhen using thegamesoftwareinstalledintheportabletelephone.
YMU762Cincludesaspeakeramplifierwith high rippleremovalratewhosemaximumoutput is550mW(SPVDD=3.6V).
Thedevice isalsoequippedwithconventionalfunction including avibratorand a circuit forcontrolling LEDs
synchronouswithmusic.
Fortheheadphone,it isprovidedwithastereophonicoutput terminal.
Forthepurposeofenabling YMU762Cto demonstrateitsfull capabilities,Yamahapurposeto use"SMAF:Syntheticmusic
MobileApplication Format"asadatadistribution format that iscompatiblewithmultimedia.Since theSMAFtakesa
structurethatsetsimportance on thesynchronization betweensound and images,variouscontentscan bewrittenintoit
including incoming call melody withwordsthatcan beusedfortraining karaoke,and commercialchannel thatcombines
texts,imagesand sounds,and others.ThehardwaresequencerofYMU762Cdirectlyinterpretsand playsblocksrelevant
tosynthesis(playing music and reproducing ADPCMwithFMsynthesizer) thatareincludedin datadistributedinSMAF.
8.Memory
SignalsintheOM6359 enabletwomemories.They useonly onevolt supply voltage,VDD3inthePCF50601.This
systemusesSamsung'smemory,KBB06A500M-T402.It isconsisted of128MbitsflashNORmemoryand 128Mbits
flashNAND memoryand 64MbitsSCRAM.Ithas16 bit dataline,HD[0~15]whichisconnectedtoOM6359 and
MV317S.Ithas26 bit address lines,HA[1~26].CS_NAND and NCSRAMsignalsare chipselect.Writing process,
HWR_Nislowand it enableswriting process toflashmemoryand SRAM.During reading process,HRD_Nislowand
it enablesreading process toflashmemoryand SRAM.EachchipselectsignalsintheOM6359 selectmemoryamong 2
flashmemoryand SCRAM.Reading orwriting procedureisprocessedafterHWR_NorHRD_Nisenabled.Memories
usereset,whichisVDD3 delayfromPCF50601.HA[25]signalenableslowerbyteofSRAMand HA[26]signalenables
higherbyteofSRAM.
9.OM6359
OM6359 isconsisted ofARMcore and DSP core.Ithas8x1Kwordon-chip program/dataRAM,55 Kwords
on-chip programROMintheDSP.Ithas4K*32bitsROMand 2K*32bitsRAMintheARMcore.DSP isconsisted
ofKBS,JTAG,EMIand UART.ARMcoreisconsisted ofEMI,PIC(ProgrammableInterruptController),
reset/power/clock unit,DMAcontroller,TIC(TestInterface Controller),peripheralbridge,PPI,SSI(SynchronousSerial
Interface),ACC(Asynchronouscommunicationscontrollers),timer,ADC,RTC(Real-TimeClock)and keyboardinterface.
KBIO(0:7),address linesofDSP core and HD[0~15].HA[1~26],address linesofARMcore and HD[0~15],datalinesof
ARMcore are connectedtomemory,YMU762C.MV317S(CameraDSP Chip)controlsthe communication betweenARM
core and DSP core.
CS_NAND,NCSRAM,NCSFLASHintheARMcore are connectedtoeachmemory.HWR_Nand HRD_Ncontrol the
process ofmemory.ExternalIRQ(InterruptReQuest)signalsfromeach units,suchas,PMUneedthe compatibleprocess.
KBIO[0~7] receivethestatusfromkeyand RXD0/TXD0areusedforthe communication using datalink
cable(DEBUG_DTR/RTS/TXD/RXD/CTS/DSR).
Ithas JTAG controlpins(TDI/TDO/TCK) forARMcore and DSP core.Itreceives13MHz clockinCKIpinfrom
externalTCXO.ADC(Analog toDigitalConvertor) partreceivesthestatusoftemperature,batterytype and battery voltage.