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CircuitDescription
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5.Multi-media processorMA55141
MA55141 isan LSI, whichisdesigned on 3GPP 3G-324MStandardforavideo telephone system.
Since protocolsoftwareisexternal,MA55141 can run with anotherprotocol likeH.323 by changing its software.
MA55141 hasARM9CPU,sosupportsmorevariousapplication.
Feature
-Based on 3GPP 3G-324Mstandard
-Video MPEG-4(simple profilelevel1)orH263 (baseline)
-AudioAMR,G723.1,MP3 orAAC(programdownloadable)
-Multiplexing H.223 (Level0,1,2,processed byCPU with assistanthardware)
-ControlH.245 (Processed all byCPU)
-Built-in 32bitRISC CPU(ARM926EJ)forcontrol.(Max133MHz, I-cache 16KB,D-cache 8KB,MMUand JAVA
accelerator (Jazelle)included.)
-Built-in 16bitDSP foraudioCODEC
-Built-inSD/MMC/MemoryStick I/F
-Video inputRec601/656 YUV=4:2:2,8 bit I/F
-Video outputRec601 YUV=4:2:2(8bit)/RGB18bit
Built-inPicture-In-PictureImage Displaying Functions
Built-inOnScreen Display(OSD)Functionswith alpha blending
-Video CODEC
Encoding and decoding :QCIF40fps,CIF10fps
Encoding only:QCIF68fps,CIF17fps
Decoding only:QCIF96fps,CIF24fps
Deblocking filterisbuilt-in.
Maxoutputimage size:2032×2032
-Programon SDRAMisexecutablewithoutROM(optional).
-Powersupply
VDDI1=1.425Vto 1.65V(Forinternalcircuit. Please poweroff during stand-by)
VDDI2=VDDI1(Forinternalcircuit. Please provide during stand-by)
VDDP0,VDDP1=1.425Vto 1.65V(ForinternalPLL0 and PLL1)
VDDO,VDDOD=2.7Vto 3.0V(ForI/O)
-Maxoperating frequency CPUclock =133MHz
DSP clock =100MHz
SDRAMclock =100MHz
Video clock =SDRAMclock/2
6.MIC2211 (U604/U605)
ThisLDOisthe voltage source ofMultimedia part. The MIC2211 isa dual-outputLDOregulator.
The one ofdual is capable ofsourcing 150mA,whilethe anotherone can supplyup to 300mA.
Idealforbatteryoperated applications, the MIC2211 offers1%accuracy,extremelylowdropoutvoltage (80mV@
100mA),and extremelylowground current(only48mAtotal).Equipped withTTLlogic compatible enable pins, the
MIC2211 can be putinto a zero-off-mode currentstate,drawing no currentwhen disabled.Separate enable pins
allowindividualcontrolofeach outputvoltage.