Semtech EB-GS2971 User manual

EB-GS2971
Evaluation Board User Guide
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Proprietary & Confidential
GS2971
EB-GS2971
Evaluation Board User Guide
52169 - 2 June 2012
www.semtech.com

EB-GS2971
Evaluation Board User Guide
52169 - 2 June 2012
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Contents
Overview ..............................................................................................................................................................3
1. Evaluation Board User Guide .................................................................................................................... 4
1.1 Power ....................................................................................................................................................5
1.2 SDI Input (J4) ......................................................................................................................................6
1.3 Switch Settings (SW2) ......................................................................................................................6
1.4 Outputs ................................................................................................................................................7
1.4.1 SDI Loop-Through (J5).........................................................................................................7
1.4.2 Audio Output (J23 and BNCs J19-J22) ...........................................................................7
1.4.3 Parallel Video Output (J16 and J17)................................................................................7
1.5 JTAG/GSPI Header (JP1) .................................................................................................................8
1.6 Lock and Data Error Status ............................................................................................................8
1.7 Modes of Operation .........................................................................................................................8
2. Schematics .......................................................................................................................................................9
2.1 Top Level Schematic ........................................................................................................................9
2.2 Cable Driver Schematic ............................................................................................................... 10
2.3 GS2971 Schematic ......................................................................................................................... 11
2.4 Power and AES Drivers ............................................................................................................... 12
3. Board Layout................................................................................................................................................ 13
4. Bill of Materials............................................................................................................................................ 19
Version ECR Date Changes and / or Modifications
2 158224 June 2012 Added a row in Table 4-1: Bill of Materials.
1 157183 November 2011 Updated Figure 3-2, Figure 3-3, Figure 3-4
and Figure 3-5 in the Board Layout section.
0 151494 March 2009 New document.

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Overview
Together with the EB-GS2971 Evaluation Board, this document serves as a guide for
evaluating the GS2971; a Gennum 3Gb/s, HD, SD SDI Receiver, with integrated
equalizer. This document contains four main sections:
1. Evaluation Board User Guide.
2. Evaluation Board Schematics.
3. Evaluation Board Layout.
4. Evaluation Board Bill of Materials
The figure below shows a block diagram of the features and the functions of the
EB-GS2971.
The board includes a power supply, a 3G-SDI input, a 3G-SDI loop-through output, a
GS2971 Receiver, a parallel video output connector, an audio output with four BNCs for
AES audio, a four-pin header for serial audio, a JTAG/GSPI header, a 27MHz crystal, a
DIP switch and some status indication LEDs.
The GS2971 will automatically detect the input signal as SD-SDI, HD-SDI or 3G-SDI. The
input format may also be configured to DVB-ASI or Data-Through mode manually,
through a DIP switch. The deserialized video is available on the parallel output
connector (J16). The extracted audio is available as serial audio or AES on an audio
header (J23), or as buffered AES only audio on the BNC connectors (J19-J22). A serial
digital loop-through output is also available.
The EB-GS2971 also provides a JTAG interface and access to the GS2971’s internal
registers via GSPI. A GSPI dongle is included in the kit, to communicate with the GS2971
through a USB connection.The GSPI dongle has the provision to control and monitor an
additional EB2972 board connected to the EB-GS2971.
Block Diagram of the EB-GS2971
GS2971
(Receiver)
Audio
O/P
Parallel
Video
O/P
3G-SDI
Loop-Through
3G-SDI I/P
8-ch Audio
20-bit Video
FVH
DIP Switch
LEDs
(Lock; Data Error)
Audio Clocks
CD
(GS2978)
Power
AES
PCLK
Audio
Header
GSPI/JTAG
Header
GSPI/5V

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1. Evaluation Board User Guide
Figure 1-1 shows the inputs, outputs and power connections for the EB-GS2971.
Figure 1-1: GS2971 Evaluation Board (EB-GS2971)
SDI Input
(J4)
SDI Loop-Through
(J5)
CD O/P Jumper
(JP4)
AES Audio Outputs (J19 - J22)
Parallel Video Output
(J16)
GSPI
(J18)
H, V & F TimingSignals
(J17)
1.8V/3.3V Jumper
(JP7)
Power
(J24)
Power
(J100)
Power Selection Switch
(SW100)
DIP Switch
(SW2)
Serial Audio Output
(J23)
Power Status
LED (D11)
Lock Status
Indicator
(U12)
Data Error
Status
Indicator
(U13)

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1.1 Power
The EB-GS2971 requires a single +5V DC power supply. The board can be powered
through either J24 or J100. Additionally, the board can powered through J18 from an
EB-GS2972 or FPGA board.
Figure 1-2: Power Supply
Switch SW100 allows the user to select three different voltages: 5V Ext, 5V EB and 3.3V
FPGA. It is important to note that if you are interfacing with an FPGA, you must select
3.3V FPGA.
NOTE 1: If you have accidently selected 3.3V FPGA and connect to a EB-GS2972
Serializer board, protection* will turn on.
Figure 1-3: Power Selection Switch
*The EB-GS2971 has features to protect the GS2971. A fuse (F101) will trip when the
Zener Diodes (D100, D101) turn on.
NOTE 2: If the fuse trips, it will recover in approximately 1 hour, with a resistance of 1Ω.
Figure 1-4: Power Protection
LED (D11) indicates the power on/off state of the board.
Through the use of jumper JP7, the GS2971 I/O voltage can be selected as either 1.8V or
3.3V.
If the EB-GS2971 and the EB-GS2972 are connected together, one supply will power
both boards. Therefore, the +5V DC power is only required on either the EB-GS2971 or
the EB-GS2972.
5V
J24
5V Input
GND
VCC_5V_In
3
2
1
J100
PJ-202AH
C36
EEV-FK1C221XP
5V
1
2
3
4
5
6
7
8
SW100
SW SLIDE-DP3T
VCC_3.3V
VCC_3.3V_reg
VCC_3.3V
VCC_MB_F
VCC_5V_In
VCC_5V
VCC_MB
VCC_LED
5V Ext
5V EB
3.3V FPGA
GND
D101
3.6V
VCC_MB
D100
3.6V
VCC_3.3V
F101
0603L035
C102
470u
VCC_MB VCC_MB_F
GND
C103
22u

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1.2 SDI Input (J4)
The EB-GS2971 includes a single SDI input.
1.3 Switch Settings (SW2)
A DIP switch (SW2) is populated on the EB-GS2971, with each bit labelled on the
silk-screen. This switch is used to set the operating modes of the GS2971. The signal can
be set HIGH by placing the switch to the ‘1’ position (Closed).
NOTE: Some signals are active LOW, so you will need to switch the bit ‘OFF’ to activate
the signal.
Refer to Table 1-1 below for definitions of each bit.
Table 1-1: SW2 Settings
Bit Name Description
TIM861Connected to the GS2971 TIM_861 pin. Used to select CEA-861 timing mode.
When TIM_861 is HIGH, the device outputs CEA 861 timing signals (HSYNC/VSYNC/DE) instead of H:V:F digital
timing signals.
SMPTE_BYPASSbConnected to the GS2971 SMPTE_BYPASS pin. Used to enable/disable all forms of encoding/decoding,
descrambling, audio and ANCdata detection and extraction and error detection and correction.
When the AUTO/MAN bit in the Host Interface register is HIGH (Default), this pin is an OUTPUT. SMPTE_BYPASS is
HIGH when the device locks to a SMPTE compliant input. SMPTE_BYPASS is LOW under all other conditions.
When the AUTO/MAN bit in the Host Interface register is LOW, this pin is an INPUT. No SMPTE scrambling takes
place, and none of the I/O processing features of the device are available when SMPTE_BYPASS is set LOW.
When SMPTE_BYPASS is set HIGH, the device carries out SMPTE descrambling and I/O processing.
When SMPTE_BYPASS and DVB_ASI are both set LOW, the device operates in Data-Through mode.
DVB_ASIConnected to the GS2971 DVB_ASI pin. Used to enable/disable DVB-ASI data decoding in manual mode.
When the AUTO/MAN bit in the Host Interface is LOW, this pin is an input and when set HIGH the device will
carry out DVB_ASI data extraction and processing. The SMPTE_BYPASS pin must be set LOW.
When SMPTE_BYPASS and DVB_ASI are both set LOW, the device operates in Data-Through mode.
When the AUTO/MAN bit in the Host Interface is HIGH (Default), DVB-ASI input is not supported.
AUDIO_EN/DISbConnected to the GS2971 AUDIO_EN/DISpin. Enables or disables audio extraction.
IOPROC_EN/DISbConnected to the GS2971 IOPROC_EN/DISpin. Used to enable or disable I/O processing features.
When IOPROC_EN/DISis HIGH, the I/O processing features of the device are enabled.
When IOPROC_EN/DISis LOW, the I/O processing features of the device are disabled, and the latency of the
device is LOW. Please refer to the Data Sheet for more information.
20BIT/10BITb Connected to the GS2971 20bit/10bit pin. Used to select the output bus width. (HIGH = 20bit, LOW = 10bit)
SDO_EN/DISbConnected to the GS2971 SDO_EN/DISpin. Used to enable/disable the serial digital output stage.
When the SDO_EN/DISis LOW, the serial digital output signals, SDO and SDO, remain static.
When connected to logic HIGH, the serial digital output signals, SDO and SDO, are enabled.
The SDO and SDO outputs will also be disabled when the RESET pin is LOW.
RC_BYPb Connected to the GS2971 RC_BYP pin. When this pin is LOW, the serial digital output is the buffered version of
the input serial data.
When this pin is HIGH, the serial digital output is the reclocked version of the input serial data.

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1.4 Outputs
1.4.1 SDI Loop-Through (J5)
A relocked or non-relocked buffered version of the input stream is available on the
serial loop-through output (J5). It is designed to be SMPTE compliant for voltage level,
rise/fall time and return loss at three rates (SD, HD and 3G) using the compensation
network. The GS2978 Cable Driver is necessary to guarantee return loss specification.
The GS2978 should be set to SD or HD mode; use jumper JP4 to select the mode. See
Table 1-2 below.
If the SDI loop-through is not required, disable the SDO through the SDO_EN/DIS DIP
switch setting (SW2). Doing this will also disable the GS2978 Cable Driver.
1.4.2 Audio Output (J23 and BNCs J19-J22)
The extracted 8-channel audio, together with the Audio Master Clock generated by the
GS2971, is available on a 10-pin header (J23).
For AES mode, AES-encoded CMOS-level signals are distributed through line drivers,
and supplied to four BNC connectors (J19, J20, J21 and J22).
An audio output board can be connected to Serial Audio Output header (J23).
1.4.3 Parallel Video Output (J16 and J17)
Parallel video data with the PCLK is available on a 48-pin connector (J16) and timing
signals H, V and F are connected to a 10-pin connector (J17). This is a standard Gennum
parallel interface, compatible with all Gennum evaluation boards.
SW_EN Connected to the GS2971 SW_EN pin. Used to enable switch-line locking. Please refer to the Data Sheet for more
information.
STANDBY Connected to the GS2971 STANDBY pin. When this pin is set HIGH, the device power is reduced, and placed into
Standby mode.
Table 1-1: SW2 Settings (Continued)
Bit Name Description
Table 1-2: GS2978 Cable Driver format
JP4 Position Status
Open HD/3G
Closed SD

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1.5 JTAG/GSPI Header (JP1)
The GS2971 contains a set of internal status and configuration registers. These registers
are available to the host via the GS2971’s GSPI pins. Access to the applicable pins on the
GS2971 is provided using the JTAG/GSPI header.
A GSPI dongle is provided for communication to the GSPI interface. If you have the
EB-GS2971 and an EB-GS2972 connected together, only one GSPI dongle is required,
and can be connected to either of the boards.
1.6 Lock and Data Error Status
LED U12 indicates the lock status of the GS2971, and LED U13 indicates data error. Both
are bi-colour devices. See Table 1-3 below.
1.7 Modes of Operation
The GS2971 supports four distinct modes of operation that can be set through the DIP
switch or by programming internal registers through the GSPI. These modes are: SMPTE
mode, Data-Through mode, DVB-ASI mode and Standby mode.
The GS2971 can automatically detect the format of the incoming signal when
AUTO/MAN = HIGH. If the format of the incoming signal is not recognized, the GS2971
defaults into SMPTE Bypass mode. Alternatively, the device may be forced into any of
the four modes through the Host Interface (Address 024h).
In SMPTE mode, the GS2971 performs full SMPTE processing, and features a number of
signal integrity checks and measurement capabilities.
In DVB-ASI mode, 8b/10b decoding is applied to the received data stream.
In SMPTE Bypass mode, all forms of SMPTE and DVB-ASI decoding are disabled, and the
device can be used as a simple serial-to-parallel converter without incurring the latency
penalties associated with SMPTE or DVB-ASI mode.
The device can also operate in a lower power Standby mode. In this mode, no signal is
generated at the output.
The DIP switch (SW2) corresponds directly to pins on the GS2971. Refer to the GS2971
Data Sheet for a more detailed explanation of the modes of operation.
Table 1-3: Lock and Data Error Status
LED Green Red
U12 (Lock Status) Locked Unlocked
U13 (Data Error Status) No Error Detected Error Detected

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2. Schematics 2.1 Top Level Schematic Figure 2-1: Top Level Schematic
GND GND
S1
B3S-1002P
RESET
GND GND
PCLK
MA L E: T OP- SIDE
MA L E: T OP- SIDE
2 4 6 8
10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46
48
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47
J16
TMMH-124-01-F-D-RA-ES
2 4 6 8
10
1 3 5 7 9
J17
TMMH-105-01-F-D-RA
R84
1.15K
HHVF0 FHVF2 VHVF1
VID_DAT_Out3 VID_DAT_Out0 VID_DAT_Out2 VID_DAT_Out1
SERIA L AUDIO
VID_DAT_Out5 VID_DAT_Out7 VID_DAT_Out4 VID_DAT_Out9 VID_DAT_Out8 VID_DAT_Out6 VID_DAT_Out12 VID_DAT_Out11 VID_DAT_Out15 VID_DAT_Out16 VID_DAT_Out10 VID_DAT_Out17 VID_DAT_Out13 VID_DAT_Out14 VID_DAT_Out19 VID_DAT_Out18
GND
GND
RESET
AMCLK
ACLK WCLK
12 34 56 78
9 10
J23
TSW-105-07-L-D
AOUT_3/4
ACLK
WCLK
AOUT_1/2 AOUT_5/6
AOUT_7/8
GND
SERIAL AUDIO OUT
1
3
2
J4
UCBBJE20-1
SDI INPUT
Pin _ctrl0JTAG/HOSTb
C91
0.1u
VCC_MB
CS1
2 4 6 8
10
1 3 5 7 9
J18
TMMH-105-01-F-D-RA
CS3 CS2
CS0
A_GND
1
3
2
J5
UCBBJE20-1
SDI OUT
CD CD
SDO
SDI OUT
GND
JTAG/ H OSTb
CS2 CS1
R8910K
VCC_3.3V
R9010K R8810K
AUDIO_Out[6:0]
IO_VDD
GND
1
2
J22
BCJ-FPLV01
1
2
J19
BCJ-FPLV01
1
2
J21
BCJ-FPLV01
1
2
J20
BCJ-FPLV01
AES Ch 3_4
AES Ch 1_2
AES Ch 7_8
AES Ch 5_6
GND
Power andAES driv ers
Power andAES driv ers
AOUT_1/2 AOUT_3/4 AOUT_5/6 AOUT_7/8
AES Ch 1_2 AES Ch 3_4 AES Ch 5_6 AES Ch 7_8
GND
GND
GND
GSPI[3:0]
IO_VDD
IO_VDD
GSPI
GND
12 34 56 78
910
JP1
TSW-105-07-L-D
VCC_3.3V
AUDIO_Out1
GND
IO_VDD
GSPI1
SDOUT
RESET
HVF[2:0]
Lock
CS3
IO_VDD
GSPI0
GSPI2
AUDIO_Out0
R8710K
SDIN
GS2971
VID_DAT_Out[19:0]
PCLK
HVF[2:0]
AUDIO_Out [6: 0]
Lock
Data Error
SDO RESET
GSPI[3:0]
Pin _ctrl[10:0]
SDI Input
Data Error
R93
10K
VCCA 1
VCCB 10
A0 2 A1 3
TR0 4 TR1 6
GND
5
OEb
7
B0
9
B1
8
U24 FXL2TD245
AUDIO_Out3
GND
Pin _ctrl[10:0]
AUDIO_Out2
VCC_3.3V
SCLK
AUDIO_Out6
VCC_3.3V
T/R b0
2
A0
3
A1
4
A2
5
A3
6
T/R b3
7T/R b210
B3 11 B2 12 B1 13 B0 14
T/R b115
VCCA
1
VCCB
16
GND
8
OEb
9
U16
FXL4TD245
VID_DAT_Out[19: 0]
RST
AUDIO_Out5
SMPTE_BYPASSbPin _ctrl9 STANDBY Pin _ctrl1 RC_BY bPin _ctrl3
ST A NDBY
IO_VDD
GND
SW2 SW DIP-10/SM
TIM 861 SW_EN SMPTE_BYPASSb AUDIO_EN/DISb DV B_A SI
AUDIO_Out4
SDO_EN/DISb 20BIT/10BITb IOPROC_EN/DISb RC_BYb
SDO_EN/DISbPin _ctrl4 20BIT/10BITbPin _ctrl5
CS0
R36
10K
R35
10K
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
RN3 742C163103
AUDIO_EN/DISbPin _ctrl7
GSPI3
GND
IOPROC_EN/DISbPin _ctrl6 DVB_ASI Pin _ctrl8 TIM861 Pin _ctrl10
GND
SW_EN Pin _ctrl2
GND 2
RESET
1
MR
3
Vcc 5
WDI
4
U1
MAX6823V
VCC_3.3V
GND
A1 green
1
A2 red
2
K1 3 K2 4
U13
HSMF-C165
Data Error
Lock
A1 green
1
A2 red
2
K1 3 K2 4
U12
HSMF-C165
GND
VCC_3.3V
R86 75R
R85 75R
SDO
SDO
SD_EN/DIS SD_EN/DIS
A_GND
IO_VDD
AOUT_7/8
AOUT_5/6
AOUT_3/4
AOUT_1/2

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2.2 Cable Driver Schematic
Figure 2-2: Cable Driver Schematic
R41
75R
R92
10K
R43
75R
C48
10n
75-ohm traces
A_GND
C52 4u7
JP4
R48
49R9 R49
49R9
C57
10n
SDI
1
SDI
2
NC
5
GND
3
DISABLE
6
NC
14
SD/HD 10
TAB NC
8
SDO 11
SDO 12
NC
15
NC
13
NC
7
RSET
4
VCC 9
NC
16
U7
GS2978
A_GND
C50 4u7
SD closed
HD open
A_GND
LOOP-THROUGH
L4 5n6
R47 75R
R40
750R
+3.3V
R44 75R
C47
10n
+3.3V
C20
10n
R94
0R
C22
1u
C23
10n
R9
0R
C21
1u
A_GND
VCC_3.3V
+3.3V
GND
CD Power Decoupling& Filtering
CD
SDO
SDI OUT
SD_EN/DIS
SD_EN/DIS
A_GND
SDO SDO
SDO
A_GND
A_GND

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2.3 GS2971 Schematic Figure 2-3: GS2971 Schematic
AUDIO_EN/DISbPin _ctrl7
TP18
Y1 CS10-27. 000M
C43 16p C44 16p
IOPROC_EN /DI SbPin _ctrl6
A_GND
C18
22u
VID_DAT_Out4
JTAG/HOSTbPin _ctrl0 20BIT/10BITbPin _ctrl5
RESET
A_GND
C9
1u
12. Impedance controlledsignals (refer to PCB layout guide).
Float ingor +3.3V or GND
SDO_EN/D ISbPin _ctrl4 RESET
8. Lable the connectors, LEDs, DIP sw itches andjumpers. Lable s ome critical signals on the connectors;
RC_BY bPin _ctrl3
VID_DAT_Out18 VID_DAT_Out3
R21 DNP
FW_ENPin _ctrl2
A_GND
STANDBYPin _ctrl1
VID_DAT_Out[19:0]
A_GND
R7
105R
VID_DAT_Out17
IO_VDD
+1.2VA
VID_DAT_Out2
4. SQT andTMM ser ies connectors are ratedfor 3A f rom 20C-80C, w ith operation temp range of -65-+125C
PCLK
R19
DNP
Close to GS2971
1 2 3 4 5 6 7 89
10 11 12 13 14 15 16
RN2 742C163220
HVF[2: 0]
VID_DAT_Out16
C101 470n
C100 470n
VID_DAT_Out1
+3.3VA
Data Error
AUDIO_Out [ 6:0]
VID_DAT_Out15
Pin _ctrl[10:0]
VBG
A1
LF
A2
LB_CONT
A3
VCO_VDD A4
STAT0 A5 STAT1 A6 STAT2 B5 STAT3 B6 STAT4 C5 STAT5 C6
IO_VDD A7
PCLK A8
DOUT0 K8 DOUT1 J8 DOUT2 K9 DOUT3 K10 DOUT4 J9 DOUT5 J10 DOUT6 H9 DOUT7 H10 DOUT8 F9 DOUT9 F10
DOUT10 E9 DOUT11 E10 DOUT12 C8 DOUT13 C10 DOUT14 C9 DOUT15 B10 DOUT16 B9 DOUT17 A10 DOUT18 A9 DOUT19 B8
A_VDD B1
PLL_VDD B2
A_TEST
B3
VCO_GND
B4
IO_GND
B7
SDI
C1
A_GND
C2
PLL_VDD C3
PLL_VDD C4
RESET
C7
SDI
D1
A_GND
D2
A_GND
D3
PLL_GND
D4
CORE_GND
D5
CORE_VDD D6
SW_EN
D7
JTAG/HOST
D8
IO_GND
D9
IO_VDD D10
SDI_VDD E1
A_GND
E3
PLL_GND
E4
CORE_GND
E5
CORE_VDD E6
SDOUT_TDO
E7
SDIN_TDI
E8
AGC+
F1
RSV
F2
A_GND
F3
PLL_GND
F4
CORE_GND
F5
CORE_VDD F6
CS_ TMS
F7 SCLK_TCK F8
AGC-
G1
A_GND
G2
RC_BY P
G3
CORE_GND
G4
CORE_GND
G5
CORE_VDD G6
SMPTE_BYPASS
G7
DVB_ASI
G8
IO_GND
G9
IO_VDD G10
BUF_VDD H1
BUF_GND
H2
AUDIO_EN/DIS
H3
WCLK H4
TIM_861
H5
XTA L _O U T
H6
20BIT/10BIT
H7 IOPROC_EN /DI S H8
SDO
J1
SDO_EN/D IS
J2
AOUT_1/2 J3
ACLK J4
AOUT_5/6 J5
XTA L 2
J6
IO_GND
J7
SDO K1
STANDBY
K2
AOUT_3/4 K3
AMCLK K4
AOUT_7/8 K5
XTA L 1
K6
IO_VDD K7
SDI_GND
E2
U5
GS2971
Close to GS2971
Lock
VID_DAT_Out0
WCLK AUDIO_Out 0
R37 22R ACLK AUDIO_Out 1 R38 22R
+1.2V
5. IO_ V DD can be +3.3V, w hich is s uppliedby this boardthrough a 1-ohm jumper, or dif f er en t
voltage suppliedby the output boardconnectedto it, in w hich case the 1-ohm jumper shall be removed;
R24 22R R25 22R
VID_DAT_Out14
10. Analogpow er andgroundisolation (refer to PCB layout guide).
9. Minimum of 3x trace w idth spacingf or DOUT1 0~1 9, PCLK;
11. Critital 3G signal layout (refer to PCB layout guide);
SCLKGSPI1 SDINGSPI2 SDOUTGSPI3 CS0GSPI0 Lock
+3.3VA
Data Error
C51 1u
R42 75R L3 6n2
R45
75R
R46
37R4
C49 1u
A_GND
VID_DAT_Out13 VID_DAT_Out11
GS2971 Power Decoupling& Filtering
VID_DAT_Out12 VID_DAT_Out10
1
2
3
JP7
TP7
7 . Us e BNC groundas the groundtest points;
VCC_1.8V
TP19
VID_DAT_Out9
+3.3VA
GSPI[3:0]
PCLK
R18 22R
C26
1u
TP20
13. Via size test points shouldbe as close as pos sible to the pins;
AOUT_3/4 AUDIO_Out 4 AOUT_1/2 AUDIO_Out 5
VID_DAT_Out8
6. The value of the serial resistors on video output por t w ill be determinedby boardsignal integrity test;
R16 22R R17 22R R14 22R FHVF2
VHVF1
HHVF0
GND
C25
1u
TP8
Lock
GND
AOUT_7/8 AUDIO_Out 2 AOUT_5/6 AUDIO_Out 3
1 2 3 4 5 6 7 89
10 11 12 13 14 15 16
RN1 742C163220
VID_DAT_Out7
C31 1u
C34 10n
C17
10n
C27
10n
C16
10n
C41 47n-470n
C15
10n
R12
0R
R10
0R
C30
10n
R2
0R
C14
10n
C29
10n
C8
10n
R91
0R
C24 10n
C33
10n
R11
0R
C13 10n
C35 10n
C12
10n
C32 10n
+1.2VA
C28
10n
C11
10n
A_GND
A_GND
VCC_3.3V
GND
GND
VCC_3.3V
+1.2V
GND
GND
+1.2VA +3.3VA
IO_VDD
+1.2V
R20 22R
TIM86 1Pin _ct rl10
VID_DAT_Out6
LB_CONT Settings:
VID_DAT_Out19
Data Error
R22 22R
SMPTE_BYPASSbPin _ctrl9
AMCLK AUDIO_Out 6
3. Pow er consumption: 2. DNP (Do Not Populate);
217 +1.2V +3.3V
75GS2970_1
Notes:
Device
0GS2978 51
SDI Input
C42 1u
1. This boardis GS2960/1 compatible;
217mATot a l 191mA
C10
1u
DVB_ASIPin _ctrl8
VID_DAT_Out5
SDO
SDO
SDO
SDO

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2.4 Power and AES Drivers
Figure 2-4: Power and AESDrivers Schematics
GND
C70 0.1u
C95 0.1u
C85
10n
C65 0.1u
C87
1u
5V
J24
5V Input
C92 0.1u
C39
33u
C40
22u
A
3
B
4
R5
GND
2
Vcc
1
110R
U19
SN65LVDT2
C93 0.1u
R57
240R
A
3
B
4
R5
GND
2
Vcc
1
110R
U20
SN65LVDT2
R96
49.9K
A
3
B
4
R5
GND
2
Vcc
1
110R
U18
SN65LVDT2
IN
8
SHDN
5
AGND
4PGND
6
SENSE 3
OUT 2
NC 1
NC 7
U4
LT3021ES8-1.2
R6
1.15K
PWR
VCCA
1
GND
2
A
3B4
DIR 5
VCCB 6
SN74LVC1T45DRLR
U15
PWRGD_3V3
C58 0.1u
C86
22u
AES AUDIO OUT
C94 0.1u
C63 0.1u
R3
3.57K
C3
22u
VCC_5V
IN
5
IN
6
IN
7
IN
8
BIAS
10
PG
9
OUT 1
OUT 18
OUT 19
OUT 20
NC 17
FB 16 EN
11
SS 15
GND
12
NC
13
NC
14
NC
2
NC
3
NC
4
Pad
U14
TPS74201_RGW
D11
LNJ311G8PRA
A
3
B
4
R5
GND
2
Vcc
1
110R
U17
SN65LVDT2
GND
GND
VCC_3.3V
GND
GND
GND
VCC_3.3V
GND
GND GND
GND
VCC_3.3V
GND GND
GND
VCC_3.3V
GND
VCC_5V_In
GNDGND
GND
VCC_3.3V_reg
VCC_5V
VCC_3.3V +1.2V
GND
GND
VCC_5V
GND
VCC_3.3V_reg
GND
D101
3.6V
VCC_MB
R100
240R
3.3V MB
D102
LNJ311G8PRA
GND
C84
0.1u
C88
33u
He at s in k
on copper
IN
8
SHDN
5
AGND
4PGND
6
SENSE 3
OUT 2
NC 1
NC 7
U22
LT3021ES8-1.8
500mA
VCC_3.3V VCC_1.8V
C90
1u
GND
GND
D100
3.6V
VCC_3.3V
VCC_3.3V
3
2
1
J100
PJ-202AH
1
2
3
4
5
6
7
8
SW100
SW SLIDE-DP3T
F101
0603L035
C102
470u
VCC_3.3V
VCC_MB
TP2
VCC_3.3V_reg
C36
EEV-FK1C221XP
VCC_3.3V
VCC_MB_F
VCC_MB_F
AOUT_1/2
VCC_5V_In
PWRGD_3V3
AOUT_3/4
VCC_5V
AOUT_5/6
VCC_MB
VCC_LED
AOUT_7/8
5V
5V Ext
5V EB
GND
3.3V FPGA
AES Ch 1_2
AES Ch 3_4
AES Ch 5_6
He at s in k
on copper
AES Ch 7_8
POWER SUPPLIES
500mA
C103
22u
+1.2V
AOUT_3/4
AOUT_5/6
AOUT_7/8
AOUT_1/2

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3. Board Layout
Figure 3-1: Layer 1 (Top Layer)

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Figure 3-2: Layer 2 (Ground)

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Figure 3-3: Layer 3 (Power)

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Figure 3-4: Layer 4 (Signal 1)

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Figure 3-5: Layer 5 (Signal 2)

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Figure 3-6: Layer 6(Bottom Layer)

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4. Bill of Materials
Table 4-1: Bill of Materials
Quantity Reference Part
5C3, C18, C40, C86, C103 22μF Capacitor (805)
5C8, C20, C23, C24, C30 10nF Capacitor (0603)
9C9, C10, C21, C22, C25, C26, C31, C87, C90 1μF Capacitor (0603)
18 C11, C12, C13, C14, C15, C16, C17, C27, C28,
C29, C32, C33, C34, C35, C47, C48, C57, C85
10nF Capacitor (0402)
1C36EEV-FK1C221XP
(CT-CAP/PANA_FK_D8)
2C39, C88 33μF Capacitor (1210)
1C41 47nF-470nF Capacitor (0402)
3C42, C49, C51 1μF Capacitor (0402)
2C43, C44 16pF Capacitor (0603)
2C50, C52 4.7μF Capacitor (0603)
10 C58, C63, C65, C70, C84, C91, C92, C93, C94,
C95
0.1μF Capacitor (0402)
2C100, C101 470nF Capacitor (0402)
2 D11, D102 LNJ311G8PRA (1206_LED)
2 D100, D101 CT-SMB_DO214AA
1 F101 0603L035 (CT-0603)
1JP1 TSW-105-07-L-D (BLKCON
.100/VH/TM2OE/W.200/10)
1 JP4 JUMPER (HEADER_.100_1X2)
1JP7 BLKCON
.100/VH/TM1SQ/W.100/3
2J4,J5 UCBBJE20-1 (BNC_EDGEMNT
_GHZ-POUR-2LYR-ER3.8)
1J16TMMH-124-01-F-D-RA-ES
(HEADER2MM_48_2X24)
2 J17, J18 TMMH-105-01-F-D-RA
(HEADER2MM_10_2X5)
4 J19, J20, J21, J22 BCJ-FPLV01 (BNC
_EDGEMNT_RIGHT_ANGLE)
1J23 TSW-105-07-L-D
(HEADER2MM_10_2X5)
1 J24 5V Input
(CON_WEID5MM_2_PWR)
1L3 6.2nH Inductor (0402)

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1L4 5.6nH Inductor (0402)
2 RN1, RN2 742C163220 (CT-742_16)
1 RN3 742C163103 (CT-742_16)
7 R2, R9, R10, R11, R12, R91, R94 0ΩResistor (0603)
1 R3 3.57kΩResistor (0603)
2R6, R84 1.15kΩResistor (0603)
1 R7 105ΩResistor (0603)
10 R14, R16, R17, R18, R20, R22, R24, R25, R37,
R38
22ΩResistor (0402)
7R35,R36, R87, R88, R89, R90, R93 10kΩResistor (0402)
1 R40 750ΩResistor (0402)
8 R41, R42, R43, R44, R45, R47, R85, R8675ΩResistor (0402)
1R4637.4ΩResistor (0402)
2 R48, R49 49.9ΩResistor (0402)
2 R57, R100 240ΩResistor (0603)
1 R92 10kΩResistor (0603)
1R9649.9kΩResistor (0603)
1SW2 Switch, DIP-10/SM (Through
Hole)
1SW100 Switch, SLIDE-DP3T
1S1B3S-1002P
6TP2, TP7, TP8, TP18, TP19, TP20 Via (CT-TP)
1U1 MAX6823V (SOT23-5)
1U4 MCP1725-1202E/SN (CT-SOIC_8)
1U5 GS2971 Receiver
(CT-BGA_100_11X11_1.00)
1U7 GS2978 Cable Driver
(CT-QFN_4MM_16/WSHLD)
2 U12, U13 HSMF-C165
1 U14 TPS74201_RGW (20-QFN)
1U15 SN74LVC1T45DBVR (SOT23-6)
1U16FXL4TD245 (DQFN-MLP016E)
4 U17, U18, U19, U20 SN65LVDT2 (SOT23-5)
1 U22 TPS77518D (CT-SOIC_8)
Table 4-1: Bill of Materials (Continued)
Quantity Reference Part