SiFive FE310-G002 User manual

SiFive FE310-G002 Manual
v19p05
© SiFive, Inc.

SiFive FE310-G002 Manual
Proprietary Notice
Copyright © 2019, SiFive Inc. All rights reserved.
Information in this document is provided “as is,” with all faults.
SiFive expressly disclaims all warranties, representations, and conditions of any kind, whether
express or implied, including, but not limited to, the implied warranties or conditions of mer-
chantability, fitness for a particular purpose and non-infringement.
SiFive does not assume any liability rising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation indirect, incidental, spe-
cial, exemplary, or consequential damages.
SiFive reserves the right to make changes without further notice to any products herein.
Release Information
Version Date Changes
v19p04 April 11, 2019 • Initial release
v19p05 May 08, 2019 • Correct UART1 pin assignment

Contents
1 Introduction .............................................................................................................. 8
1.1 F 310-G002 Overview ................................................................................................8
1.2 31 RISC‑V Core ..................................................................................................... 10
1.3 Interrupts ................................................................................................................. 10
1.4 On-Chip Memory System...........................................................................................11
1.5 Always-On (AON) Block ............................................................................................11
1.6 GPIO Complex ......................................................................................................... 11
1.7 Universal Asynchronous Receiver/Transmitter.............................................................11
1.8 Hardware Serial Peripheral Interface (SPI) ..................................................................11
1.9 Pulse Width Modulation.............................................................................................12
1.10 I²C ......................................................................................................................... 12
1.11 Debug Support ....................................................................................................... 12
2 List of Abbreviations and Terms .................................................................13
3 E31 RISC-V Core .................................................................................................. 15
3.1 Instruction Memory System........................................................................................15
3.1.1 I-Cache Reconfigurability ..................................................................................16
3.2 Instruction Fetch Unit ................................................................................................16
3.3 xecution Pipeline .................................................................................................... 16
3.4 Data Memory System................................................................................................17
3.5 Atomic Memory Operations........................................................................................17
3.6 Supported Modes ..................................................................................................... 18
3.7 Physical Memory Protection (PMP).............................................................................18
3.7.1 Functional Description ......................................................................................18
3.7.2 Region Locking ................................................................................................18
3.8 Hardware Performance Monitor..................................................................................19
4 emory ap ........................................................................................................... 21
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5 Boot Process.......................................................................................................... 23
5.1 Reset Vector............................................................................................................. 23
5.1.1 Mask ROM (MROM).........................................................................................24
5.1.2 One-Time Programmable (OTP) Memory ...........................................................24
5.1.3 Quad SPI Flash Controller (QSPI)......................................................................24
6 Clock Generation .................................................................................................25
6.1 Clock Generation Overview .......................................................................................25
6.2 PRCI Address Space Usage ......................................................................................26
6.3 Internal Trimmable Programmable 72 MHz Oscillator (HFROSC) ..................................26
6.4 xternal 16 MHz Crystal Oscillator (HFXOSC).............................................................27
6.5 Internal High-Frequency PLL (HFPLL) ........................................................................28
6.6 PLL Output Divider.................................................................................................... 30
6.7 Internal Programmable Low-Frequency Ring Oscillator (LFROSC) ................................31
6.8 Alternate Low-Frequency Clock (LFALTCLK)...............................................................32
6.9 Clock Summary ........................................................................................................ 32
7 Power odes.......................................................................................................... 33
7.1 Run Mode ................................................................................................................ 33
7.2 Wait Mode................................................................................................................ 33
7.3 Sleep Mode.............................................................................................................. 33
8 Interrupts.................................................................................................................. 35
8.1 Interrupt Concepts .................................................................................................... 35
8.2 Interrupt Operation.................................................................................................... 36
8.2.1 Interrupt ntry and xit .....................................................................................36
8.3 Interrupt Control Status Registers...............................................................................37
8.3.1 Machine Status Register (mstatus)..................................................................37
8.3.2 Machine Trap Vector (mtvec)............................................................................37
8.3.3 Machine Interrupt nable (mie).........................................................................39
8.3.4 Machine Interrupt Pending (mip).......................................................................39
8.3.5 Machine Cause (mcause).................................................................................39
8.4 Interrupt Priorities ..................................................................................................... 40
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8.5 Interrupt Latency....................................................................................................... 41
9 Core-Local Interruptor (CLINT).....................................................................42
9.1 CLINT Memory Map.................................................................................................. 42
9.2 MSIP Registers......................................................................................................... 42
9.3 Timer Registers ........................................................................................................ 43
10 Platform-Level Interrupt Controller (PLIC)...........................................44
10.1 Memory Map .......................................................................................................... 44
10.2 Interrupt Sources .................................................................................................... 45
10.3 Interrupt Priorities.................................................................................................... 46
10.4 Interrupt Pending Bits ..............................................................................................46
10.5 Interrupt nables..................................................................................................... 47
10.6 Priority Thresholds .................................................................................................. 48
10.7 Interrupt Claim Process ...........................................................................................48
10.8 Interrupt Completion................................................................................................49
11 Error Device ......................................................................................................... 51
12 One-Time Programmable emory (OTP) Peripheral......................52
12.1 Memory Map .......................................................................................................... 52
12.2 Programmed-I/O lock register (otp_lock)................................................................53
12.3 Programmed-I/O Sequencing...................................................................................54
12.4 Read sequencer control register (otp_rsctrl)........................................................54
12.5 OTP Programming Warnings....................................................................................54
12.6 OTP Programming Procedure ..................................................................................55
13 Always-On (AON) Domain ............................................................................56
13.1 AON Power Source.................................................................................................57
13.2 AON Clocking......................................................................................................... 57
13.3 AON Reset Unit ...................................................................................................... 57
13.4 Power-On Reset Circuit ...........................................................................................57
13.5 xternal Reset Circuit..............................................................................................58
13.6 Reset Cause........................................................................................................... 58
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13.7 Watchdog Timer (WDT) ...........................................................................................58
13.8 Real-Time Clock (RTC)............................................................................................58
13.9 Backup Registers.................................................................................................... 58
13.10 Power-Management Unit (PMU) .............................................................................58
13.11 AON Memory Map.................................................................................................58
14 Watchdog Timer (WDT) ..................................................................................61
14.1 Watchdog Count Register (wdogcount)...................................................................61
14.2 Watchdog Clock Selection .......................................................................................62
14.3 Watchdog Configuration Register (wdogcfg).............................................................62
14.4 Watchdog Compare Register (wdogcmp)...................................................................63
14.5 Watchdog Key Register (wdogkey)..........................................................................63
14.6 Watchdog Feed Address (wdogfeed).......................................................................64
14.7 Watchdog Configuration ..........................................................................................64
14.8 Watchdog Resets.................................................................................................... 64
14.9 Watchdog Interrupts (wdogip0)...............................................................................64
15 Power- anagement Unit (P U).................................................................65
15.1 PMU Overview........................................................................................................ 66
15.2 Memory Map .......................................................................................................... 66
15.3 PMU Key Register (pmukey)....................................................................................67
15.4 PMU Program......................................................................................................... 67
15.5 Initiate Sleep Sequence Register (pmusleep)...........................................................68
15.6 Wakeup Signal Conditioning ....................................................................................68
15.7 PMU Interrupt nables (pmuie) and Wakeup Cause (pmucause)...............................69
16 Real-Time Clock (RTC) ...................................................................................71
16.1 RTC Count Registers (rtccounthi/rtccountlo)...................................................71
16.2 RTC Configuration Register (rtccfg)......................................................................72
16.3 RTC Compare Register (rtccmp)............................................................................72
17 General Purpose Input/Output Controller (GPIO) ............................74
17.1 GPIO Instance in F 310-G002.................................................................................76
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17.2 Memory Map .......................................................................................................... 76
17.3 Input / Output Values ...............................................................................................76
17.4 Interrupts................................................................................................................ 77
17.5 Internal Pull-Ups ..................................................................................................... 77
17.6 Drive Strength......................................................................................................... 77
17.7 Output Inversion ..................................................................................................... 77
17.8 HW I/O Functions (IOF) ...........................................................................................77
18 Universal Asynchronous Receiver/Transmitter (UART)...............79
18.1 UART Overview ...................................................................................................... 79
18.2 UART Instances in F 310-G002...............................................................................79
18.3 Memory Map .......................................................................................................... 80
18.4 Transmit Data Register (txdata).............................................................................80
18.5 Receive Data Register (rxdata)..............................................................................80
18.6 Transmit Control Register (txctrl).........................................................................81
18.7 Receive Control Register (rxctrl)..........................................................................81
18.8 Interrupt Registers (ip and ie)................................................................................82
18.9 Baud Rate Divisor Register (div).............................................................................82
19 Serial Peripheral Interface (SPI) ................................................................84
19.1 SPI Overview.......................................................................................................... 84
19.2 SPI Instances in F 310-G002 ..................................................................................84
19.3 Memory Map .......................................................................................................... 85
19.4 Serial Clock Divisor Register (sckdiv).....................................................................86
19.5 Serial Clock Mode Register (sckmode).....................................................................87
19.6 Chip Select ID Register (csid)................................................................................87
19.7 Chip Select Default Register (csdef).......................................................................88
19.8 Chip Select Mode Register (csmode)........................................................................88
19.9 Delay Control Registers (delay0 and delay1).........................................................89
19.10 Frame Format Register (fmt).................................................................................89
19.11 Transmit Data Register (txdata)...........................................................................90
19.12 Receive Data Register (rxdata)............................................................................91
19.13 Transmit Watermark Register (txmark)..................................................................91
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19.14 Receive Watermark Register (rxmark)...................................................................92
19.15 SPI Interrupt Registers (ie and ip)........................................................................92
19.16 SPI Flash Interface Control Register (fctrl)..........................................................93
19.17 SPI Flash Instruction Format Register (ffmt)..........................................................93
20 Pulse Width odulator (PW ) ...................................................................94
20.1 PWM Overview ....................................................................................................... 94
20.2 PWM Instances in F 310-G002 ...............................................................................95
20.3 PWM Memory Map .................................................................................................95
20.4 PWM Count Register (pwmcount)............................................................................96
20.5 PWM Configuration Register (pwmcfg).....................................................................97
20.6 Scaled PWM Count Register (pwms).........................................................................98
20.7 PWM Compare Registers (pwmcmp0–pwmcmp3)........................................................98
20.8 Deglitch and Sticky Circuitry.....................................................................................99
20.9 Generating Left- or Right-Aligned PWM Waveforms .................................................100
20.10 Generating Center-Aligned (Phase-Correct) PWM Waveforms ................................100
20.11 Generating Arbitrary PWM Waveforms using Ganging ............................................101
20.12 Generating One-Shot Waveforms .........................................................................102
20.13 PWM Interrupts................................................................................................... 102
21 Inter-Integrated Circuit (I²C) aster Interface ..................................103
21.1 I²C Instance in F 310-G002...................................................................................103
22 Debug .................................................................................................................... 104
22.1 Debug CSRs ........................................................................................................ 104
22.1.1 Trace and Debug Register Select (tselect)..................................................104
22.1.2 Trace and Debug Data Registers (tdata1-3)................................................105
22.1.3 Debug Control and Status Register (dcsr).....................................................106
22.1.4 Debug PC dpc .............................................................................................106
22.1.5 Debug Scratch dscratch.............................................................................106
22.2 Breakpoints .......................................................................................................... 106
22.2.1 Breakpoint Match Control Register mcontrol ................................................106
22.2.2 Breakpoint Match Address Register (maddress).............................................108
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22.2.3 Breakpoint xecution ....................................................................................108
22.2.4 Sharing Breakpoints Between Debug and Machine Mode ................................109
22.3 Debug Memory Map..............................................................................................109
22.3.1 Debug RAM and Program Buffer (0x300–0x3FF)...........................................109
22.3.2 Debug ROM (0x800–0xFFF)........................................................................109
22.3.3 Debug Flags (0x100–0x110,0x400–0x7FF)................................................110
22.3.4 Safe Zero Address........................................................................................110
23 Debug Interface................................................................................................111
23.1 JTAG TAPC State Machine ....................................................................................111
23.2 Resetting JTAG Logic............................................................................................112
23.3 JTAG Clocking...................................................................................................... 112
23.4 JTAG Standard Instructions ...................................................................................113
23.5 JTAG Debug Commands .......................................................................................113
24 References.......................................................................................................... 114
7

Chapter 1
Introduction
The F 310-G002 is the second revision of the General Purpose Freedom 300 family.
The F 310-G002 is built around the 31 Core Complex instantiated in the Freedom 300 plat-
form and fabricated in the TSMC CL018G 180nm process. This manual serves as an architec-
tural reference and integration guide for the F 310-G002.
The F 310-G002 is compatible with all applicable RISC‑V standards, and this document should
be read together with the official RISC‑V user-level, privileged, and external debug architecture
specifications.
1.1 FE310-G002 Overview
Figure 1 shows the overall block diagram of the F 310-G002.
A feature summary table can be found in Table 1.
8

Figure 1: F 310-G002 top-level block diagram.
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Feature Description Available in
QFN48
RISC-V Core
1× 31 RISC‑V cores with machine and user mode,
16 KiB 2-way L1 I-cache, and 16 KiB data tightly inte-
grated memory (DTIM).
✔
Interrupts Software and timer interrupts, 52 peripheral interrupts con-
nected to the PLIC with 7 levels of priority. ✔
UART 0 Universal Asynchronous/Synchronous Transmitters for
serial communication. ✔
UART 1 Universal Asynchronous/Synchronous Transmitters for
serial communication. ✔
QSPI 0 Serial Peripheral Interface. QSPI 0 has 1 chip select sig-
nal.
✔
(4 DQ lines)
SPI 1 Serial Peripheral Interface. SPI 1 has 4 chip select signals.
✔
(3 CS lines)
(2 DQ lines)
SPI 2 Serial Peripheral Interface. SPI 2 has 1 chip select signal.
PWM 0 8-bit Pulse-width modulator with 4 comparators. ✔
PWM 1 16-bit Pulse-width modulator with 4 comparators. ✔
PWM 2 16-bit Pulse-width modulator with 4 comparators. ✔
I²C 0 Inter-Integrated Circuit (I²C) controller. ✔
GPIO 32 General Purpose I/O pins. ✔
Always On
Domain Supports low-power operation and wakeup. ✔
Table 1: F 310-G002 Feature Summary.
1.2 E31 RISC‑V Core
The F 310-G002 includes a 32-bit 31 RISC‑V core, which has a high-performance single-
issue in-order execution pipeline, with a peak sustainable execution rate of one instruction per
clock cycle. The 31 core supports Machine and User privilege modes as well as standard Mul-
tiply, Atomic, and Compressed RISC‑V extensions (RV32IMAC).
The core is described in more detail in Chapter 3.
1.3 Interrupts
The F 310-G002 includes a RISC-V standard platform-level interrupt controller (PLIC), which
supports 52 global interrupts with 7 priority levels. The F 310-G002 also provides the standard
RISC‑V machine-mode timer and software interrupts via the Core-Local Interruptor (CLINT).
Interrupts are described in Chapter 8. The CLINT is described in Chapter 9. The PLIC is
described in Chapter 10.
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1.4 On-Chip emory System
The 31 core has a(n) 2-way set-associative 16 KiB L1 instruction cache and a(n) 16 KiB L1
DTIM.
All cores have Physical Memory Protection (PMP) units.
The Level 1 memories are described in Chapter 3. The PMP is described in Section 3.7.
1.5 Always-On (AON) Block
The AON block contains the reset logic for the chip, an on-chip low-frequency oscillator, a
watchdog timer, connections for an off-chip low-frequency oscillator, the real-time clock, a pro-
grammable power-management unit, and 32×32-bit backup registers that retain state while the
rest of the chip is in a low-power mode.
The AON can be instructed to put the system to sleep. The AON can be programmed to exit
sleep mode on a real-time clock interrupt or when the external digital wakeup pin, dwakeup_n, is
pulled low. The dwakeup_n input supports wired-OR connections of multiple wakeup sources.
The Always-On block is described in Chapter 13.
1.6 GPIO Complex
The GPIO complex manages the connection of digital I/O pads to digital peripherals, including
SPI, UART, I²C, and PWM controllers, as well as for regular programmed I/O operations.
The GPIO complex is described in more detail in Chapter 17.
1.7 Universal Asynchronous Receiver/Transmitter
Multiple universal asynchronous receiver/transmitter (UARTs) are available and provide a
means for serial communication between the F 310-G002 and off-chip devices.
The UART peripherals are described in Chapter 18.
1.8 Hardware Serial Peripheral Interface (SPI)
There are 3 serial peripheral interface (SPI) controllers. ach controller provides a means for
serial communication between the F 310-G002 and off-chip devices, like quad-SPI Flash mem-
ory. ach controller supports master-only operation over single-lane, dual-lane, and quad-lane
protocols. ach controller supports burst reads of 32 bytes over TileLink to accelerate instruc-
tion cache refills. 1 SPI controller can be programmed to support eXecute-In-Place (XIP) modes
to reduce SPI command overhead on instruction cache refills.
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The SPI interface is described in more detail in Chapter 19.
1.9 Pulse Width odulation
The pulse width modulation (PWM) peripheral can generate multiple types of waveforms on
GPIO output pins and can also be used to generate several forms of internal timer interrupt.
The PWM peripherals are described in Chapter 20.
1.10 I²C
The F 310-G002 has an I²C controller to communicate with external I²C devices, such as sen-
sors, ADCs, etc.
The I²C is described in detail in Chapter 21.
1.11 Debug Support
The F 310-G002 provides external debugger support over an industry-standard JTAG port,
including 8 hardware-programmable breakpoints per hart.
Debug support is described in detail in Chapter 22, and the debug interface is described in
Chapter 23.
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Chapter 2
List of Abbreviations and Terms
13

Term Definition
BHT Branch History Table
BTB Branch Target Buffer
RAS Return-Address Stack
CLINT Core-Local Interruptor. Generates per-hart software interrupts and timer
interrupts.
CLIC Core-Local Interrupt Controller. Configures priorities and levels for core
local interrupts.
hart HARdware Thread
DTI Data Tightly Integrated Memory
ITI Instruction Tightly Integrated Memory
JTAG Joint Test Action Group
LI Loosely Integrated Memory. Used to describe memory space delivered in
a SiFive Core Complex but not tightly integrated to a CPU core.
P P Physical Memory Protection
PLIC Platform-Level Interrupt Controller. The global interrupt controller in a
RISC-V system.
TileLink A free and open interconnect standard originally developed at UC Berke-
ley.
RO Used to describe a Read Only register field.
RW Used to describe a Read/Write register field.
WO Used to describe a Write Only registers field.
WARL Write-Any Read-Legal field. A register field that can be written with any
value, but returns only supported values when read.
WIRI Writes-Ignored, Reads-Ignore field. A read-only register field reserved for
future use. Writes to the field are ignored, and reads should ignore the
value returned.
WLRL Write-Legal, Read-Legal field. A register field that should only be written
with legal values and that only returns legal value if last written with a
legal value.
WPRI Writes-Preserve Reads-Ignore field. A register field that might contain
unknown information. Reads should ignore the value returned, but writes
to the whole register should preserve the original value.
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Chapter 3
E31 RISC-V Core
This chapter describes the 32-bit 31 RISC‑V processor core used in the F 310-G002. The
31 processor core comprises an instruction memory system, an instruction fetch unit, an exe-
cution pipeline, a data memory system, and support for global, software, and timer interrupts.
The 31 feature set is summarized in Table 2.
Feature Description
ISA RV32IMAC.
Instruction Cache 16 KiB 2-way instruction cache.
Instruction Tightly Integrated Memory The 31 has support for an ITIM with a maxi-
mum size of 8 KiB.
Data Tightly Integrated Memory 16 KiB DTIM.
Modes The 31 supports the following modes:
Machine Mode, User Mode.
Table 2: 31 Feature Set
3.1 Instruction emory System
The instruction memory system consists of a dedicated 16 KiB 2-way set-associative instruction
cache. The access latency of all blocks in the instruction memory system is one clock cycle. The
instruction cache is not kept coherent with the rest of the platform memory system. Writes to
instruction memory must be synchronized with the instruction fetch stream by executing a
F NC .I instruction.
The instruction cache has a line size of 32 bytes, and a cache line fill triggers a burst access.
The core caches instructions from executable addresses, with the exception of the Instruction
Tightly Integrated Memory (ITIM), which is further described in Section 3.1.1. See the
F 310-G002 Memory Map in Chapter 4 for a description of executable address regions that are
denoted by the attribute X.
Trying to execute an instruction from a non-executable address results in a synchronous trap.
15

3.1.1 I-Cache Reconfigurability
The instruction cache can be partially reconfigured into ITIM, which occupies a fixed address
range in the memory map. ITIM provides high-performance, predictable instruction delivery.
Fetching an instruction from ITIM is as fast as an instruction-cache hit, with no possibility of a
cache miss. ITIM can hold data as well as instructions, though loads and stores from a core to
its ITIM are not as performant as loads and stores to its Data Tightly Integrated Memory (DTIM).
The instruction cache can be configured as ITIM for all ways except for 1 in units of cache lines
(32 bytes). A single instruction cache way must remain an instruction cache. ITIM is allocated
simply by storing to it. A store to the nth byte of the ITIM memory map reallocates the first n+1
bytes of instruction cache as ITIM, rounded up to the next cache line.
ITIM is deallocated by storing zero to the first byte after the ITIM region, that is, 8 KiB after the
base address of ITIM as indicated in the Memory Map in Chapter 4. The deallocated ITIM space
is automatically returned to the instruction cache.
For determinism, software must clear the contents of ITIM after allocating it. It is unpredictable
whether ITIM contents are preserved between deallocation and allocation.
3.2 Instruction Fetch Unit
The 31 instruction fetch unit contains branch prediction hardware to improve performance of
the processor core. The branch predictor comprises a 28-entry branch target buffer (BTB) which
predicts the target of taken branches, a 512-entry branch history table (BHT), which predicts the
direction of conditional branches, and a 6-entry return-address stack (RAS) which predicts the
target of procedure returns. The branch predictor has a one-cycle latency, so that correctly pre-
dicted control-flow instructions result in no penalty. Mispredicted control-flow instructions incur a
three-cycle penalty.
The 31 implements the standard Compressed (C) extension to the RISC‑V architecture, which
allows for 16-bit RISC‑V instructions.
3.3 Execution Pipeline
The 31 execution unit is a single-issue, in-order pipeline. The pipeline comprises five stages:
instruction fetch, instruction decode and register fetch, execute, data memory access, and regis-
ter writeback.
The pipeline has a peak execution rate of one instruction per clock cycle, and is fully bypassed
so that most instructions have a one-cycle result latency. There are several exceptions:
• LW has a two-cycle result latency, assuming a cache hit.
• LH, LHU, LB, and LBU have a three-cycle result latency, assuming a cache hit.
• CSR reads have a three-cycle result latency.
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• MUL, MULH, MULHU, and MULHSU have a 5-cycle result latency.
• DIV, DIVU, R M, and R MU have between a 2-cycle and 33-cycle result latency, depending
on the operand values.
The pipeline only interlocks on read-after-write and write-after-write hazards, so instructions
may be scheduled to avoid stalls.
The 31 implements the standard Multiply (M) extension to the RISC‑V architecture for integer
multiplication and division. The 31 has a 8-bit per cycle hardware multiply and a 1-bit per cycle
hardware divide. The multiplier can only execute one operation at a time and will block until the
previous operation completes.
The hart will not abandon a Divide instruction in flight. This means if an interrupt handler tries to
use a register that is the destination register of a divide instruction the pipeline stalls until the
divide is complete.
Branch and jump instructions transfer control from the memory access pipeline stage. Correctly-
predicted branches and jumps incur no penalty, whereas mispredicted branches and jumps
incur a three-cycle penalty.
Most CSR writes result in a pipeline flush with a five-cycle penalty.
3.4 Data emory System
The 31 data memory system consists of a DTIM. The access latency from a core to its own
DTIM is two clock cycles for full words and three clock cycles for smaller quantities. Misaligned
accesses are not supported in hardware and result in a trap to allow software emulation.
Stores are pipelined and commit on cycles where the data memory system is otherwise idle.
Loads to addresses currently in the store pipeline result in a five-cycle penalty.
3.5 Atomic emory Operations
The 31 core supports the RISC‑V standard Atomic (A) extension on the DTIM and the periph-
eral memory region. Atomic memory operations to regions that do not support them generate an
access exception precisely at the core.
The load-reserved and store-conditional instructions are only supported on cached regions,
hence generate an access exception on DTIM and other uncached memory regions.
See The RISC‑V Instruct on Set Manual, Volume I: User-Level ISA, Vers on 2.1 for more infor-
mation on the instructions added by this extension.
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3.6 Supported odes
The 31 supports RISC‑V user mode, providing two levels of privilege: machine (M) and user
(U). U-mode provides a mechanism to isolate application processes from each other and from
trusted code running in M-mode.
See The RISC‑V Instruct on Set Manual, Volume II: Pr v leged Arch tecture, Vers on 1.10 for
more information on the privilege modes.
3.7 Physical emory Protection (P P)
The 31 includes a Physical Memory Protection (PMP) unit compliant with The RISC‑V Instruc-
t on Set Manual, Volume II: Pr v leged Arch tecture, Vers on 1.10. PMP can be used to set mem-
ory access privileges (read, write, execute) for specified memory regions. The 31 PMP sup-
ports 8 regions with a minimum region size of 4 bytes.
This section describes how PMP concepts in the RISC‑V architecture apply to the 31. The
definitive resource for information about the RISC‑V PMP is The RISC‑V Instruct on Set Manual,
Volume II: Pr v leged Arch tecture, Vers on 1.10.
3.7.1 Functional Description
The 31 includes a PMP unit, which can be used to restrict access to memory and isolate
processes from each other.
The 31 PMP unit has 8 regions and a minimum granularity of 4 bytes. Overlapping regions are
permitted. The 31 PMP unit implements the architecturally defined pmpcfgX CSRs pmpcfg0
and pmpcfg1 supporting 8 regions. pmpcfg2 and pmpcfg3 are implemented but hardwired to
zero.
The PMP registers may only be programmed in M-mode. Ordinarily, the PMP unit enforces per-
missions on U-mode accesses. However, locked regions (see Section 3.7.2) additionally
enforce their permissions on M-mode.
3.7.2 Region Locking
The PMP allows for region locking whereby, once a region is locked, further writes to the config-
uration and address registers are ignored. Locked PMP entries may only be unlocked with a
system reset. A region may be locked by setting the Lbit in the pmpicfg register.
In addition to locking the PMP entry, the Lbit indicates whether the R/W/X permissions are
enforced on M-Mode accesses. When the Lbit is clear, the R/W/X permissions apply only to U-
mode.
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