Silicon Laboratories EFM8 Series User manual

EFM8 Universal Bee Family
EFM8UB3 Reference Manual
The EFM8UB3, part of the Universal Bee family of MCUs, is a
multi-purpose line of 8-bit microcontrollers with USB feature set in
small packages.
These devices offer high value by integrating an innovative energy-smart USB peripheral
interface, charger detect circuit, 8 kV ESD protection, and enhanced high speed commu-
nication interfaces into small packages, making them ideal for space-constrained USB
applications. With an efficient 8051 core and precision analog, the EFM8UB3 family is
also optimal for embedded applications.
EFM8UB3 applications include the following:
KEY FEATURES
• Pipelined 8-bit C8051 core with 48 MHz
maximum operating frequency
• Up to 17 multifunction I/O pins
• Low Energy USB with full- and low-speed
support saves up to 90% of the USB
energy
• USB charger detect circuit (USB-BCS 1.2
compliant)
• One 12-bit ADC and two analog
comparators with internal voltage DAC as
reference input
• Six 16-bit timers
• UART and SMBus master/slave
• Priority crossbar for flexible pin mapping
• USB I/O controls
• Docking stations/USB hubs
• Dongles
• Consumer electronics
• USB Type-C converters
• USB Type-C billboard/alternate mode
SecurityI/O Ports
Core / Memory Clock Management
CIP-51 8051 Core
(48 MHz)
High Frequency
48 MHz RC
Oscillator
Energy Management
Internal LDO
Regulator
Brown-Out
Detector
Power-On Reset
8-bit SFR bus
Serial Interfaces Timers and Triggers Analog Interfaces
Pin Reset ADC
Comparator 0
Internal Voltage
Reference
16-bit CRC
Flash Memory
40 KB
RAM Memory
3328 bytes
Debug Interface
with C2
Lowest power mode with peripheral operational:
IdleNormal ShutdownSuspend Snooze
5 V-to 3.3 V LDO
Regulator
USB
High Frequency
24.5 MHz RC
Oscillator
Pin Wakeup
External
Interrupts
General
Purpose I/O
SMBus
UART
External CMOS
Oscillator
Low Frequency
RC Oscillator
SPI
Charger Det
Comparator 1
Timer 3/4/5
4 x Configurable Logic Units
Watchdog
Timer
PCA/PWM
Timers
0/1/2
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Table of Contents
1. System Overview .............................13
1.1 Introduction ...............................13
1.2 Power .................................14
1.3 I/O ..................................14
1.4 Clocking ................................15
1.5 Counters/Timers and PWM ..........................15
1.6 Communications and Other Digital Peripherals ...................17
1.7 Analog.................................19
1.8 Reset Sources ..............................20
1.9 Debugging ...............................20
1.10 Bootloader ...............................21
2. Memory ................................23
2.1 Memory Organization............................23
2.2 Program Memory .............................23
2.3 Data Memory ..............................23
2.4 Memory Map ..............................25
2.5 XRAM Control Registers...........................27
2.5.1 EMI0CN: External Memory Interface Control ..................27
3. Special Function Registers .........................28
3.1 Special Function Register Access .......................28
3.2 Special Function Register Memory Map .....................30
3.3 SFR Access Control Registers.........................37
3.3.1 SFRPAGE: SFR Page ..........................37
3.3.2 SFRPGCN: SFR Page Control .......................38
3.3.3 SFRSTACK: SFR Page Stack .......................38
4. Flash Memory ..............................39
4.1 Introduction ...............................39
4.2 Features ................................39
4.3 Functional Description ...........................40
4.3.1 Security Options ............................40
4.3.2 Programming the Flash Memory ......................41
4.3.3 Flash Write and Erase Precautions......................42
4.4 Flash Control Registers ...........................43
4.4.1 PSCTL: Program Store Control .......................43
4.4.2 FLKEY: Flash Lock and Key ........................44
5. Device Identification ...........................45
5.1 Device Identification ............................45
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5.2 Unique Identifier .............................45
5.3 Device Identification Registers.........................45
5.3.1 DEVICEID: Device Identification.......................45
5.3.2 DERIVID: Derivative Identification ......................46
5.3.3 REVID: Revision Identifcation .......................46
6. Interrupts ................................ 47
6.1 Introduction ...............................47
6.2 Interrupt Sources and Vectors .........................47
6.2.1 Interrupt Priorities ...........................47
6.2.2 Interrupt Latency ............................48
6.2.3 Interrupt Summary ...........................49
6.3 Interrupt Control Registers ..........................51
6.3.1 IE: Interrupt Enable ...........................51
6.3.2 IP: Interrupt Priority ...........................53
6.3.3 IPH: Interrupt Priority High ........................54
6.3.4 EIE1: Extended Interrupt Enable 1 ......................55
6.3.5 EIP1: Extended Interrupt Priority 1 Low ....................57
6.3.6 EIP1H: Extended Interrupt Priority 1 High ...................58
6.3.7 EIE2: Extended Interrupt Enable 2 ......................59
6.3.8 EIP2: Extended Interrupt Priority 2 ......................60
6.3.9 EIP2H: Extended Interrupt Priority 2 High ...................61
7. Power Management and Internal Regulators ..................62
7.1 Introduction ...............................62
7.2 Features ................................63
7.3 Idle Mode................................64
7.4 Stop Mode ...............................64
7.5 Suspend Mode ..............................64
7.6 Snooze Mode ..............................65
7.7 Shutdown Mode .............................65
7.8 5V-to-3.3V Regulator ............................65
7.9 Power Management Control Registers ......................66
7.9.1 PCON0: Power Control..........................66
7.9.2 PCON1: Power Control 1 .........................67
7.9.3 PSTAT0: Power Status..........................68
7.9.4 REG0CN: Voltage Regulator 0 Control ....................69
7.9.5 REG1CN: Voltage Regulator 1 Control ....................70
8. Clocking and Oscillators ..........................71
8.1 Introduction ...............................71
8.2 Features ................................71
8.3 Functional Description ...........................71
8.3.1 Clock Selection ............................71
8.3.2 HFOSC0 24.5 MHz Internal Oscillator .....................72
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8.3.3 HFOSC1 48 MHz Internal Oscillator .....................72
8.3.4 LFOSC0 80 kHz Internal Oscillator ......................72
8.3.5 External Clock.............................72
8.4 Clocking and Oscillator Control Registers .....................73
8.4.1 CLKSEL: Clock Select ..........................73
8.4.2 HFO0CAL: High Frequency Oscillator 0 Calibration ................74
8.4.3 HFO1CAL: High Frequency Oscillator 1 Calibration ................74
8.4.4 HFOCN: High Frequency Oscillator Control ...................75
8.4.5 LFO0CN: Low Frequency Oscillator Control...................76
9. Reset Sources and Power Supply Monitor ...................77
9.1 Introduction ...............................77
9.2 Features ................................77
9.3 Functional Description ...........................78
9.3.1 Device Reset .............................78
9.3.2 Power-On Reset ............................79
9.3.3 Supply Monitor Reset ..........................80
9.3.4 External Reset ............................80
9.3.5 Missing Clock Detector Reset .......................80
9.3.6 Comparator (CMP0) Reset ........................81
9.3.7 Watchdog Timer Reset ..........................81
9.3.8 Flash Error Reset ...........................81
9.3.9 Software Reset ............................81
9.3.10 USB Reset .............................81
9.4 Reset Sources and Supply Monitor Control Registers .................82
9.4.1 RSTSRC: Reset Source .........................82
9.4.2 VDM0CN: Supply Monitor Control ......................83
10. CIP-51 Microcontroller Core ........................84
10.1 Introduction ..............................84
10.2 Features ...............................85
10.3 Functional Description ...........................85
10.3.1 Programming and Debugging Support ....................85
10.3.2 Prefetch Engine............................85
10.3.3 Instruction Set ............................86
10.4 CPU Core Registers ...........................90
10.4.1 DPL: Data Pointer Low .........................90
10.4.2 DPH: Data Pointer High .........................90
10.4.3 SP: Stack Pointer ...........................90
10.4.4 ACC: Accumulator ...........................91
10.4.5 B: B Register.............................91
10.4.6 PSW: Program Status Word .......................92
10.4.7 PFE0CN: Prefetch Engine Control .....................93
11. Port I/O, Crossbar, External Interrupts, and Port Match ..............94
11.1 Introduction ..............................94
11.2 Features ...............................94
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11.3 Functional Description ...........................95
11.3.1 Port I/O Modes of Operation .......................95
11.3.2 Analog and Digital Functions .......................96
11.3.3 Priority Crossbar Decoder ........................98
11.3.4 INT0 and INT1 ...........................100
11.3.5 Port Match ............................100
11.3.6 Direct Port I/O Access (Read/Write) ....................100
11.4 Port I/O Control Registers .........................101
11.4.1 XBR0: Port I/O Crossbar 0 .......................101
11.4.2 XBR1: Port I/O Crossbar 1 .......................103
11.4.3 XBR2: Port I/O Crossbar 2 .......................104
11.4.4 PRTDRV: Port Drive Strength ......................105
11.4.5 P0MASK: Port 0 Mask ........................106
11.4.6 P0MAT: Port 0 Match .........................107
11.4.7 P0: Port 0 Pin Latch .........................108
11.4.8 P0MDIN: Port 0 Input Mode .......................109
11.4.9 P0MDOUT: Port 0 Output Mode .....................110
11.4.10 P0SKIP: Port 0 Skip .........................111
11.4.11 P1MASK: Port 1 Mask ........................112
11.4.12 P1MAT: Port 1 Match ........................113
11.4.13 P1: Port 1 Pin Latch .........................114
11.4.14 P1MDIN: Port 1 Input Mode ......................115
11.4.15 P1MDOUT: Port 1 Output Mode .....................116
11.4.16 P1SKIP: Port 1 Skip .........................117
11.4.17 P2MASK: Port 2 Mask ........................118
11.4.18 P2MAT: Port 2 Match ........................118
11.4.19 P2: Port 2 Pin Latch .........................119
11.4.20 P2MDIN: Port 2 Input Mode ......................119
11.4.21 P2MDOUT: Port 2 Output Mode .....................120
11.5 INT0 and INT1 Control Registers ......................121
11.5.1 IT01CF: INT0/INT1 Configuration .....................121
12. Analog-to-Digital Converter (ADC0) .....................123
12.1 Introduction .............................123
12.2 Features ..............................124
12.3 Functional Description ..........................124
12.3.1 Clocking .............................124
12.3.2 Voltage Reference Options .......................124
12.3.3 Input Selection ...........................125
12.3.4 Gain Setting ............................126
12.3.5 Initiating Conversions .........................126
12.3.6 Input Tracking ...........................126
12.3.7 Burst Mode ............................129
12.3.8 8-Bit Mode ............................129
12.3.9 12-Bit Mode ............................130
12.3.10 Output Formatting .........................131
12.3.11 Power Considerations ........................132
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12.3.12 Window Comparator .........................134
12.3.13 Temperature Sensor .........................136
12.4 ADC0 Control Registers .........................137
12.4.1 ADC0CN0: ADC0 Control 0 .......................137
12.4.2 ADC0CN1: ADC0 Control 1 .......................138
12.4.3 ADC0CF: ADC0 Configuration ......................139
12.4.4 ADC0AC: ADC0 Accumulator Configuration .................140
12.4.5 ADC0PWR: ADC0 Power Control .....................142
12.4.6 ADC0TK: ADC0 Burst Mode Track Time ..................143
12.4.7 ADC0H: ADC0 Data Word High Byte ...................143
12.4.8 ADC0L: ADC0 Data Word Low Byte ....................144
12.4.9 ADC0GTH: ADC0 Greater-Than High Byte .................144
12.4.10 ADC0GTL: ADC0 Greater-Than Low Byte .................144
12.4.11 ADC0LTH: ADC0 Less-Than High Byte ..................145
12.4.12 ADC0LTL: ADC0 Less-Than Low Byte ..................145
12.4.13 ADC0MX: ADC0 Multiplexer Selection ...................145
12.4.14 REF0CN: Voltage Reference Control ...................146
13. Comparators (CMP0 and CMP1) .......................147
13.1 Introduction .............................147
13.2 Features ..............................147
13.3 Functional Description ..........................148
13.3.1 Response Time and Supply Current ....................148
13.3.2 Hysteresis ............................148
13.3.3 Input Selection ...........................148
13.3.4 Output Routing ...........................153
13.4 CMP0 Control Registers .........................155
13.4.1 CMP0CN0: Comparator 0 Control 0 ....................155
13.4.2 CMP0MD: Comparator 0 Mode .....................157
13.4.3 CMP0MX: Comparator 0 Multiplexer Selection ................158
13.4.4 CMP0CN1: Comparator 0 Control 1 ....................159
13.5 CMP1 Control Registers .........................160
13.5.1 CMP1CN0: Comparator 1 Control 0 ....................160
13.5.2 CMP1MD: Comparator 1 Mode .....................162
13.5.3 CMP1MX: Comparator 1 Multiplexer Selection ................163
13.5.4 CMP1CN1: Comparator 1 Control 1 ....................164
14. Configurable Logic Units (CLU0, CLU1, CLU2, CLU3) ...............165
14.1 Introduction .............................165
14.2 Features ..............................166
14.3 Functional Description ..........................167
14.3.1 Configuration Sequence ........................167
14.3.2 Input Multiplexer Selection .......................167
14.3.3 Output Configuration .........................169
14.3.4 LUT Configuration ..........................169
14.4 Configurable Logic Control Registers .....................170
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14.4.1 CLEN0: Configurable Logic Enable 0 ...................170
14.4.2 CLIE0: Configurable Logic Interrupt Enable 0 .................171
14.4.3 CLIF0: Configurable Logic Interrupt Flag 0 ..................172
14.4.4 CLOUT0: Configurable Logic Output 0 ...................173
14.4.5 CLU0MX: Configurable Logic Unit 0 Multiplexer ................173
14.4.6 CLU0FN: Configurable Logic Unit 0 Function Select ..............174
14.4.7 CLU0CF: Configurable Logic Unit 0 Configuration ...............175
14.4.8 CLU1MX: Configurable Logic Unit 1 Multiplexer ................176
14.4.9 CLU1FN: Configurable Logic Unit 1 Function Select ..............176
14.4.10 CLU1CF: Configurable Logic Unit 1 Configuration ...............177
14.4.11 CLU2MX: Configurable Logic Unit 2 Multiplexer ...............178
14.4.12 CLU2FN: Configurable Logic Unit 2 Function Select ..............178
14.4.13 CLU2CF: Configurable Logic Unit 2 Configuration ...............179
14.4.14 CLU3MX: Configurable Logic Unit 3 Multiplexer ...............180
14.4.15 CLU3FN: Configurable Logic Unit 3 Function Select ..............180
14.4.16 CLU3CF: Configurable Logic Unit 3 Configuration ...............181
15. Cyclic Redundancy Check (CRC0) ......................182
15.1 Introduction .............................182
15.2 Features ..............................182
15.3 Functional Description ..........................183
15.3.1 16-bit CRC Algorithm .........................183
15.3.2 Using the CRC on a Data Stream .....................184
15.3.3 Using the CRC to Check Code Memory ...................184
15.3.4 Bit Reversal ............................184
15.4 CRC0 Control Registers .........................185
15.4.1 CRC0CN0: CRC0 Control 0.......................185
15.4.2 CRC0IN: CRC0 Data Input .......................185
15.4.3 CRC0DAT: CRC0 Data Output......................186
15.4.4 CRC0ST: CRC0 Automatic Flash Sector Start ................186
15.4.5 CRC0CNT: CRC0 Automatic Flash Sector Count ...............186
15.4.6 CRC0FLIP: CRC0 Bit Flip .......................187
15.4.7 CRC0CN1: CRC0 Control 1.......................187
16. Programmable Counter Array (PCA0) .....................188
16.1 Introduction .............................188
16.2 Features ..............................189
16.3 Functional Description ..........................189
16.3.1 Counter / Timer ...........................189
16.3.2 Interrupt Sources ..........................190
16.3.3 Capture/Compare Modules .......................190
16.3.4 Edge-Triggered Capture Mode ......................191
16.3.5 Software Timer (Compare) Mode .....................192
16.3.6 High-Speed Output Mode .......................193
16.3.7 Frequency Output Mode ........................194
16.3.8 PWM Waveform Generation ......................194
16.4 PCA0 Control Registers .........................201
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16.4.1 PCA0CN0: PCA Control ........................201
16.4.2 PCA0MD: PCA Mode .........................202
16.4.3 PCA0PWM: PCA PWM Configuration ...................203
16.4.4 PCA0CLR: PCA Comparator Clear Control .................204
16.4.5 PCA0L: PCA Counter/Timer Low Byte ...................204
16.4.6 PCA0H: PCA Counter/Timer High Byte ...................205
16.4.7 PCA0POL: PCA Output Polarity .....................205
16.4.8 PCA0CENT: PCA Center Alignment Enable .................206
16.4.9 PCA0CPM0: PCA Channel 0 Capture/Compare Mode ..............207
16.4.10 PCA0CPL0: PCA Channel 0 Capture Module Low Byte .............208
16.4.11 PCA0CPH0: PCA Channel 0 Capture Module High Byte ............208
16.4.12 PCA0CPM1: PCA Channel 1 Capture/Compare Mode .............209
16.4.13 PCA0CPL1: PCA Channel 1 Capture Module Low Byte .............210
16.4.14 PCA0CPH1: PCA Channel 1 Capture Module High Byte ............210
16.4.15 PCA0CPM2: PCA Channel 2 Capture/Compare Mode .............211
16.4.16 PCA0CPL2: PCA Channel 2 Capture Module Low Byte .............212
16.4.17 PCA0CPH2: PCA Channel 2 Capture Module High Byte ............212
17. Serial Peripheral Interface (SPI0) ......................213
17.1 Introduction .............................213
17.2 Features ..............................213
17.3 Functional Description ..........................214
17.3.1 Signals ..............................214
17.3.2 Master Mode Operation ........................215
17.3.3 Slave Mode Operation ........................216
17.3.4 Clock Phase and Polarity .......................217
17.3.5 Basic Data Transfer .........................218
17.3.6 Using the SPI FIFOs .........................218
17.3.7 SPI Timing Diagrams .........................221
17.4 SPI0 Control Registers ..........................224
17.4.1 SPI0CFG: SPI0 Configuration ......................224
17.4.2 SPI0CN0: SPI0 Control ........................226
17.4.3 SPI0CKR: SPI0 Clock Rate .......................227
17.4.4 SPI0DAT: SPI0 Data .........................227
17.4.5 SPI0FCN0: SPI0 FIFO Control 0 .....................228
17.4.6 SPI0FCN1: SPI0 FIFO Control 1 .....................229
17.4.7 SPI0FCT: SPI0 FIFO Count.......................230
17.4.8 SPI0PCF: SPI0 Pin Configuration .....................231
18. System Management Bus / I2C (SMB0) ....................232
18.1 Introduction .............................232
18.2 Features ..............................232
18.3 Functional Description ..........................232
18.3.1 Supporting Documents ........................232
18.3.2 SMBus Protocol ...........................233
18.3.3 Configuring the SMBus Module .....................235
18.3.4 Operational Modes ..........................240
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18.4 SMB0 Control Registers .........................248
18.4.1 SMB0CF: SMBus 0 Configuration .....................248
18.4.2 SMB0TC: SMBus 0 Timing and Pin Control .................249
18.4.3 SMB0CN0: SMBus 0 Control ......................250
18.4.4 SMB0ADR: SMBus 0 Slave Address ....................251
18.4.5 SMB0ADM: SMBus 0 Slave Address Mask .................252
18.4.6 SMB0DAT: SMBus 0 Data .......................252
18.4.7 SMB0FCN0: SMBus 0 FIFO Control 0 ...................253
18.4.8 SMB0FCN1: SMBus 0 FIFO Control 1 ...................254
18.4.9 SMB0RXLN: SMBus 0 Receive Length Counter ................255
18.4.10 SMB0FCT: SMBus 0 FIFO Count ....................255
19. Timers (Timer0, Timer1, Timer2, Timer3, Timer4, and Timer5) ............256
19.1 Introduction .............................256
19.2 Features ..............................256
19.3 Functional Description ..........................257
19.3.1 System Connections .........................257
19.3.2 Timer 0 and Timer 1 .........................258
19.3.3 Timer 2, Timer 3, Timer 4, and Timer 5 ...................262
19.4 Timer 0, 1, 2, 3, 4, and 5 Control Registers ...................268
19.4.1 CKCON0: Clock Control 0 .......................268
19.4.2 CKCON1: Clock Control 1 .......................270
19.4.3 TCON: Timer 0/1 Control .......................271
19.4.4 TMOD: Timer 0/1 Mode ........................272
19.4.5 TL0: Timer 0 Low Byte ........................273
19.4.6 TL1: Timer 1 Low Byte ........................273
19.4.7 TH0: Timer 0 High Byte ........................274
19.4.8 TH1: Timer 1 High Byte ........................274
19.4.9 TMR2CN0: Timer 2 Control 0 ......................275
19.4.10 TMR2RLL: Timer 2 Reload Low Byte ...................276
19.4.11 TMR2RLH: Timer 2 Reload High Byte ...................276
19.4.12 TMR2L: Timer 2 Low Byte .......................276
19.4.13 TMR2H: Timer 2 High Byte ......................277
19.4.14 TMR2CN1: Timer 2 Control 1 ......................278
19.4.15 TMR3CN0: Timer 3 Control 0 ......................279
19.4.16 TMR3RLL: Timer 3 Reload Low Byte ...................280
19.4.17 TMR3RLH: Timer 3 Reload High Byte ...................280
19.4.18 TMR3L: Timer 3 Low Byte .......................280
19.4.19 TMR3H: Timer 3 High Byte ......................281
19.4.20 TMR3CN1: Timer 3 Control 1 ......................282
19.4.21 TMR4CN0: Timer 4 Control 0 ......................284
19.4.22 TMR4RLL: Timer 4 Reload Low Byte ...................285
19.4.23 TMR4RLH: Timer 4 Reload High Byte ...................285
19.4.24 TMR4L: Timer 4 Low Byte .......................285
19.4.25 TMR4H: Timer 4 High Byte ......................286
19.4.26 TMR4CN1: Timer 4 Control 1 ......................287
19.4.27 TMR5RLL: Timer 5 Reload Low Byte ...................288
19.4.28 TMR5RLH: Timer 5 Reload High Byte ...................288
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19.4.29 TMR5L: Timer 5 Low Byte .......................288
19.4.30 TMR5H: Timer 5 High Byte ......................289
19.4.31 TMR5CN0: Timer 5 Control 0 ......................290
19.4.32 TMR5CN1: Timer 5 Control 1 ......................291
20. Universal Asynchronous Receiver/Transmitter 1 (UART1) .............292
20.1 Introduction .............................292
20.2 Features ..............................292
20.3 Functional Description ..........................293
20.3.1 Baud Rate Generation ........................293
20.3.2 Data Format ............................293
20.3.3 Flow Control ............................294
20.3.4 Basic Data Transfer .........................294
20.3.5 Data Transfer With FIFO ........................294
20.3.6 Multiprocessor Communications .....................297
20.3.7 LIN Break and Sync Detect .......................297
20.3.8 Autobaud Detection .........................297
20.3.9 Routing RX Through Configurable Logic ..................298
20.4 UART1 Control Registers .........................299
20.4.1 SCON1: UART1 Serial Port Control ....................299
20.4.2 SMOD1: UART1 Mode ........................301
20.4.3 SBUF1: UART1 Serial Port Data Buffer ...................302
20.4.4 SBCON1: UART1 Baud Rate Generator Control ................303
20.4.5 SBRLH1: UART1 Baud Rate Generator High Byte ...............303
20.4.6 SBRLL1: UART1 Baud Rate Generator Low Byte ...............304
20.4.7 UART1FCN0: UART1 FIFO Control 0 ...................305
20.4.8 UART1FCN1: UART1 FIFO Control 1 ...................307
20.4.9 UART1FCT: UART1 FIFO Count .....................308
20.4.10 UART1LIN: UART1 LIN Configuration ...................309
20.4.11 UART1PCF: UART1 Configuration ....................310
21. Universal Serial Bus (USB0) ........................311
21.1 Introduction .............................311
21.2 Features ..............................311
21.3 Functional Description ..........................312
21.3.1 Endpoint Addressing .........................312
21.3.2 Transceiver Control .........................312
21.3.3 Clock Configuration .........................312
21.3.4 VBUS Control ...........................312
21.3.5 Register Access...........................313
21.3.6 FIFO Management ..........................315
21.3.7 Function Addressing .........................316
21.3.8 Function Configuration and Control ....................317
21.3.9 Interrupts .............................317
21.3.10 Serial Interface Engine ........................317
21.3.11 Endpoint 0 ............................318
21.3.12 Endpoints 1, 2, and 3 ........................319
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