Silicon Laboratories Si53154-EVB User manual

Rev. 0.1 1/12 Copyright © 2012 by Silicon Labs Si53154-EVB
Si53154-EVB
Si53154 EVALUATION BOARD USER’SGUIDE
Description
The Si53154 is a four port PCIe clock buffer compliant
to the PCIe Gen1, Gen2 and Gen3 standards. The
Si53154 is a 24-pin QFN device that operates on a
3.3 V power supply and can be controlled using SMBus
signals along with hardware control input pins. The
device is spread aware and accepts a frequency spread
differential clock frequency range from 100 to 210 MHz.
The connections are described in this document.
EVB Features
This document is intended to be used in conjunction
with the Si53154 device and data sheet for the following
tests:
PCIe Gen1, Gen2, Gen3 compliancy
Power consumption test
Jitter performance
Testing out I2C code for signal tuning
In-system validation where SMA connectors are
present
Si53154
SRC3
connection
for
application
SRC2
connection
for
application
SRC1
connection for
application
VDD = 3.3V
power supply
GND
SDATA
SCLK
SRC0
connection for
application
DIFF3 Output Enable
DIFF1 Output Enable
DIFF2 Output Enable
DIFF0 Output Enable
Power connectors
Differential
Clock Input

Si53154-EVB
2 Rev. 0.1
1. Front Panel
Figure 1. Evaluation Module Front Panel
Table 1. Input Jumper Settings
Jumper Label Type Description
OE0 I OE0, 3.3 V Input for Enabling DIFF0 Clock Output.
1 = DIFF0 enabled, 0 = DIFF0 disabled.
OE1 I OE1, 3.3 V Input for Enabling DIFF1 Clock Output.
1 = DIFF1 enabled, 0 = DIFF1 disabled.
OE2 I OE2, 3.3 V Input for Enabling DIFF2 Clock Output.
1 = DIFF2 enabled, 0 = DIFF2 disabled.
OE3 I OE3, 3.3 V Input for Enabling DIFF3 Clock Output.
1 = DIFF3 enabled, 0 = DIFF3 disabled.
SDATA I/O SMBus-Compatible SDATA.
SCLK I SMBus-Compatible SCLOCK.
I2C connect -For I2C read and
write. In sequence SData, Gnd,
SCLK from left to right .
3.3V Power Supply Connector
VDD Connectors OE_DIFF3 hardware input
control for DIFF3 out
p
ut
DIFF3 Differential output
DIFF2 Differential output
DIFF1 Differential output
DIFF0 Differential output
Differential Buffer Input
for on Si53154-EVB only
No Connect
OE0 hardware input
control for DIFF0 output
OE1 hardware input
control for DIFF1 output
OE2 hardware input
control for DIFF2 output
Si53154 device mount
GND Connector

Si53154-EVB
Rev. 0.1 3
1.1. Generating DIFF Outputs from the Si53154
Upon power-on of the device if the differential input is applied and input pins are left floating, by default all DIFF
outputs DIFF[0:3] are ON. The input pin headers have clear indication of jumper settings for setting logic low (0)
and high (1) as shown in the figure below, the jumper placed on middle and left pin will set input OE0 to low; and
jumper placed on middle and right pin will set input OE0 to high.
The output enable pins can be changed on the fly to observe outputs stopped cleanly. Input functionality is
explained in detail below.
1.1.1. OE [0:3] Inputs
The output enable pins can change on the fly when the device is on. Deasserting (valid low) results in
corresponding DIFF output to be stopped after their next transition with final state low/low. Asserting (valid high)
results in corresponding output that was stopped are to resume normal operation in a glitch-free manner.
Each of the hardware OE [0:3] pins are mapped via I2C to control bit in Control register. The hardware pin and the
Register Control Bit both need to be high to enable the output. Both of these form an “AND” function to disable or
enable the DIFF output. Both of these form an “AND” function to disable or enable the DIFF output. The DIFF
outputs and their corresponding I2C control bits and hardware pins are listed in Table 2.
Table 2. Output Enable Control
I2C Control Bit Output Hardware Control Input
Byte1 [bit 2] DIFF0 OE0
Byte1 [bit 0] DIFF1 OE1
Byte2 [bit 7] DIFF2 OE2
Byte2 [bit 6] DIFF3 OE3


Si53154-EVB
4 Rev. 0.1
2. Schematics
Figure 2. QFN-24 Device Connection
Figure 3. Device Power Supply
DUTGND
DUTGND
XTL P/N:
ECS-250-20-5PXDU-F-TR
Use SMD footprint
DUTGND
0
0
For Si52144,R10 open
For Si53154,R11 open
VDD1
VDD6
VDD12
VDD17
VDD21
DIFF0
DIFF0#
DIFF1
DIFF1#
DIFF2
DIFF2#
DIFF3
DIFF3#
SCLK
SDATA
OE2
OE0
OE3
OE1
XOUT_DIFFIN
XIN_DIFF IN#
SSON
VDD1
YC2
NI
YC1
NI
R4
C5
0.1uF
R3
NI
C4
0.1uF
R2
NI
C3
0.1uF
R1
C2
0.1uF
R11 NI
R10
0
C1
0.1uF
U1
Si53154
EPAD
25
DIFF2 14
OE1
2
XOUT/DIFFIN 22
VDD
3
OE2
5
OE3
18
OE0
7
DIFF1# 11
DIFF1 10
DIFF0# 9
DIFF0 8
VDD21
21 VDD17
17 VDD12
12 VDD6
6VDD1
1
VSS4
4
XIN/DIFFIN# 23
SCLK
19
SDA
20
VSS24
24
DIFF3# 15
DIFF3 16
DIFF2# 13
Y1
NI
VCC_3.3V
VCC_3.3V
VDD1
VDD21
VDD6
VDD12
VDD17
C7
0.1uF
+
C9
10uF
JP4
JUMPER
+
C8
10uF
C16
1uF
GND1
HEADER 1x1
1
L6
TP4
JP3
JUMPER
C15
1uF
C14
1uF
L5
VDD_3.3V1
HEADER 1x1
1
C17
1uF
L4
C13
1uF
L3
JP2
JUMPER
R9
0
L2
R8
0
TP5
JP1
JUMPER
R7
0
TP1 TP2
R6
0
R5
0
+
C12
10uF
+
C11
10uF
JP5
JUMPER
L1
+
C6
10uF
TP3
+
C10
10uF

Si53154-EVB
Rev. 0.1 5
Figure 4. Clock and Control Signals
Figure 5. Differential Clock Signals
SCLK/SDATA
DUTGND
DUTGND
DUTGND
DUTGND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
DUTGND
OE2
OE0
OE3
OE1
DUTGND
DUTGND
SSON
DUTGND
VDD
GND
VDD_3.3V
VDD_3.3V
VDD_3.3V
VDD_3.3V
VDD_3.3V
VDD_3.3V
VDD_3.3V
OE2
OE0
OE3
OE1
SSON
SCLK
SDATA
XIN_ D IF F IN#
XOUT_DIFFIN
XOUT _D IFF IN1
SMA
R24
10K
P4
HEADER 1 x3
1
2
3
P2
HEADER 1 x3
1
2
3
R20
10K
R23
10K
XIN_ D IF F IN# 1
SMA
P1
HEADER 1x3
1
2
3
P3
HEADER 1x3
1
2
3
R17
10K
R15
10K
R16
10K
P6
HEADER 1x3
1
2
3
P5
HEADER 1x3
1
2
3
L1 SHOULD BE
SHORT AS POSSIBLE
L1 SHOULD BE
SHORT AS POSSIBLE
L1 SHOULD BE
SHORT AS POSSIBLE
L1 SHOULD BE
SHORT AS POSSIBLE
DUTGND
DUTGND
DUTGND
DUTGND
DUTGND
DUTGND
DUTGND
DUTGND
DUTGND
DUTGND
DUTGND
DUTGND
DUTGND
DIFF0
DIFF0#
DIFF1#
DIFF1
DIFF2#
DIFF2
DIFF3#
DIFF3
C28
2.0pF
DIFF0_1
SMA
C33
2.0pF
C30
2.0pF
C27
2.0pF
DIFF1_1
SMA
DIFF3#_1
SMA
DIFF2#_1
SMA
C32
2.0pF
C29
2.0pF
C34
2.0pF
DIFF3_1
SMA
DIFF1#_1
SMA
DIFF2_1
SMA
DIFF0#_1
SMA
C31
2.0pF

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