SiTime SiT6502EB User manual

SiT6502EB HW UM Preliminary Rev 1.0
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SiT6502EB Evaluation Board (EVB) HW User Manual
Contents
1 Introduction ............................................................................................................................................. 1
2 SiT6502EB Features.................................................................................................................................. 1
3 SiT6502EB Support Collateral .................................................................................................................. 2
4 Connectors Descriptions .......................................................................................................................... 2
5 Test Points Descriptions........................................................................................................................... 3
6 Jumpers Default List................................................................................................................................. 4
7 Status LEDs............................................................................................................................................... 5
8 SiT6502EB Power Supplying..................................................................................................................... 6
9 I2C/SPI Mode Connection......................................................................................................................... 8
10 Clock Inputs.............................................................................................................................................. 8
11 Clock Outputs........................................................................................................................................... 9
11.1 Output Differential Termination.................................................................................................... 10
11.1.1LVDS, CML............................................................................................................................10
11.1.2LVPECL ................................................................................................................................. 11
11.1.3HCSL..................................................................................................................................... 11
12 Quick Start.............................................................................................................................................. 11
Appendix A: EVB Schematic Diagrams........................................................................................................13
Appendix B: EVB Top View.......................................................................................................................... 32
1Introduction
The SiT6502EB Evaluation Board (EVB) is designed evaluating the programmable jitter attenuating clock
synthesizer SiT95147 device.
2SiT6502EB Features
-Powered from USB port or external power supply
-Programmable VDDO supplies for each of the 8 outputs selectable from 3.3, 2.5, or 1.8V
-Status LEDs for power supplies status signals of SiT6502EB
-Each of the 8 outputs accessible via edge mount
-High bandwidth SMA connectors
-4 pairs of edge mount SMA connectors for feeding external differential or single-ended clocks
-Supports full configuration flexibility of the device via standard I2C or SPI interface with a
Windows hosted Time Master for Clocks GUI

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3SiT6502EB Support Collateral
The SiT6502EB Evaluation Board is provided with the following collateral:
-SiT6502EB EVB HW User Manual
-Time Master for Clocks SW
-Time Master for Clocks SW User Manual
4Connectors Descriptions
Table 1 lists the SiT6502EB EVB connectors.
Table 1. SiT6502EB connectors
Connector Designators
Description
Power + Control
USB Type B connectors (J3) for Device programming and
+5V supply
Power
USB Type B connectors (J4) for +5V supply, 2-pin connectors
(J80, J7) for external +5V power supply
Inputs
SMA connectors (J35 through J42) for receiving external
clock signals
Outputs
SMA connectors (J43 through J62) for synthesized clock
outputs
External FTDI supply
2-pin connector (H13)
External +3.3V (VDD Left)
Input receiver supply
2-pin connector (H1)
External +3.3V (VDD PLL)
supply
2-pin connector (H12)
External Output VDD Supply
2-pin connectors (H2 through H11)
Common Mode to GND
Headers in output
terminations
2-pin Headers (JSCL13 through JSCL22)
Output LDO Regulators
Enable Inputs to GND Headers
2-pin Headers (J2, JSCL3 through JSCL11), shorted by default
for LDO outputs enabling
Left Supply LDO Regulators
Enable Inputs to GND Headers
2-pin Headers (J1), shorted by default for LDO outputs
enabling
Header for internal use only
2-pin Header (JSCL 1), shorted by default
Headers for I2C bus Pull-up
2-pin Headers (JSCL 2, JSCL 12), shorted by default
Header
1-pin Header (J5)
Header for PLL supply LDO
regulator output Shut Down
2-pin Header (J12)

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Connector Designators
Description
Header for internal use only
10-pin Header (J76)
(Default Jumper position see in Figure A20)
PullUp vs PullDown switch
Headers
3-pin Headers (J67 through J69, J72 through J74, J75, J81,
JVDD1)
Signals switch Header
3-pin Header (J71)
PLL supply voltage source
switching Header
3-pin Header (J31)
PLL supply voltage levels
switching Header
3-pin Header (J32)
Left supply voltage source
switching Header
3-pin Header (J8)
Left supply voltage levels
switching Header
3-pin Header (J9)
FTDI supply voltages source
switching Header
3-pin Header (J78)
FTDI supply voltage levels
switching Header
3-pin Header (J30)
USB –External Power sources
switching Headers
3-pin Headers (J79, J6)
Outputs supply voltage
source switching Header
3-pin Headers (J10, J77, J14, J16, J18, J20, J22, J24, J26, J28)
Outputs supply voltage levels
switching Header
3-pin Headers (J11, J13, J15, J17, J19, J21, J23, J25, J27, J29)
5Test Points Descriptions
Table 2 describes all Test Point (TP)s on the EVB.
Table 2. SiT6502EB Test Points description
Connector Designators
Description
GND Test Points
1-pin Headers (TP1, TP3, TP4, TP5, TP7)
Reference Clock Test Point
1-pin Header (TP6)
Test Points for internal use only
1-pin Headers (TP2, TP8, J82 through J86)

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6Jumpers Default List
Table 3 lists the default positions of the Jumpers on the EVB.
Table 3. Jumper Default List
Jumper
Location
Type
I = Installed
O = Open
Jumper
Location
Type
I = Installed
O = Open
Jumper
Location
Type
I = Installed
O = Open
JSCL1
2-Pin
I
J1
2-Pin
I
J28
3-Pin
1 to 2
JSCL2
2-Pin
I
J2
3-Pin
1 to 2
J29
3-Pin
1 to 2
JSCL3
2-Pin
I
J6
3-Pin
2 to 3
J30
3-Pin
1 to 2
JSCL4
2-Pin
I
J8
3-Pin
1 to 2
J31
3-Pin
1 to 2
JSCL5
2-Pin
I
J9
3-Pin
1 to 2
J32
3-Pin
2 to 3
JSCL6
2-Pin
I
J10
3-Pin
1 to 2
J67
3-Pin
O
JSCL7
2-Pin
I
J11
3-Pin
1 to 2
J68
3-Pin
O
JSCL8
2-Pin
I
J12
2-Pin
O
J69
3-Pin
O
JSCL9
2-Pin
I
J13
3-Pin
1 to 2
J71
3-Pin
O
JSCL10
2-Pin
I
J14
3-Pin
1 to 2
J72
3-Pin
O
JSCL11
2-Pin
I
J15
3-Pin
1 to 2
J73
3-Pin
1 to 2
JSCL12
2-Pin
I
J16
3-Pin
1 to 2
J74
3-Pin
O
JSCL13
2-Pin
O
J17
3-Pin
1 to 2
J75
3-Pin
2 to 3
JSCL14
2-Pin
O
J18
3-Pin
1 to 2
J76
10-Pin
Header
1 to 2,
3 to 4,
7 to 8,
9 to 10
JSCL15
2-Pin
O
J19
3-Pin
1 to 2
J77
3-Pin
1 to 2
JSCL16
2-Pin
O
J20
3-Pin
1 to 2
J78
3-Pin
1 to 2
JSCL17
2-Pin
O
J21
3-Pin
1 to 2
J79
3-Pin
1 to 2
JSCL18
2-Pin
O
J22
3-Pin
1 to 2
J80
2-Pin
O
JSCL19
2-Pin
O
J23
3-Pin
1 to 2
J81
3-Pin
O
JSCL20
2-Pin
O
J24
3-Pin
1 to 2
J87
3-Pin
O
JSCL21
2-Pin
O
J25
3-Pin
1 to 2
J88
3-Pin
O
JSCL22
2-Pin
O
J26
3-Pin
1 to 2
J89
3-Pin
O
JVDD1
3-Pin
2 to 3
J27
3-Pin
1 to 2

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7Status LEDs
Table 4 lists the Status LEDs on the SiT6502EB EVB in Figure 1.
Table 4. SiT6502EB Status LEDs
Location
Color
Status Function Indication
D5
Blue
5V Main USB Power
D6
Blue
5V Additional USB Power
D12
Green
FTDI_5V_Power
D13
Green
FTDI_3.3V_Power
*Note: All LEDs are illuminated when corresponding voltages are present.
Figure 1. Status LEDs

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8SiT6502EB Power Supplying
Device under Test (DUT) Analog supplying voltage (VDDIN) and DUT outputs supplying voltages (VDDOx)
on the SiT6502EB are configured to 3.3V by default, whereas DUT PLLs supplying voltage VDD supply is
configured to 1.8V. The on board supplies/LDO’s are configurable to 1.8V, 2.5V and 3.3V with the
Jumper option as shown in Figure 2. Please refer to SiT95147 datasheet for configuring the supply
voltages on the VDDIN/VDD and VDDOx pins and to the Table 5 for on board configuration options for
SiT95147:
Table 5. SiT6502EB Supply configuration
Variant
VDD
VDDIN
VDDOx
SiT95147
2.5V / 3.3V
2.5V / 3.3V
1.8V / 2.5V / 3.3V
Figure 2. Supply Regulator for VDDIN/VDDOx
Note: For changing the VDDIN (J9) and VDDOx Supply, connect the corresponding Jumpers to below
settings:
1. 3.3V - Connect the 3-Pin Jumper from 1 to 2.
2. 2.5V - Connect the 3-Pin Jumper from 2 to 3.
3. 1.8V - Remove the Jumper.
There is a provision for connecting external supplies after bypassing the on board regulators for all the
supplies as shown in Figure 3.

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Figure 3. External Supply Connection Provision
PLLs supply circuitry is shown in Figure 4.
Figure 4. Supply Regulator for PLLs
Note: For changing the VDD (J32) Supply, connect the Jumper to below settings:
1. 3.3V - Connect the 3-Pin Jumper from 2 to 3.
2. 2.5V - Connect the 3-Pin Jumper from 1 to 2.

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3. 1.8V - Remove the Jumper.
9I2C/SPI Mode Connection
The 10 pin Header J76 (Figure 5) is mainly used for configuring the SiT6503EB into I2C and SPI Mode
(I2C Mode is default one)
For I2C Mode of Operation:
1. SCLK_OUT is shorted to SCLK in J76.
2. SDAIO_OUT is shorted to SDAIO in J76.
3. CSB_OUT is shorted to CSB in J76.
Figure 5. Supply Regulator for PLLs
For SPI Mode of Operation:
1. SCLK_OUT is shorted to SCLK in J76.
2. SDAIO_OUT is shorted to SDAIO in J76.
3. CSB_OUT is shorted to CSB in J76.
4. SDO_OUT is shorted to SDO in J76.
5. JSCL1 Jumper should be removed.
6. JVDD1 Jumper should be changed from (2 to 3) to (1 to 2).
7. J73 Jumper should be changed from (1 to 2) to (2 to 3).
10 Clock Inputs
The SiT6502EB has eight inputs (4 differential pairs) with SMA connectors (IN0_P, IN0_N, IN1_P, IN1_N,
IN2_P, IN2_N, IN3_P, IN3_N) for receiving external clock signals. All input clocks are ac-coupled and
50 terminated as shown in Figure 6 below. This represents four differential input clock pairs. Single-

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ended clocks can be used by driving the ‘P’ side of the differential pair with the ‘N’ input floating.
Figure 6 shows the Input Clock Termination Circuit for one of the 4 pairs.
Figure 6. Input Clock Termination Circuit
11 Clock Outputs
When shipped from factory, each of the twenty output drivers (8 differential pairs) is ac-coupled to its
respective SMA connector –this is the default configuration. The output clock termination circuit is
shown in Figure 7 below. If dc coupling is required, the corresponding 0.1 uF ac coupling capacitor can
be replaced with a zero resistor. Figure 7 shows Output Clock Termination Circuit for one of the 8
output pairs.

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Figure 7. Output Clock Termination Circuit
11.1 Output Differential Termination
LVDS (default configuration), LVPECL, HCSL, and CML differential signaling types can be supported by
changing the output termination circuits.
11.1.1 LVDS, CML
The board is shipped to support LVDS, CML in its default differential. The signals are ac coupled with
ceramic 0.1 uF capacitors instead of the corresponding series resistors RSExx (Refer to Table 6) which
are not populated.
Table 6. Output Port RSExx Resistors
Output Port #
0
1
2
3
4
5
6
7
0B
0T
0.1 uF capacitors
RSE1
RSE5
RSE2
RSE6
RSE4
RSE7
RSE3
RSE8
RSE10
RSE14
RSE9
RSE13
RSE11
RSE15
RSE12
RSE16
RSE17
RSE19
RSE18
RSE20
Output termination resistors as shown in Table 7 are not populated.
CSE6
10pF
VCM_1 JSCL14
JSCL2
12
DNP
J44
CONNECTOR COAX-P_3PIN
1
2 3
DNP
CLK1_OUT_P
GND
VCM_1
CLK1_DUT_N
GND
R118
49.9
DNP
CLK1_DUT_P
DNP
GND
R111
0
R123
0
CLK1_OUT_N
RSE2
453E
C71
10 uF
DNP
CLK1_DUT_P
CSE2
10pF
DNP
C70
1 uF
GND
CLK1_OUT_P
CLK1_DUT_N
J49 CONNECTOR COAX-P_3PIN
1
2 3
CLK1_OUT_N
RSE6
453E
R114
49.9

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Table 7. Output Port Not Populated Resistors
Output Port #
0
1
2
3
4
5
6
7
0B
0T
Not Populated
Resistors
R113
R117
R114
R118
R115
R119
R116
R120
R129
R133
R130
R134
R131
R135
R132
R136
R143
R145
R144
R146
11.1.2 LVPECL
For LVPECL output configuration ceramic capacitors 0.1 uF are placed instead of correspondent series
resistors RSExx (Refer to Table 6). Termination resistor values depending on the output driver VDD level
are shown in Table 8.
Table 8. Output Port Termination Resistors for LVPECL
Output Port #
0
1
2
3
4
5
6
7
0B
0T
Resistors
R113
R117
R114
R118
R115
R119
R116
R120
R129
R133
R130
R134
R131
R135
R132
R136
R143
R145
R144
R146
VDD, 3.3V
150 
150 
150 
150 
150 
150 
150 
150 
150 
150 
VDD, 2.5V
120 
120 
120 
120 
120 
120 
120 
120 
120 
120 
Also, ensure that jumpers JSCLxx as per Table 9 are populated to allow path to GND.
Table 9. Output Port Jumpers to GND
Output Port #
0
1
2
3
4
5
6
7
0B
0T
Jumpers to GND
JSCL13
JSCL14
JSCL15
JSCL16
JSCL17
JSAL18
JSCL19
JSCL20
JSCL21
JSCL22
11.1.3 HCSL
For HCSL output configuration series resistors RSExx (Refer to Table 6). 33 should be used for each
output port. Please note each lane per pair should be terminated by 50 to GND on the receiver side.
12 Quick Start
-Install Time Master for Clocks GUI on your Windows PC
-Confirm jumpers are installed as shown in Table 3
-Connect a USB cable from SiT6502EB, J3 to your PC
-Launch the Time Master for Clocks GUI
-Refer to the accompanying Time Master for Clocks SW User Manual to configure your frequency
plan on the SiT6502EB
-Default Output Driver Configuration is LVDS and Output Driver Supplies are configured to 3.3V

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-Default VDD Supply on the EVB is configured to 1.8V and default VDDIN supply on the EVB is
configured to 3.3V
-The FTDI chip on the EVB is configured to I2C as the default communication protocol
-EVB default configuration is shown in Figure 8.
Figure 8. SiT6502EB Starter Connection Diagram
The general guidelines for single USB power supply operation are listed below:
-Use either a USB 3.0 or USB 2.0 port. These ports are specified to supply 900 mA and 500 mA
respectively at +5V
-If you are working with a USB 2.0 port and you are current limited, turn off enough DUT output
voltage regulators to drop the total DUT current ≤470 mA.
Note: USB 2.0 ports may supply > 500 mA. Provided the nominal +5V drops gracefully by less
than 10%, the EVB will still work

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Appendix A: EVB Schematic Diagrams
EVB Top Level Diagram
Figure A1. SiT6502EB Top Level Diagram

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VDDS Supply
Figure A2. SiT6502EB VDDS Supply Diagram

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Power Supply
Figure A3. SiT6502EB Power Supply Diagram

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Left Supply
Figure A4. SiT6502EB Left Supply Diagram

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ODR1 Supply
Figure A5. SiT6502EB ODR1 Supply Diagram

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ODR2 Supply
Figure A6. SiT6502EB ODR2 Supply Diagram

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ODR3 Supply
Figure A7. SiT6502EB ODR3 Supply Diagram

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ODR5 Supply
Figure A8. SiT6502EB ODR5 Supply Diagram