SONIX SNM9S50 Series User manual

SNM9S50x/51xx/52xx
2-wire Interface Manual
www.sonix.com.tw
1
STWM-2010
About This Document
This purpose of this document is to introduce SONiX 2-wire interface of the SNM9S50x/51xx/52xx Series
by defining the Master and Slave of the transmission, explaining signal, data transmission, and data format.
Refer to the commands provided in the end of this document to make various settings of OID decoder
functions.
Revision History
Date
Revision
Description
21-Oct-2020
Version 1.0
Initial release
Convention
WARNING
Indicates a hazard with a medium or low level of risk that, if not avoided, could result
in minor or moderate injury.
TIP
Indicates a tip that may help you solve a problem or save time.
NOTE
Provides additional information to emphasize or supplement important points of the
main text.

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Table of Contents
1Introduction...........................................................................................................................................4
1.1 Master and Slave........................................................................................................................4
1.2 Signal Description.......................................................................................................................4
2Data Transmission................................................................................................................................6
2.1 Read Operation...........................................................................................................................6
2.2 Write Operation...........................................................................................................................7
2.3 Timing.........................................................................................................................................8
3Data Format........................................................................................................................................10
4Command...........................................................................................................................................13
4.1 Single Command ......................................................................................................................13
4.2 Multi-write Command................................................................................................................13

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List of Figures
Figure 1–1Master and Slave 2-wire Interface Communication.............................................................4
Figure 1–2Bit Transfer on 2-wire Interface...........................................................................................4
Figure 2–1Conditions of 2-wire Interface .............................................................................................6
Figure 2–2Valid Data ...........................................................................................................................6
Figure 2–3Read Operation...................................................................................................................7
Figure 2–4Write Operation...................................................................................................................8
Figure 2–5Timing.................................................................................................................................9
Figure 3–1Coordinate for OID3 with Position Code...........................................................................11
Figure 4–1Multi-write Command........................................................................................................13
List of Tables
Table 1–1Characteristics of SCLK and SDIO.....................................................................................5
Table 2–1SDIO Status in Read Operation..........................................................................................7
Table 2–2SDIO Status in Write Operation..........................................................................................7
Table 2–3Timing Requirements..........................................................................................................8
Table 3–1Indication and Definition of Bit [63:0].................................................................................10
Table 3–2Code Type v.s. Value Combination...................................................................................10
Table 3–3Valid Index Indication of Bit [59:0].....................................................................................10
Table 3–4Invalid Index Indication of Bit [59:0] ..................................................................................11
Table 3–564-bit Data of OID3 Position Code....................................................................................11
Table 3–6Command Indication.........................................................................................................12
Table 3–7Command Value...............................................................................................................12
Table 3–8Options for Command Indication.......................................................................................12
Table 4–1Command and Setting Value............................................................................................13
Table 4–2PGA Gain1 Setting............................................................................................................14
Table 4–3PGA Gain2 Setting............................................................................................................14

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1Introduction
1.1 Master and Slave
1.2 Signal Description
1.1 Master and Slave
A Master device is the device that initiatesa data transfer on the bus and generates the clock signals to
permit that transfer. The 2-wire interface of SONiX OID products receives and transmits signals
between the backend DSP/MCU (Master) and OID decoder (Slave). Functions of the Master include:
•Initiating a transfer cycle
•Generating clock signals
•Deciding the direction of a transfer cycle
Anydevice that is addressed by the Master is considered a Slave during transfer. To send data to the
Master, the Slave initiates a transfer request to the Master by pulling SDIO low.
OID Decoder
(Slave)
SCLK
SDIO DSP/MCU
(Master)
4.7K
VDD
Figure 1–1 Master and Slave 2-wire Interface Communication
1.2 Signal Description
The 2-wire interface has a serial clock pin (SCLK) and a serial data pin (SDIO) for data communication.
The SDIO is connected to a positive supply voltage using a 4.7K pull-up resistor to reduce rising time
as shown in Figure 1–1. The data on SDIO must be stable during the low period of the clock. The
state of the data line, SDIO only changes when the clock signal of SCLK is high.
Change of
data allowed
Data line stable
Figure 1–2 Bit Transfer on 2-wire Interface
The table below describes the characteristics of SCLK and SDIO. The data transmitted from the OID
decoder to the DSP/MCU are 64-bit indexand command. The data transmitted from the DSP/MCU to
the OID decoder are 8-bit commands.

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Table 1–1 Characteristics of SCLK and SDIO
Item
SCLK
SDIO
Usage
Serial clock
Serial data
Transmission Direction
DSP/MCU →OID
DSP/MCU ↔ OID
Pull High
No
Yes
Default Status
Low
Pulled high
The table below lists some of the recommended SONiX backend DSP to pair with SONiX OID image
decoder or OID decoder module. For more options and detailed information of each product, refer to
http://www.sonix.com.tw/category-tw-146.
Part No.
System
Clock
(MHz)
Audio
Channel
Audio Format
RAM
(Word)
SNC7648
24.576
1
MIDI/Audio32/SNX8K/Music96/IMMPCM/MSADPCM
4K
SNC7649
49.152
1
MIDI/Audio32/SNX8K/Music96/IMMPCM/MSADPCM
12K
SNC715
16
1
MRC
2K
SNC71101
48
1
MIDI/Audio32/SNX8K
4K
SNC7001A
48
2
MIDI/Audio32/SNX8K/Music96/IMAADPCM
16K

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2Data Transmission
2.1 Read Operation
2.2 Write Operation
2.3 Timing
The Master holds the signal on SCLK low, and an external pull-up resistor pulls the signal on SDIO
high by default. To begin a transfer, the Master keeps the signal on SCLK high, and the Slave waits
for the first falling edge of the signal on SCLK to read the read/write (R/W) control bit. The data
transfer includes:
•A START condition is defined as a low-to-high transition on the SCLK line. The Master drives
this condition to indicate the start of a data transfer.
•A R/W control bit: The Master controls the SDIO to indicate data direction.
•A stop condition is defined as the SCLK line staying low over 78 μs. The Master drives this
condition to indicate the end of the data transfer. When the bus is free, the serial clock is low
and the serial data is high.
Figure 2–1 Conditions of 2-wire Interface
Data transfer starts from the MSB to the LSB sequentially. The Master must control the SCLK as
below.
•Keep high for over 4 μs for SDIO state change
•Keep low for over 2 μs but less than 78 μs for data access
Figure 2–2 Valid Data
2.1 Read Operation
The read operation is initiated by the Master to transfer data from the Slave to the Master. In R/W
control bit, the Master keeps the R/W control bit on SDIO low to indicate read operation. The table
below lists the controlled status of the signal on SDIO in different timing during a read operation.
StopDefault Start Default
Pull High
R/W Control Bit
Default
SDIO
SCLK
4 μs
2 μs–78 μs
SDIO
SCLK

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Table 2–1 SDIO Status in Read Operation
Line
Part
Start
1st (R/W
Control) Bit
2nd–65th Bit
Stop
SDIO
Master
Z
L
Z
Z
Slave
L
Z
64-bit data
Z
Abbreviations: Z = High impedance, L = Logic low
To begin reading, the Slave pulls the signal on SDIO low as a transmission request to the Master.
The Master pulls the signal on SCLK low and sets the R/W control bit on the SDIO. The Slave begins
to read each bit on SDIO at every rising edge of signal on SCLK. When the read operation completes,
the Master keeps the signal on SCLK low as a stop condition. The Slave releases the SDIO on the
falling edge for an external pull-up resistor to pull high.
Figure 2–3 Read Operation
NOTE
In both read and write operations, the Slave releases the signal on SDIO when
the Master generates a rising edge of the signal on SCLK to start the
operation. It is normal for the signal of SDIO be pulled up for a split second at
the first clock after the Slave’s release for the Master controls the signal on
SDIO. For the same reason, there is another split second of signal rising on
SDIO at the second clock after the Master’s release for the Slave to take
control of the SDIO.
2.2 Write Operation
In write operation, the Master transmits data to the Slave. The 8-bit data generated by the Master
transmits on SDIO. In R/W control bit, the Master pulls the R/W control bit on the SDIO high to
indicate write operation. The table below lists the controlled status of the signal on SDIO in different
timing during a write operation.
Table 2–2 SDIO Status in Write Operation
Line
Part
Start
1st (R/W
Control) Bit
2nd–9th Bit
Stop
SDIO
Master
Z
H
8-bit data
H
Slave
L/Z
Z
Z
Z
Abbreviations: Z = High impedance, H = Logic high, L = Logic low
To begin writing, the Master pulls the signal on SCLK high and sets the R/W control bit on the SDIO.
The Master then transfers each data bit to the Slave at each falling edge of the signal on SCLK.
When the write operation completes, the Master keeps the signal on SCLK low as a stop condition.
The Slave releases the SDIO on the falling edge for an external pull-up resistor to pull high. The
signal on SDIO has to be pulled high before every write operation. The Slave pulls the signal on SDIO
Start R/W Bit63 Bit62 Bit61 Bit0
Keep Low
Pull High
Read Control Bit
SDIO
SCLK

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low indicating a transfer request to the Master, and a read operation occurs instead of a write
operation.
Figure 2–4 Write Operation
After the Master transmits 8-bit command to the Slave, the Slave returns 16-bit acknowledgement
(ACK) to the Master if the command is valid. The transmission is similar to a read operation except for
the data length being 16 bits instead of 64 bits. The content of the ACK is command + 1. For
example, if the Master transmits 0x35 command to the Slave, the ACK from the Slave is 0x0036.
2.3 Timing
According to the 2-wire protocol, the Master initiates a start signal by pulling the signal on SCLK from
low to high. The Master initiates a start signal when:
•the Master writes to the Slave.
•the Slave pulls the signal on SDIO low as a transmission request to the Master.
The pulse duration of the high signal on SCLK must exceed the minimum time requirement for the
completion of the state change of the SDIO. To stabilize the signal on SDIO, the signal on SCLK must
stay low for over 2 μs but less than 78 μs. When the signal on SCLK stays low for over 78 μs, the
Master initiates a stop signal to indicate an end of the data transfer.
Table 2–3 Timing Requirements
No.
Parameter
MIN.
MAX.
Unit
1
Tr(SCLK)
Rise time, SCLK
–
< 10
ns
2
Tr(SDIO)
Rise time, SDIO
–
< 4
μs
3
Tf(SCLK)
Fall time, SCLK
–
< 10
ns
4
Tf(SDIO)
Fall time, SDIO
–
< 4
μs
5
Tw(SCLKH)
Pulse duration, SCLK high
4
–
μs
6
Tw(SCLKL)
Pulse duration, SCLK low
2
< 78
μs
7
Tsu(SDIOV-SCLKL)
Setup time, SDIO state change before
SCLK low
–
< Tw(SCLKH)
μs
8
Th(SDIOV-SCLKL)
Hold time, SDIO valid after SCLK low
Tw(SCLKL)
–
μs
Start R/W Bit7 Bit6 Bit1 Bit0
Keep Low
Pull High
Write Control Bit
SDIO
SCLK

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Figure 2–5 Timing
1 3
4
5
7 8
6
2
SDIO
SCLK

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3Data Format
The data format (Format 1.0) has 64-bit addressing. Crucial information such as index and angle are
stored in the lower numbered bits.
Index (Bit 63 = 0)
Indications (INDN) of lower numbered bits vary depending on indications of the higher numbered bits.
When bit 63 = 0 (index), indications of bit 62–0 are listed in the table below. Bit 60 indicates whether
the code is valid or invalid.
Table 3–1 Indication and Definition of Bit [63:0]
Bit
Indication
63
Command/Index
0: Index
1: Command
–
62
OID2/OID3 code
0: OID2
1: OID3
–
–
Bit 62 = 0 (OID2)
Bit 62 = 1 (OID3)
61
Reserved
Code type
0: General
1: Position
–
OID2; OID3 with General Code
OID3 with Position Code
60
Valid or invalid upon decoder error message
0: Valid
1: Invalid
Position code index is valid or invalid
0: Valid
1: Invalid
The table below lists the values of bit[63:60] corresponding different code types of OID2 or OID3 code
for parsing convenience.
Table 3–2 Code Type v.s. Value Combination
Bit
63
62
61
60
Type
OID2 Index
0
0
0
0
OID3 Index with Valid General Code
0
1
0
0
OID3 Index with Valid Position Code
0
1
1
0
Invalid Code
0
Reserved
1
Table 3–3 Valid Index Indication of Bit [59:0]
Valid (Bit 60 = 0)
Bit
Indication
59–54
Reserved
53–45
Angle
44
Reserved
OID2
OID3 with General code
OID3 with Position Code
Bit
Indication
Bit
Indication
Bit
Indication
43–16
Reserved
43–28
Reserved
43–0
Coordinate
15–0
16-bit index
27–0
Index

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Bit 35 Bit 0 Bit 28 Bit 27 Bit 14 Bit 13Bit 43 Bit 36
Y decimal X decimal Y integer X integer
Figure 3–1 Coordinate for OID3 with Position Code
Table 3–4 Invalid Index Indication of Bit [59:0]
Invalid (Bit 60 = 1)
Bit
Indication
59–0
Reserved
Calculation for Coordinates
The position code bit[43:0] of X and Yis consisted of two sets14 bits of unsigned integers and eight bits
of signed decimals. The MSB is a signed bit, and the rest 7 bits are decimals. Use the method
below to convert the coordinate to get the values of X or the Y.
Method
Combine the 14-bit integer bit and 7-bit fractional bit to get a 21-bit coordinate. Convert the coordinate
to decimal and divide it by 128.
The decimal fraction of the X/Y coordinate is signed number. If the decimal is positive,
21-bit coordinate = Shift the integer 7 bits leftward + Decimal
If the decimal is negative, convert to 2’s complement, and then implement subtraction.
21-bit coordinate = Shift the integer 7 bits leftward - Decimal in 2’complement
Coordinate = 21-bit coordinate in decimal / 128
Example
The OID decoder sends 64-bit raw data to the DSP/MCU as shown in the table below. Use the
method above to convert to the X/Y coordinate.
Table 3–5 64-bit Data of OID3 Position Code
Bit
Indication
63–60
0110b
59–54
Reserved
53–45
Angle
44
Reserved
43–36
1111 0010b (Y decimal)
35–28
0111 0100b (X decimal)
27–14
00 0000 0000 0100b (Y integer)
13–0
00 0000 0000 0100b (X integer)
To convert the coordinate to X coordinate:
Combine the integer in binary, 00 0000 0000 0100b, with the fractional bit in binary, 0111 0100b to get
the 21-bit X coordinate.
21-bit X coordinate = 0 0000 0000 0010 0111 0010b
= 29+26+25+24+21
= 626 (decimal)

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X coordinate = 626 / 128
= 4.890625
To convert the coordinate to Y coordinate:
Combine the integer in binary, 00 0000 0000 0100b, with the fractional bit in binary, 1111 0010b to get
the 21-bit Y coordinate.
Since the first bit = 1, the decimal is negative.
Combine the integer in binary, 00 0000 0000 0100b, with the fractional bit in binary, 1111 0010b to get
the 21-bit Y coordinate. Since the first bit is 1, and the decimal is negative, it is necessary to calculate
2’s complement of 1111 0010b before calculating the 21-bit Y coordinate.
2’s complement of 1111 0010b = 0000 1110b
21-bit coordinate = (0 0000 0000 0010 0000 0000b) - (0000 1110b)
= 0 0000 0000 0001 1111 0010b
= 28+27+26+25+24+21
= 498
Y Coordinate = 498 / 128
= 3.890625
The X/Y coordinate is (4.890625,3.890625).
Command (Bit 63 = 1)
When bit 63 = 1, indications of bit 62–0 are listed in the table below.
Table 3–6 Command Indication
Bit
63
62
61
60
...
16
15
...
0
Original
OID Mode
1
0
1
Reserved
Command
Table 3–7 Command Value
Value
Status
0xFFF8
The decoder has entered normal mode.
0xFFF6
The decoder is going to enter the calibration mode, and the DSP/MCU sets SCLK
and SDIO in input mode.
Table 3–8 Options for Command Indication
Bit
Indication
63
Command/Index
1: Command
62–61
OID mode
01: Original OID mode
Else: Reserved
60–16
Reserved
15–0
Command
0xFFF8: Decoder entered normal mode.
0xFFF6: Decoder is going to enter calibration mode. DSP/MCU sets 2-wire SCLK and
SDIO as input mode.

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4Command
4.1 Single Command
4.2 Multi-write Command
4.1 Single Command
The serial data from DSP/MCU to OID is 8-bit command to set functions of the OID decoder. The
transmission starts with the MSB. The table below lists the single commands and corresponding
values of settings. The OID decoder responds a 16-bit acknowledgement (data + 1) upon receiving
each command. Make sure the time interval between two commands must be greater than 250 ms.
Table 4–1 Command and Setting Value
Command
Description
Value
UserCmd_OIDEnterSuspendMode
OID decoder enters suspend mode; wakes
up by keeping SCLK high over 2 μs
0x57
UserCmd_MinFrameRate_5
OID decoder adjusts sensor frame rate to 5
fps
0x21
UserCmd_MinFrameRate_20
OID decoder adjusts sensor frame rate to
20 fps
0x24
UserCmd_MinFrameRate_30
OID decoder adjusts sensor frame rate to
30 fps
0x25
UserCmd_MinFrameRate_40
OID decoder adjusts sensor frame rate to
40 fps
0x26
UserCmd_MinFrameRate_50
OID decoder adjusts sensor frame rate to
50 fps (default)
0x27
UserCmd_EnablePositionWorkingMode1
OID decoder outputs data once the
decoding result becomes available, valid or
not
0x40
UserCmd_OutputAngleEnable
OID decoder starts to detect angle and
outputs the result from 0°–359°
0x10
UserCmd_OutputAngleDisable
OID decoder stops angle detection
0x11
4.2 Multi-write Command
The DSP/MCU sends a command (0x73) first, and multiple bytes of data one at a time to the OID
decoder. The OID decoder responds a 16-bit acknowledgement (data + 1) upon receiving each set of
data. The DSP/MCU waits for the acknowledgement before sending data again. The length is from
Data1 high byte to Datanlow byte plus the Checksum, 2n+1. Checksum is the low byte of the sum of
all values from Length to Datanlow byte.
Command
Length
Data1
high
byte
Data1
low
byte
Data2
high
byte
Data2
low
byte
…
Datan
high
byte
Datan
low
byte
Check-
sum
Figure 4–1 Multi-write Command
1
Although the OID decoder is in condition to decode continuously, it only outputs the index once even if the same valid data is being read again
on the coded surface. The OID decoder does not output index until a different set of valid data is read. By setting this command, the OID
decoder outputs all indexes even if the data is redundant or invalid.

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Example: Setting PGA gain by multi-write command
The only way to set the value of PGA gain is by multi-write command. There are two options for PGA
gain setting. PGA Gain1 is the default setting. Set PGA Gain2 for brighter base on the same driving
current and IR LED pulse.
Table 4–2 PGA Gain1 Setting
Command
Length
Data1
high byte
Data1
low byte
Data2
high byte
Data2
low byte
Checksum
0x73
0x05
0x16
0xC7
0x00
0x00
0xE2
Table 4–3 PGA Gain2 Setting
Command
Length
Data1
high byte
Data1
low byte
Data2
high byte
Data2
low byte
Checksum
0x73
0x05
0x16
0xC7
0x04
0x70
0x56
Take PGA gain2 as an example, the calculation of length and checksum is demonstrated as below.
Length = 2 * 2 + 1
=5
Checksum = Low Byte of 0x05 + 0x16 + 0xC7 + 0x04 + 0x70
= Low Byte of 0x156
= 0x56

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TERMS AND CONDITIONS
2
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2
The information contained in this document is the property of Sonix, and none of it may be used, reproduced or distributed without the express
written permission by Sonix.

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