Sony DP-IF5000 User manual

– 1 –
SERVICE MANUAL
DP-IF5000
MICROFILM
DIGITAL SURROUND PROCESSOR
SPECIFICATIONS
Modulation System Frequency modulation
Carrier wave frequency Right channel 2.8 MHz
Left channel 2.3 MHz
Transmission distance Approx. 10 m
Frequency response 20 – 20,000 Hz
Distortion rate 1% or less (1 kHz)
Audio inputs Optical input
(square-type) ×1
Analog input (pin jack
right/left) ×1
Power requirements DC 9 V (from the
supplied AC power
adapter)
Dimensions (w/h/d) Approx. 85 ×190 ×180
mm
Mass Approx. 1.0 kg
(1000 g)
Design and specifications are subject to
change without notice.
•DP-IF5000 is the component model block one in
MDR-DS5000.
COMPONENT MODEL NAME FOR MDR-DS5000
DIGITAL SURROUND PROCESSOR DP-IF5000
CORDLESS STEREO HEADPHONES MDR-IF5000
•Manufactured under license from Dolby Laboratories Licensing
Corporation.
DOLBY, the double-D symbol a, “PRO LOGIC”,
“Dolby Digital (AC-3)”, and “VIRTUAL DOLBY DIGITAL” are
trademarks of Dolby Laboratories Licensing Corporation.
Notes on Chip Component Replacement
•Never reuse a disconnected chip component.
•Notice that the minus side of a tantalum capacitor may be dam-
aged by heat.
Ver 1.1 1999. 02
US Model
Canadian Model
AEP Model
UK Model
E Model

– 2 –
TABLE OF CONTENTS
1. GENERAL
Listening to the Sound of a Connected Component ............... 3
2. DISASSEMBLY
2-1. Cover Assy .......................................................................... 5
2-2. Panel Assy, Front................................................................. 5
2-3. Panel Assy, Sub ................................................................... 6
2-4. TX Board ............................................................................ 6
3. SERVICE MODE
3-1. General ................................................................................ 7
3-2. Setting the Test Mode.......................................................... 7
3-3. Releasing the Test Mode ..................................................... 7
3-4. Test Mode ............................................................................ 7
4. ELECTRICAL ADJUSTMENTS................................... 8
5. DIAGRAMS
5-1. Block Diagram –Processor Section–...................................9
5-2. Block Diagram –Transmitter Section–.............................. 11
5-3. Printed Wiring Board
–Processor, Transmitter Section– ...................................... 14
5-4. Schematic Diagram –Processor Section– ......................... 17
5-5. Schematic Diagram –Transmitter Section– ...................... 20
5-6. Printed Wiring Board –LED Section– .............................. 22
5-7. Schematic Diagram –LED Section– ................................. 23
5-8. Printed Wiring Board –Amplifier Section–....................... 25
5-9. Schematic Diagram –Amplifier Section– ......................... 26
5-10. IC Pin Descriptions ........................................................... 29
6. EXPLODEDVIEW........................................................... 34
7. ELECTRICAL PARTS LIST......................................... 35

– 3 –
SECTION 1
GENERAL This section is extracted
from instruction manual.

– 4 –

– 5 –
SECTION 2
DISASSEMBLY
2-1. COVER ASSY
• The equipment can be removed using the following procedure.
Note : Follow the disassembly procedure in the numerical order given.
Set Cover assy Panel assy, front Panel assy, sub
TX board
2-2. PANEL ASSY, FRONT
5 cover assy
3 PTT 2.6X5
2 PTT 2.6X
5
4 PTT 2.6X5
1 PTT 2.6X5
3 lug plate
5 CN103
!º panel assy, front
6 CN901
7 P 3X6
8 P 3X6
4 CN102
9 claws
1 PTT 2.6X5
2 PTT 2.6X5

– 6 –
2-3. PANEL ASSY, SUB
2-4.TX BOARD
3 LED board
4 panel assy, su
b
1 P 2.6X6
2 P 2.6X6
4 TX board
2 PTT 2.6X5
1 P 3X6
3 PTT 2.6X5

– 7 –
SECTION 3
SERVICE MODE
3-1. GENERAL
This set has the test mode of the built-in microprocessor which
allows various check items required repairing.
3-2. SETTINGTHETEST MODE
Press the POWER key and the EFFECT key at the same time and
turn on the power. (Insert the DC plug.)
3-3. RELEASINGTHETEST MODE
Press the POWER key to turn off the power. (Remove the DC plug.)
3-4.TEST MODE
1. LED check
LEDs go on in sequence *1)
All LEDs on
All LEDs off
DEMO key
DEMO key
Go to Key check
*1) In test mode
2. Key check
DEMO key
Go to Audio check
Press each key and its corresponding
LED goes on *2)
*2) Corresponding LEDs
POWER key : POWER LED
INPUT key : ANALOG LED
EFFECT key : MUSIC LED
OUTPUT key : VIRTUAL LED
3. Audio check
DEMO key
DEMO key
DEMO key
Go to IF test tone
ANALOG, HR and HL LEDs on *4) *6)
POWER, DIGITAL,
L and R LEDs on *3)
HL and HR LEDs off *5)
*3) Digital input check : Do not use this in repair.
*4) Analog input check :Other than MUTE check, do not use this
in repair.
*5) Mute mode : Use this in electrical adjustment (see page 8).
*6)
LCR
LS RS
HR LED
HL LED
4. IF test tone
POWER and MUSIC LEDs on
OUTPUT key
OUTPUT key
OUTPUT key
OUTPUT key
OUTPUT key
OUTPUT key
DEMO key
End of Test mode
1 kHz, –10 dBv
1 kHz, –30 dBv
100 Hz, –30 dBv
10 kHz, –30 dBv
1 kHz, FS
L LED on
C LED on
R LED on
RS LED on
LS LED on

– 8 –
TP L
TP R
TP L
TP R
SECTION 4
ELECTRICAL ADJUSTMENTS
Notes:
1. These adjustments are performed in the order that they are
described.
2. Adjustment and measurement are performed for each channel
unless otherwise specified.
3. Adjustment is made for the right channel first and then the left
channel.
4. The power voltage is supplied with 9V.
Oscillation Frequency Adjustment
Setting:
+
–
LED board
TP03 or TP04 (L-ch)
TP05 or TP06 (R-ch)
digital frequency
counter
Adjustment method:
• Perform this adjustment without signal.
1. Connect TP L (L-ch) and TP R (R-ch) to ground on the LED
board (to set the mute state), or use the test mode to set the mute
state (see page 7).
2. Connect a digital frequency counter to TP03 or TP04 for L-ch
and TP05 or TP06 for R-ch on the LED board.
3. Adjust L51 (L-ch) and L1 (R-ch) on the TX board so that the
reading on the digital frequency counter is each within 2.3 MHz
(L-ch) and 2.8 MHz (R-ch).
Specified value:
L-ch L51 2.298 to 2.302 MHz
R-ch L1 2.798 to 2.802 MHz
RF Level Adjustment
Setting:
digital voltmeter
+
–
LED board
TP03 or TP04 (L-ch)
TP05 or TP06 (R-ch)
Adjustment method:
• Perform this adjustment without signal.
1. Connect TP L (L-ch) and TP R (R-ch) to ground on the LED
board (to set the mute state), or use the test mode to set the mute
state (see page 7).
2. Connect a digital voltmeter to TP03 or TP04 for L-ch and TP05
or TP06 for R-ch on the LED board.
3. Adjust RV51 (L-ch) and RV1 (R-ch) on the TX board so that
the reading on the digital voltmeter is 480 mV.
Specified value:
L-ch RV51 477.5 to 482.5 mV
R-ch RV1 477.5 to 482.5 mV
Adjustment Location:
– TX board (side B) –
TP05
TP06
TP03
TP04
TP05
TP06
TP03
TP04
– LED board (conductor side) –
RV51 RF LEVEL
ADJUSTMENT
OSCILLATION
FREQUENCY
ADJUSTMENT
L51
RV1
L1
– TX board (side A) –

– 9 – – 10 – – 11 –
DP-IF5000
5-1. BLOCK DIAGRAM — PROCESSOR SECTION —
– 12 –
SECTION 5
DIAGRAMS
5-2. BLOCK DIAGRAM — TRANSMITTER SECTION —
61 80
SPFRK SDI0
SDI1
SCKR
SCKT
WSR
WST
MISO/SDA BUSY
SI
SCK/SCL
SDB
DIGITAL FRONT LR
79
SBC SDO0
VCCA
VCCD
REAR LR
BCK 64fs
L/R 1fs
95
91
SCKB
SCKA
95
92
WSB
WSA
B+
(+5V)
9
10
12
13
5
4
1
2
8
11
6
3
66
SCKIN MCK 256fs
34
SO
58
GPIO0
89
SI
B+
(+5V)
5
4
2
1
13
12
6
3
11
NAND
IC303
AC-3/PROLOGIC
SURROUND DECODER
IC301
LOGIC 3D
PROCESSOR
IC302
NAND
IC304
SO1
87
SCK
82
RESET
3
SS
64
70 XT1
VCCA
SCK1
CLOCK 12M
51
56 47
70
57
49
55
50
35
41
26
6
•
17 B+
(+5V)
VCCS 40
•
48
B+
(+5V)
VCCQ
9
•
28
•
53
B+
(+5V)
B+
(+5V)
VCCP 30
HREQ 43
CS 42
RESET 36
GPIO3 73
GPIO2 74
GPIO1 75
GPIO0 76
EXTAL 27
B+
(+5V)
P20(SI1)
57 P01
37 P21(SO1)
58 P22(SCK1)
59
P12
49 P11
X1
X2
X1
X2
48
P64
SI1
S01
SCK1
RESET
SSZ11
31
P65 32
P66 33
P67 34
P17 54
P10 47
P24(BUSY) 61
P40 10
P41 11
P42 12
P43 13
P44 14
P50 18
P51 19
P52 20
P27 64
P26
P16
P15
P57
RESET
63
RESET
POWER
SELECT
MODE
EFFECT
DEMO
LEDEN EN
LAT
RES
SCK
MUTE
POWER A
POWER B
RESET
SIN O2
O3
O4
O5
O6
O8
O1
LEDLAT
LEDRES
SCK0
SO0
SW
BLOCK
SW1-5
DISPLAY
LED DRIVE
IC206
15
3
2
13
14 8
9
10
11
12
7
5
RES
SCK
SIN
SO
LAT O2 O3
O4
O5
O6
O7
O1
DISPLAY
LED DRIVE
IC205
13
14
15
3EN
CLK10
RST
BCKIN
LRCK
LR DATA
2
4
8
9
10
11
12
7
6
O8 5
TRANSMITTER
SECTION
2
TRANSMITTER
SECTION
1
DISPLAY
LED DRIVE
D201-208
DISPLAY
LED
D209-214,216
12 13
1 2
5
3
4
11
8 41
V
DD
40
AV
DD
55
42 52
26
35
539
INVERTER
IC203(1/2)
10 6
9
CMOS LOGIC
IC201
CLOCK
Q1
Q3
X201
12.288MHz
6
10
INVERTER
IC203(2/2) B+
(+5V)
TRANSMITTER
SECTION
3
8319 SDA
D OUT
B+
(+3.3V)
6
•
12
•
17
•
30
•
35
•
45
•
55
•
59
•
67
•
81
•
84
•
93
VDD
B+
(+3.3V)
DIGITAL
AUDIO
INTERFACE
(1/2)
DECIMATION
FILTER
DELTA
SIGMA
MODULATOR
ANALOG
FRONT END
ANALOG
FRONT END
+
–
+
–
V IN L
V IN R
1
6
19
A/D CONVERTER
IC102 (1/2)
+
–
+
–
3
2
6
5
1
6
LINE AMP
IC101
ATT SW
Q101
ATT SW
Q102
B+
(+9V)
SW101
ATT
0dB
–6dB
ANALOG L
ANALOG R
L
R
LINE INPUT
J101
–1
–2
1
3
OUT
VCC
OPTICAL
RECEIVER
MODULE
IC305
DIGITAL IN B+
(+5V)
DIGITAL
: DIGITAL
Signal path
PROGRAM,
SYSTEM
CONTROL
IC105
: ANALOG
PROCESSOR
SECTION
1DIGITAL
AUDIO
INTERFACE
(2/2)
+
–
+
–
LR DATA
PROCESSOR
SECTION 2
LRCK
BCK IN
CLK10
RST
INTERPOLATION
FILTER DELTA SIGMA MODULATION
CLK/OSC
MANAGER
RESET
BIAS
LPF
&
BUFFER
LPF
&
BUFFER
V OUT L
V COM
V OUT R
BINAURAL L
BINAURAL R
+
18
16
17
22
28
11
12
15
D/A CONVERTER
IC102 (2/2)3
21
7
5
6
+
–
+
–
5
67
1
3
2
MUTE
Q31
MUTE
Q32
MUTE
Q901
MUTE
Q902
MUTING
SW
Q33,34
PROCESSOR
SECTION 3
MUTE
POWER A
POWER B
RESET
BINAURAL R
B+ (SW+5V)
BINAURAL L
13
9
1
7
RV901
PHONES
LEVEL
HEADPHONES
AMP
IC901
J901
PHONES
+9V
REG
IC805
B+
(+9V)
LF801
B+
(SW+9V)
B+
(SW+5V)
B+
(+5V)
+9V
REG
IC804
SW+9V
REG
Q803
RESET
IC204 +5V
REG
IC801
+5V
REG
IC802
+3.3V
REG
IC803
B+
(+3.3V)
J801
DC IN 9V
AFC
IC1
AUDIO AMP
IC103
6
4
2
6
4
2
L51
FREQUENCY
(L-CH)
RV51
RF LEVEL
(L-CH)
2.3MHz OSC
COIL
L1
FREQUENCY
(R-CH)
2.8MHz OSC
COIL
OSC
Q51
OSC
Q1
BUFFER
Q52 LED
DRIVE
Q301,351
LED
DRIVE
Q302,352
RV1
RF LEVEL
(R-CH)
BUFFER
Q2
REG
SWITCH
Q35, 36
B+
(+9V)
B+
(+9V)
INFRARED
EMITTER
D301-304
INFRARED
EMITTER
D305-308
D1
D51
DIN
• Signal path
: DIGITAL
: ANALOG
: RF
-1
L
-2
R

– 13 – – 14 – – 15 – – 16 –
DP-IF5000
5-3. PRINTEDWIRING BOARD — PROCESSOR,TRANSMITTER SECTION —
TP L
TP R
( ) ( )
1
A
B
C
D
E
F
G
H
I
2345678910111213141516171819202122
Note:
•X: parts extracted from the component side.
•®: Through hole.
•b: Pattern from the side which enables seeing.
(The other layer’s patterns are not indicated.)
Caution:
Pattern face side: Parts onthe pattern face side seenfrom the
(Side B) pattern face are indicated.
Parts face side: Parts on the par ts faceside seen from the
(Side A) parts face are indicated.
D1 G-3
D51 F-3
D101 H-9
D102 H-9
IC1 F-4
IC101 F-9
IC102 F-6
IC103 E-8
IC105 B-3
IC201 D-2
IC202 D-3
IC204 E-4
IC301 C-7
IC302 C-5
IC303 D-6
IC304 E-6
(IC305) C-12
(IC801) H-14
(IC802) I-7
(IC803) C-12
(IC804) I-14
(IC805) H-17
Q1 G-3
Q2 H-2
Q31 F-3
Q32 G-3
Q33 F-5
Q34 F-4
Q35 G-4
Q36 G-5
Q51 F-3
Q52 F-2
Q101 F-9
Q102 G-9
Q803 H-8
• Semiconductor
Location
Ref. No. Location
( ) : SIDE B
(Page 25)
(Page 22)
(Page 22)

– 17 – – 18 – – 19 –
DP-IF5000
5-4. SCHEMATIC DIAGRAM — PROCESSOR SECTION — • Refer to page 27 for IC Block Diagrams.
B
Note:
• All capacitors are in µF unless otherwise noted. pF: µµF
50 WV or less are not indicated except for electrolytics
and tantalums.
• All resistors are in Ωand 1/4W or less unless otherwise
specified.
•C: panel designation.
•U: B+ Line.
• Total current is measured with Power ON/OFF mode.
• Power voltage is dc 9 V and fed with regulated dc power
supply from external power voltage jack.
• Voltage and waveforms are dc with respect to ground
under no-signal conditions.
no mark : POWER ON
∗: Impossible to measure
• Voltagesare takenwith aVOM(Inputimpedance 10 MΩ).
Voltage variations may be noted due to normal produc-
tion tolerances.
• Waveforms are taken with a oscilloscope.
Voltage variations may be noted due to normal produc-
tion tolerances.
• Circled numbers refer to waveforms.
• Signal path.
F: ANALOG
c: DIGITAL
•Waveforms
1
2
3
4
5
IC102 !§ (LRCK)
IC202 2
IC301 (¡ (SCKA)
IC301 (™ (WSA)
6
IC302 @¶ EXTAL
5Vp-p
80µsec
6.2Vp-p
IC102 !¶ (BCKIN)
4.5Vp-p
1.3µsec
12.288MHz
4Vp-p
13µsec
3.4Vp-p
80µsec
6.2Vp-p
0.7µsec
(Page 20)
(Page
26)
(Page 20)
(Page 23)

– 20 – – 21 – – 22 –
DP-IF5000
5-5. SCHEMATIC DIAGRAM —TRANSMITTER SECTION — • Refer to page 27 for IC Block Diagrams.
B
TP05
TP06
TP03
TP04
D301-304
INFRARED
EMITTER
(L-CH)
D305-308
INFRARED
EMITTER
(R-CH)
1
A
B
C
D
E
F
G
H
I
23456
5-6. PRINTEDWIRING BOARD — LED SECTION —
Note:
• All capacitors are in µF unless otherwise noted. pF: µµF
50 WV or less are not indicated except for electrolytics
and tantalums.
• All resistors are in Ωand 1/4W or less unless otherwise
specified.
•U: B+ Line.
•H: adjustment for repair.
• Power voltage is dc 9V and fed with regulated dc power
supply from external power voltage jack.
• Voltage is dc with respect to ground under no-signal
condition.
no mark : POWER ON
• Voltagesare taken with a VOM(Inputimpedance10 MΩ).
Voltage variations may be noted due to normal produc-
tion tolerances.
• Signal path.
F: ANALOG
J: RF
Note:
•X: parts extracted from the component side.
•b: Pattern from the side which enables seeing.
D201 A-4
D202 C-5
D203 C-5
D204 H-5
D205 F-5
D206 E-5
D207 F-5
D208 F-4
D209 F-3
D210 G-4
D211 G-3
D212 H-5
D213 H-3
D214 D-5
D216 D-5
D301 A-6
D302 C-6
D303 E-6
D304 G-6
D305 A-2
D306 C-2
D307 E-2
D308 G-2
IC205 B-3
IC206 E-3
Q301 F-5
Q302 G-2
Q351 G-5
Q352 H-2
• Semiconductor
Location
Ref. No. Location
(Page
17)
(Page 23)
(Page 16)
(Page 16)
(Page 25)

5-7. SCHEMATIC DIAGRAM — LED SECTION — • Refer to page 28 for IC Block Diagrams.
– 23 – – 24 –
DP-IF5000
Note:
• All capacitors are in µF unless otherwise noted. pF: µµF
50 WV or less are not indicated except for electrolytics
and tantalums.
• All resistors are in Ωand 1/4W or less unless otherwise
specified.
•C: panel designation.
•U: B+ Line.
• Power voltage is dc 9V and fed with regulated dc power
supply from external power voltage jack.
• Voltage is dc with respect to ground under no-signal
condition.
no mark : POWER ON
∗: Impossible to measure
• VoltagesaretakenwithaVOM(Inputimpedance10 MΩ).
Voltage variations may be noted due to normal produc-
tion tolerances.
• Signal path.
J: RF
(Page 26)
(Page 21)
(Page 19)

DP-IF5000
– 25 – – 26 –
5-8. PRINTEDWIRING BOARD — AMPLIFIER SECTION —
Note:
•X: parts extracted from the component side.
•b: Pattern from the side which enables seeing.
5-9. SCHEMATIC DIAGRAM — AMPLIFIER SECTION —
RV901
PHONES
LEVEL
-2
R
-1
L
1
A
B
C
D
E
23456
Note:
• All capacitors are in µF unless otherwise noted. pF: µµF
50 WV or less are not indicated except for electrolytics
and tantalums.
• All resistors are in Ωand 1/4W or less unless otherwise
specified.
•C: panel designation.
•U: B+ Line.
• Power voltage is dc 9V and fed with regulated dc power
supply from external power voltage jack.
• Voltage is dc with respect to ground under no-signal
condition.
no mark : POWER ON
• VoltagesaretakenwithaVOM(Inputimpedance10 MΩ).
Voltage variations may be noted due to normal produc-
tion tolerances.
• Signal path.
F: ANALOG
IC901 D-4
Q901 B-2
Q902 B-2
• Semiconductor
Location
Ref.No. Location
(Page 15)
(Page 22)
(Page 23)
(Page 17)

– 27 –
• IC Block Diagrams
IC1 BA3308F-E2
IC202 TC74VHCU04FT (EL)
IC201 TC74VHC4040FT (EL)
IC102 PCM3001E-T2
IC303, 304 TC74VHCT08AFT (EL)
OUT
GND
NC
ALC
VCC
NC
OUT
NC
IN
NC
NF
NF
IN
NC
1
2
3
4
5
6
78
9
10
11
12
13
14
128
27
26
25
24
23
22
21
20
19
18
17
16
15
RSTB
FMT0
FMT1
FMT2
DGND
VDD
CLKIO
XTO
XTI
DOUT
DIN
BCKIN
LRCIN
VOUTL
2
3
4
5
6REFERENCE
ANALOG
FRONT-END
DELTA SIGMA MODULATOR
CLK/OSC
MANAGER FORMAT CONTROL
INTERFACE
DECIMATION
FILTER
INTER-
POLATION
FILTER
DIGITAL
AUDIO
INTER-
FACE
ANALOG
FRONT-END
7
8
9
10
11
12
13
14
VINL
VCC1
AGND1
VREFL
VREFR
VINR
CINPR
CINNR
CINNL
CINPL –+–+
VCOM
VOUTR
AGND2
VCC2
DELTA SIGMA MODULATOR
BIAS
LPF &
BUFFER LPF & BUFFER
RESET
Q
QR
TQ
QR
TQ
QR
TQ
QR
T
TR TR T
Q
R
QQQQQ
T
Q
RTR
QQTR QQTR QQ
T
R
QQ
1516 14 13 12 11 10 9
CLOCKRESETQ9Q1Q8Q10Q11VDD
21 3 4 5 6 7 8
VSSQ2Q3Q4Q7Q5Q6Q12
14 13 12 11 10 9 8
1 2 3 4 5 6 7
VCC
GND
1
2
3
4
5
6
78
9
10
11
12
13
14
1A
1B
1Y
2A
2B
2Y
GND
VCC
4B
4A
4Y
3B
3A
3Y

– 28 –
IC205, 206 µPD6345GS
IC204 RN5VL42AA-TL
IC305 TORX176
IC801 TA7805S
IC802 PQ05RD11
IC804, 805 PQ09RD11
IC803 BA033T
S8S7S6S5S4S3S2S1
P8P7P6P5P4P3P2P1
100k
100k
100k
100k
100k
2
1
3
4
5
6
7
8
O8
O7
O6
O5
LAT
EN
Vss
SO 13
12
11
10
9
14
15
16
O1
SIN
SCK
RES
VDD
O2
O3
O4
1 2 3
OUT VDD GND
+
–
VREF
132
IN GND OUT
+
–
REFERENCE
VOLTAGE
OCCURENCE
CIRCUIT
GND
AMP
CIRCUIT
GND
ATC CIRCUIT
CONVERTER
4 3 2 1
GND VCC GND OUT
EXCLUSIVE
IC
321 4
VIN VOUT GND VC
+
–
REFERENCE
VOLTAGE
1 2 3
VCC GND OUT

– 29 –
• IC105 µPD78P018F (PROGRAM, SYSTEM CONTROL)
Pin No. Pin Name I/O Pin Description
1 – 8 P30 – 37 — Not used. (open)
9V
SS — Ground
10 P40 I POWER ON/OFF key signal input L: ON
11 P41 I INPUT key signal input L: ON
12 P42 I OUTPUT key signal input L: ON
13 P43 I EFFECT key signal input L: ON
14 P44 I DEMO key signal input L: ON
15 P45 — Not used. (open)
16 P46 I/O Test pin Not used. (open)
17 P47 — Not used. (open)
18 P50 O LED EN signal output
19 P51 O LED LAT signal output
20 P52 O LED reset signal output
21, 22 P53, 54 — Not used. (open)
23 P55 O POWER LED signal output Not used. (open)
24 VSS — Ground
25 P56 — Not used. (open)
26 P57 O IF circuit power supply control signal output L: OFF, H: ON
27 – 30 P60 – 63 — Not used. (open)
31 P64 O DSP GPIO0 (VR ON/OFF) signal output H: OFF, H: ON
32 P65 O DSP GPIO1 (data change) signal output Not used. (open)
33 P66 I DSP GPIO2 (audio input zero flag) signal input L: ON
34 P67 O DSP GPIO3 (REAR through) signal output H: REAR through, L: Normal
35 RESET I System reset signal input
36 P00 — Ground
37 P01 I Decoder source type change flag signal input H: Pulse
38, 39 P03, 04 — Not used. (open)
40 VDD — Power supply pin (+5V)
41 X2 I Connect to crystal for main system clock oscillator.
42 X1 I Connect to crystal for main system clock oscillator.
43 IC — Connect to internal. (Connect to AVSS.)
44 XT2 — Not used. (open)
45 XT1 — Not used. (Connect to VDD.)
46 AVSS — Ground (Ground potential of A/D converter.)
47 P10 O Serial select signal output L: ON
48 P11 O Decoder serial select signal output L: ON
49 P12 O SLAVE reset signal output L: ON
50 P13 O De-emphasis control 0 signal output
51 P14 O De-emphasis control 1 signal output
52 P15 O Peripheral set power supply control signal output L: OFF, H: ON
53 P16 O Mute ON/OFF signal output L: OFF, H: ON
54 P17 O DSP reset signal output L: ON
55 AVDD — Power supply pin (+5 V) (Analog power supply of A/D converter.)
56 AVREF — Ground
57 P20 (SI1) I Main serial data signal input
58 P21 (SO1) O Main serial data signal output
59 P22 (SCK1) O Main serial clock signal output
60 P23 O Not used. (open)
61 P24 (BUSY) I Main serial busy signal input
62 P25 I Not used. (open)
63 P26 O LED serial data signal output
64 P27 O LED serial clock signal output
5-10. IC PIN DESCRIPTIONS

– 30 –
• IC301 ZR38600PQC-RCB7A (AC-3/PROLOGIC SURROUND DECODER)
Pin No. Pin Name I/O Pin Description
1 A0 — Not used. (open)
2 GND — Ground
3 SS I Host serial interface slave select signal input
4 TMS — Not used. (Connect to ground.)
5 INT I External interference request signal input
6V
DD — Power supply pin (+3.3 V)
7 R14/RDY — Not used. (open)
8 GND — Ground
9 – 11 A1 – 3 — Not used. (open)
12 VDD — Power supply pin (+3.3 V)
13 D13/C/B — Not used. (open)
14 GPIO5 — Not used. (open)
15 D12/ERR — Not used. (open)
16 A4 — Not used. (open)
17 VDD — Power supply pin (+3.3 V)
18 GPIO4 — Not used. (open)
19 GND — Ground
20, 21 A5, A6 — Not used. (open)
22 D11/PP7 — Not used. (open)
23 GPIO3 — Not used. (open)
24, 25 A7, A8 — Not used. (open)
26 D10/PP6 — Not used. (open)
27, 28 A9, A10 — Not used. (open)
29 GND — Ground
30 VDD — Power supply pin (+3.3 V)
31 A11 — Not used. (open)
32 D9/PP5 — Not used. (open)
33 D8/PP4 — Not used. (open)
34 SO O Host serial interface data signal output
35 VDD — Power supply pin (+3.3 V)
36 SELECT — Not used. (open)
37 GND — Ground
38 A12 — Not used. (open)
39 TBO — Not used. (open)
40 A13 — Not used. (open)
41 D7/PP3 — Not used. (open)
42 D6/PP2 — Not used. (open)
43 A14 — Not used. (open)
44 GND — Ground
45 VDD — Power supply pin (+3.3 V)
46 A15 — Not used. (open)
47 D5/PP1 — Not used. (open)
48 D4/PP0 I/O Resemblance port data bus signal of external memory select and resemblance port
input/output.
49 A16 — Not used. (open)
50 RD I/O External memory read possible signal input/output
51 WR I/O External memory wright possible signal input/output
52 CS I/O External memory chip select signal input/output
53 GND — Ground
54 SDD — Not used. (open)
55 VDD — Power supply pin (+3.3 V)
56 GPIO2 — Not used. (open)

– 31 –
Pin No. Pin Name I/O Pin Description
57 GPIO1 — Not used. (open)
58 GPIO0 O General service programing signal output
59 VDD — Power supply pin (+3.3V)
60 BYPASS — Not used. (Connect to ground.)
61 SPFRX I S/P DIF receive input port
62 P/M I Resemblance input/output, resemblance port memory select signal input. Decide to
time of reset.
63 XTO — Not used. (open)
64 XTI I External system clock signal input
65 GND — Ground
66 SCKIN O Serial master clock signal output
67 VDD — Power supply pin (+3.3V)
68 GNDA— Analog ground
69 FLTAP I External filter capacitor connect pin
70 VCCA — Analog power supply pin (+3.3V)
71 GND — Ground
72 CLKOUT — Not used. (open)
73, 74 D19, D18 — Not used. (open)
75 – 77 A17 – A19 — Not used. (open)
78 GND — Ground
79 SDC O Serial L/R surround data signal output
80 SDB O Serial L/R data signal output
81 VDD — Power supply pin (+3.3V)
82 RESET I Reset signal input
83 SDA I Audio L/R data signal input
84 VDD — Power supply pin (+3.3V)
85 SDE — Not used. (open)
86 TCK — Not used. (Connect to ground.)
87 SCK I Serial interface clock signal input
88 TBI — Not used. (Connect to ground.)
89 SI I Host serial interface data signal input
90 GND — Ground
91 SCKA O Serial clock data signal output
92 WSA O Word select, frame synchronize output port.
93 VDD — Power supply pin (+3.3V)
94 SDF — Not used. (Connect to ground.)
95 WSB O Word select, frame synchronize output port.
96 D17 — Not used. (open)
97 SCKB O Serial clock data signal output
98 D16 — Not used. (open)
99 SPFTX/SDG — Not used. (Connect to ground.)
100 D15 — Not used. (open)

– 32 –
• IC302 DSP56009FJ (LOGIC 3D PROCESSOR)
Pin No. Pin Name I/O Pin Description
1 GNDA— Ground
2 MCS0 — Not used. (open)
3 MA15/MCS3 — Not used. (open)
4 MA14 — Not used. (open)
5 MA13 — Not used. (open)
6V
CCA — Power supply pin (+5 V)
7 MA12 — Not used. (open)
8 GNDA— Ground
9V
CCQ — Power supply pin (+5 V)
10 GNDQ— Ground
11 – 14 MA11 – 8 — Not used. (open)
15 GNDA— Ground
16 MA7 — Not used. (open)
17 VCCA — Power supply pin (+5 V)
18 – 20 MA6 – 4 — Not used. (open)
21 GNDA— Ground
22 – 25 MA3 – 0 — Not used. (open)
26 SCK/SCL I Main serial clock signal input
27 EXTAL I Main serial clock 1.5 MHz signal input
28 VCCQ — Power supply pin (+5 V)
29 GNDQ— Ground
30 PINIT — Not used. (Connect to ground.)
31 GNDP— Ground
32 PCAP — Ground
33 VCCP — Power supply pin (+5 V)
34 GNDS— Ground
35 MISO/SDA I Main serial data signal input
36 RESET I Reset signal input L: reset
37 MODA/IRQA — Mode set up pin
38 MODB/IRQB — Mode set up pin
39 MODC/NMI — Mode set up pin
40 VCCS — Power supply pin (+5 V)
41 SI I Main serial data signal input
42 CS I Serial select signal input
43 HREQ O Main serial busy signal input
44 GNDS— Ground
45 SDO2 — Not used. (open)
46 SDO1 — Not used. (open)
47 SDO0 O Audio L/R data signal input
48 VCCS — Power supply pin (+5 V)
49 SCKT I Audio bit clock signal input
50 WST I Audio bit clock signal input
51 SCKR I Audio bit clock signal input
52 GNDQ— Ground
53 VCCQ — Power supply pin (+5 V)
54 GNDS— Ground
55 WSR I Audio L/R clock signal input
56 SDI1 I Rear L/R signal input
57 SDI0 I Front L/R signal input
58 DS0 — Not used. (open)
59 DSI/OS0 — Mode set up pin
60 DSCK/OS1 — Mode set up pin