Spectrum Digital TMS320DM642 Use and care manual

TMS320DM642 Evaluation
Module with TVP Video Decoders
2004 DSP Development Systems
Reference
Technical

TMS320DM642 Evaluation Module
With TVP Video Decoders
Technical Reference
507345-0001 Rev. B
December 2004
SPECTRUM DIGITAL, INC.
12502 Exchange Drive, Suite 440 Stafford, TX. 77477
Tel: [phone] Fax: [phone]
[email protected] www.spectrumdigital.com

IMPORTANT NOTICE
Spectrum Digital, Inc. reserves the right to make changes to its products or to discontinue any
product or service without notice. Customers are advised to obtain the latest version of relevant
information to verify that the data being relied on is current before placing orders.
Spectrum Digital, Inc. warrants performance of its products and related software to current
specifications in accordance with Spectrum Digital’s standard warranty. Testing and other quality
control techniques are utilized to the extent deemed necessary to support this warranty.
Please be aware that the products described herein are not intended for use in life-support
appliances, devices, or systems. Spectrum Digital does not warrant nor is Spectrum Digital liable for
the product described herein to be used in other than a development environment.
Spectrum Digital, Inc. assumes no liability for applications assistance, customer product design,
software performance, or infringement of patents or services described herein. Nor does Spectrum
Digital warrant or represent any license, either express or implied, is granted under any patent right,
copyright, or other intellectual property right of Spectrum Digital, Inc. covering or relating to any
combination, machine, or process in which such Digital Signal Processing development products or
services might be or are used.
WARNING
This equipment is intended for use in a laboratory test environment only. It generates, uses, and can
radiate radio frequency energy and has not been tested for compliance with the limits of computing
devices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonable
protection against radio frequency interference. Operation of this equipment in other environments
may cause interference with radio communications, in which case the user at his own expense will be
required to take whatever measures necessary to correct this interference.
Copyright © 2004 Spectrum Digital, Inc.

Contents
1 Introduction to the DM642 Evaluation Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Provides you with a description of the DM642 Evaluation Module, key features, and
block diagram.
1.1 Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.2 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.3 Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.4 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.5 Configuration Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.6 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
2 Board Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Describes the operation of the major board components on the DM642 Evaluation Module.
2.1 EMIF Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.1.1 SDRAM Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.1.2 Flash Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.1.3 UART Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.1.4 FPGA Asynchronous Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.1.5 FPGA Synchronous Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.1.6 EMIF Buffer/Decoder Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.2 Video Port/McASP Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.2.1 Video Decoder Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.2.2 Video Encoder Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.2.3 FPGA Video Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.2.4 AIC23B Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.2.5 Audio PLL/VCXO Circuit/PLL1708 Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.3 PCI/HPI/Ethernet Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.3.1 PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.3.2 PCI EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.3.3 Ethernet Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2.3.4 HPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2.4 I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.5 SPDIF Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.6 Daughter Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2.7 Programming the FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2.8 DM642 Core CPU Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2.9 HDTV Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

3 Physical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Describes the physical layout of the DM642 Evaluation Module and its connectors.
3.1 Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.2 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.2.1 J1, S-Video Out Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3.2.2 J2, Video Out - Red and Pr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3.2.3 J3, Video Out - Green and Y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
3.2.4 J4, Video Out - Blue and Pb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
3.2.5 J5, PC Video Output Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.2.6 J6, FPGA Programming Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.2.7 J7, JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.2.8 J8, Ethernet Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.2.9 J9, Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.2.10 J10, +5 Volt Input Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.2.11 J11, J12, RS-232 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.2.12 J13, Microphone/Audio Input Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
3.2.13 J14, Audio Line Output Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
3.2.14 J15, Capture Port 1 Video Input Connector . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
3.2.15 J16, Capture Port 1 S-Video Input Connector . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
3.2.16 J17, Capture Port 1 Composite Video Input Connector . . . . . . . . . . . . . . . . . 3-13
3.2.17 J18, Capture Port 2 Composite Video Input Connector . . . . . . . . . . . . . . . . . . 3-14
3.2.18 J19, 60 Pin Emulation Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
3.2.19 J20, P2 PCI Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
3.2.20 DC_P1, Video Port 2/Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17
3.2.21 DC_P2, Video Port 0 and Video Port 1 Expansion . . . . . . . . . . . . . . . . . . . . . 3-18
3.2.22 DC_P3, EMIF Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
3.3 User LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
3.4 System Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
3.5 Reset Switch - S3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
3.6 Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
A Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
Contains the schematics for the DM642 Evaluation Module
B Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
Contains the mechanical information about the DM642 Evaluation Module

About This Manual
This document describes the board level operations of the TMS320DM642 Evaluation
Module (EVM). The EVM is based on the Texas Instruments TMS320DM642 Digital
Signal Processor.
The DM642 Evaluation Module is a table top or PCI plug-in card that allows engineers
and software developers to evaluate certain characteristics of the TMS320DM642 DSP
to determine if the processor meets the designers application requirements. Evaluators
can create software to execute on board or expand the system in a variety of ways.
Notational Conventions
This document uses the following conventions.
The DM642 Evaluation Module will sometimes be referred to as the DM642 EVM or
EVM.
Program listings, program examples, and interactive displays are shown in a special
italic typeface. Here is a sample program listing.
equations
!rd = !strobe&rw;
Information About Cautions
This book may contain cautions.
This is an example of a caution statement.
A caution statement describes a situation that could potentially damage your software,
or hardware, or other equipment. The information in a caution is provided for your
protection. Please read each caution carefully.

Related Documents
Below are descriptions of the .pdf files. Refer to the Texas Instruments web page
(http://www.ti.com) for the latest revisions of these documents.
Application Notes & User Guides
spra920.pdf: DM642 EVM Daughter card Interface Specification
sprs200b.pdf: TMS320DM642 Video/Imaging Fixed-Point Digital Signal Processor
spru041b.pdf: TMS320C6000 DSP Multichannel Audio Serial Port (McASP) Reference
Guide
spru175a.pdf: TMS320C6000 DSP Inter-Integrated Circuit (I2C) Module Reference
Guide
spru190d.pdf: TMS320C6000 Peripherals Reference Guide
spru295.pdf: TMS320DM642 EVM OSD FPGA User’s Guide
spru610.pdf: TMS320C64x DSP Two-Level Internal Memory Reference Guide
spru628.pdf: TMS320C6000 DSP Ethernet Media Access Controller
(EMAC)/Management Data Input/Output (MDIO) Module Reference Guide
spru629.pdf: TMS320C64x DSP Video Port/VCXO Interpolated Control (VIC) Port
Reference Guide

Table 1: Manual History
Revision History
A Production Release
B Updated for HD Filters
Table 2: Board History
Revision History
A Prototype Release
B Production Release

1-1
Chapter 1
Introduction to the
TMS320DM642 EVM
Chapter One provides a description of the TMS320DM642 EVM along
with the key features and a block diagram of the circuit board.
Topic Page
1.1 Key Features 1-2
1.2 Functional Overview 1-3
1.3 Basic Operation 1-4
1.4 Memory Map 1-5
1.5 Configuration Switch Settings 1-6
1.6 Power Supply 1-7

Spectrum Digital, Inc
1-2 TMS320DM642 EVM Technical Reference
1.1 Key Features
The DM642 EVM is a low-cost standalone development platform that enables users to
evaluate and develop applications for the TI C64xx DSP family. The EVM also serves
as a hardware reference design for the TMS320DM642 DSP. Schematics, logic
equations and application notes are available to ease hardware development and
reduce time to market.
The EVM comes with a full complement of on board devices that suit a wide variety of
application environments. Key features include:
• A Texas Instruments TMS320DM642 DSP operating at 720 MHz.
• Standalone or standard PCI computer slot operation
• 3 video ports with 2 on board decoders and 1 on board encoder
• 32 Mbytes of synchronous DRAM
• On Screen display (OSD) via FPGA
• 4 Mbytes of non-volatile Flash memory
• AIC23B stereo codec
• Ethernet interface
• Software board configuration through registers implemented in FPGA
• Configurable boot load options
• JTAG emulation through on-board external emulator interface
Figure 1-1, Block Diagram DM642 EVM
PWR
MIC IN
LINE IN
LINE OUT
AIC23
Codec
Comp IN 1
SVHS
IN1
Comp IN 2
Comp IN 3
Red
Output
SVHS
OUT
Green
Output
Blue
Output
VGA/
RGB
Output
OSD
FPGA
Video
Decoder
1
Video
Decoder
2
Video
Encoder
SDRAM SDRAM Flash
Dual
UART
64 EMIF
Video Port 0
Video Port 1
Video
Port 2 McASP0
PCI Connector
I/O 3.3V
DSP 1.4V
FPGA 1.8V
ENET
PHY
8
8
I2C
EEPROM
VCXO APLL
I2C Bus
LEDs FPGA
DONE
JTAG
RS-232
Port A
RS-232
Port B
PCI
Config
32
12
PCIEEAI
ENDIAN
S2
12
BTMD0 BTMD1
S1
PCI/HPI S/PDIF
DM642

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1-3
• 8 user LEDs
• Single voltage power supply (+5V)
• Expansion connectors for daughter card use
• Dual UART with RS-232 drivers
1.2 Functional Overview of the TMS320DM642 EVM
The DSP on the DM642 EVM interfaces to on-board peripherals through the 64-bit
wide EMIF or one of the three 8/16 bit wide video ports. The SDRAM, Flash, FPGA,
and UART are each connected to one of the busses. The EMIF bus is also connected
to the daughter card expansion connectors which are used for add-in boards.
On board video encoders and decoders interface to the video ports and expansion
connectors. Two decoders and one encoder are standard on the EVM. On screen
display functions are implemented in an external FPGA which resides between the
output video port and the video decoder.
An on-board AIC23B codec allows the DSP to transmit and receive analog audio
signals. I2C bus is used for the codec control interface and the McASP is used for data.
Analog interface is done through three 3.5mm audio jacks that correspond to
microphone input, line input, and line output. The codec can select the microphone or
the line input as the active input. The analog output is driven to the line out (fixed gain)
connector. The McASP can be re-routed to the expansion connectors in software.
A programmable gate array called an FPGA is used to implement glue logic that ties
the board components together. The FPGA also has a register based software user
interface that lets the user configure the board by reading and writing to these registers.
The EVM includes 8 LEDs which can be used to provide the user with interactive
feedback. These LEDs are accessed by reading and writing to the FPGA registers.
An included 5V external power supply is used to power the board for stand alone
applications whereas the PC bus supplies power when used as a PCI plug in card.
On-board switching voltage regulators provide the 1.4V DSP core voltage and 3.3V I/O
supplies. The board is held in reset until these supplies are within operating
specifications. The EVM also has an LDO regulator which provides +1.8 volt FPGA
core voltage, and +3.3 volt encoder and decoder supplies.
Code Composer communicates with the EVM through an external emulator via the
14 pin or 60 pin external JTAG connectors.

Spectrum Digital, Inc
1-4 TMS320DM642 EVM Technical Reference
1.3 Basic Operation
The EVM is designed to work with TI’s Code Composer Studio development
environment. Code Composer communicates with the board through an external JTAG
emulator. To start, follow the instructions in the Quick Start Guide to install Code
Composer. This process will install all of the necessary development tools,
documentation and drivers.
Detailed information about the EVM including examples and reference material is
available on the EVM’s CD-ROM.

Spectrum Digital, Inc
1-5
1.4 Memory Map
The C64xx family of DSPs has a large byte addressable address space. Program code
and data can be placed anywhere in the unified address space. Addresses are always
32-bits wide.
The memory map shows the address space of a generic DM642 processor on the left
with specific details of how each region is used on the right. By default, the internal
memory sits at the beginning of the address space. Portions of memory can be
remapped in software as L2 cache rather than fixed RAM.
The EMIF (External Memory Interface) has 4 separate addressable regions called
chip enable spaces (CE0-CE3). The SDRAM occupies CE0 while the Flash, UART,
and FPGA are mapped to CE1. Daughter cards use CE2 and CE3. CE3 is configured
for synchronous operation for on screen display functions and other synchronous
registers implemented in the external FPGA.
Internal Memory/Cache
DM642 EVM
Reserved
or
Peripheral
SDRAM
Flash
UART/FPGA Regs
Daughter
Card
FPGA Sync Regs
Daughter Card
Generic DM642
Address Space
Address
0x00000000
0x00040000
0x80000000
0x90000000
0xA0000000
0xB0000000
Internal Memory/Cache
EMIF CE0
EMIF CE1
EMIF CE2
EMIF CE3
Reserved Space
or
Peripheral Registers
Figure 1-2, Memory Map, DM642 EVM

Spectrum Digital, Inc
1-6 TMS320DM642 EVM Technical Reference
1.5 Configuration Switch Settings
The EVM has two 2 position configuration switches that allow users to control the
operational state of the DSP when it is released from reset. The configuration switches
are labeled S1 and S2 on the EVM board.
Switch 1 configures the boot mode that will be used when the DSP starts executing. By
default the switches are configured to EMIF boot (out of 8-bit Flash) in little endian
mode. The table below shows the settings for switch S1.
Configuration switch 2 controls the endianness of the DSP and PCI ROM enable. The
tables below shows the settings for switch S2.
* Default as shipped configuration
Table 1: Configuration Switch S1 Settings
S1-2 S1-1 Configuration Description
Off Off No Boot
Off On HPI/PCI Boot
On Off Reserved
On * On * EMIF boot from 8-bit Flash
Table 2: Configuration Switch S2-1 Settings
S2-1 Configuration Description
Off PCI EEPROM Disabled
On * PCI EEPROM Enabled
Table 3: Configuration Switch S2-2 Settings
S2-1 Configuration Description
Off * Little Endian Mode
On Big Endian Mode

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1-7
1.6 Power Supply
The EVM operates from a single +5V external power supply connected to the main
power input (J5) or from the PCI slot. Internally, the +5V input is converted into +1.4V
and +3.3V using Texas Instruments swift voltage regulators. The +1.4V supply is used
for the DSP core while the +3.3V supply is used for the DSP's I/O buffers and all other
chips on the board. The power connector is a 2.5mm barrel-type plug. LDO voltage
regulators are used to generate the FPGA core voltage, and video input and output
voltages.
There are five power test points on the EVM at TP4, TP8, TP13, TP15, and TP16.
These test points provide a convenient mechanism to check the EVM’s multiple power
supplies. The table below shows the voltages for each test point and what the supply is
used for.
Table 4: Power Test Points
Test Point Voltage Voltage Use
TP4 +1.4 V DSP Core
TP8 +3.3 V DSP I/O and logic
TP13 +1.8 V FPGA
TP15 +3.3 V Video encoder
TP16 +1.8 V Video decoder

Spectrum Digital, Inc
1-8 TMS320DM642 EVM Technical Reference

2-1
Chapter 2
Board Components
This chapter describes the operation of the major board components on
the TMS320DM642 EVM.
Topic Page
2.1 EMIF Interfaces 2-2
2.1.1 SDRAM Memory Interface 2-2
2.1.2 Flash Memory Interface 2-4
2.1.3 UART Interface 2-5
2.1.4 FPGA Asynchronous Memory Interface 2-5
2.1.5 FPGA Synchronous Memory Interface 2-6
2.1.6 EMIF Buffer/Decoder Control 2-6
2.2 Video Port/McASP Interfaces 2-7
2.2.1 Video Decoder Ports 2-7
2.2.2 Video Encoder Port 2-7
2.2.3 FPGA Video Functions 2-8
2.2.4 AIC23B Interface 2-9
2.2.5 Audio PLL/VCXO Circuit/PLL1708 Clock Generator 2-10
2.3 PCI/HPI/Ethernet Interfaces 2-11
2.3.1 PCI Interface 2-11
2.3.2 PCI EEPROM Interface 2-11
2.3.3 Ethernet Interface 2-12
2.3.4 HPI Interface 2-12
2.4 I2C Interface 2-13
2.5 SPDIF Interface 2-13
2.6 Daughter Card Interface 2-14
2.7 Programming the FPGA 2-15
2.8 DM642 Core CPU Clock 2-15
2.9 HDTV Implementation 2-16

Spectrum Digital, Inc
2-2 TMS320DM642 EVM Technical Reference
2.1 EMIF Interfaces
The DM642 incorporates a 64 bit wide external memory interface. Four chip enables
divide up the address space and allow for synchronous and asynchronous accesses at
8,16,32, and 64 bits wide. The DM642 EVM uses chip enables CE0, CE1, and CE3.
CE0 is routed to 64 bit wide SDRAM bus. CE1 is used for 8 bit Flash, UART, and FPGA
functions. CE 3 is set for synchronous functions. Both CE2 and CE3 are routed to the
daughter card interface connectors.
2.1.1 SDRAM Memory Interface
The DM642 EVM interfaces to 64 bit wide SDRAM bus in the CE0 space. This 32
megabyte SDRAM space is used for program, data, and video storage. The bus uses
an external PLL device to operate the SDRAM at 133 megahertz for optimal
performance. Refresh for SDRAM is handled automatically by the DM642.
The PLL used for the EMIF is a ICS512. The input clock to this PLL is 25 Megahertz.
The table below shows the available frequencies using the 25 Megahertz input clock.
*Default setting
Table 1: EMIF Interfaces
Chip Select Function
CE0 SDRAM bus
CE1 8 bit Flash, UART, FPGA functions
CE2 Daughter Card Interface
CE3 FPGA Sync Registers
Daughter Card Interface
Table 2: PLL Frequencies
S1 Input S2 Input Multiplier Output Frequency
0 0 4x 100 Mhz
0 Open 5.33x 133.25 Mhz *
0 1 5x 125 Mhz
Open 0 2.5x 62.5 Mhz
Open Open 2x 50 Mhz
Open 1 3.33x 83.25 Mhz
1 0 6x 150 Mhz
1 Open 3x 75 Mhz
1 1 8x 200 Mhz