Spectrum Digital TMS320DM365 Use and care manual

TMS320DM365
Evaluation Module
2009 DSP Development Systems
Reference
Technical
Preliminary
April14,2009

TMS320DM365 Evaluation
Module Technical Reference
510845-0001 Rev. A
April 2009
SPECTRUM DIGITAL, INC.
12502 Exchange Drive, Suite 440 Stafford, TX. 77477
Tel: [phone] Fax: [phone]
[e-mail] www.spectrumdigital.com

IMPORTANT NOTICE
Spectrum Digital, Inc. reserves the right to make changes to its products or to discontinue any
product or service without notice. Customers are advised to obtain the latest version of relevant
information to verify that the data being relied on is current before placing orders.
Spectrum Digital, Inc. warrants performance of its products and related software to current
specifications in accordance with Spectrum Digital’s standard warranty. Testing and other quality
control techniques are utilized to the extent deemed necessary to support this warranty.
Please be aware that the products described herein are not intended for use in life-support
appliances, devices, or systems. Spectrum Digital does not warrant nor is Spectrum Digital liable for
the product described herein to be used in other than a development environment.
Spectrum Digital, Inc. assumes no liability for applications assistance, customer product design,
software performance, or infringement of patents or services described herein. Nor does Spectrum
Digital warrant or represent any license, either express or implied, is granted under any patent right,
copyright, or other intellectual property right of Spectrum Digital, Inc. covering or relating to any
combination, machine, or process in which such Digital Signal Processing development products or
services might be or are used.
WARNING
This equipment is intended for use in a laboratory test environment only. It generates, uses, and can
radiate radio frequency energy and has not been tested for compliance with the limits of computing
devices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonable
protection against radio frequency interference. Operation of this equipment in other environments
may cause interference with radio communications, in which case the user at his own expense will be
required to take whatever measures necessary to correct this interference.
Copyright © 2009 Spectrum Digital, Inc.

Contents
1 Introduction to the DM365 Evaluation Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Provides you with a description of the DM365 Evaluation Module, key features, and
block diagram.
1.1 Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.2 Functional Overview of the DM365 EVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.3 Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.4 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.5 Boot / Configuration Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.6 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
2 Board Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Describes the operation of the major board components on the DM365 Evaluation Module.
2.1 EMIF Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.1.1 Flash, NAND Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.1.1.1 One NAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.1.1.2 CPLD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.1.1.2.1 Register 0, CPLD Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.1.1.2.2 Register 1, Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.1.1.2.3 Register 2, LED Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.1.1.2.4 Register 3, Board Mux Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.1.1.2.5 Register 4, Board Switch Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.1.1.2.6 Register 5, Power Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.1.1.2.7 Register 6, GPIO Video Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.1.1.2.8 Register 7, Media Card Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.1.1.2.9 Register 8, DILC Output Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.1.1.2.10 Register 9, DILC Input Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.1.1.2.11 Register 10, Imager Internal I/O Direction Register 0 . . . . . . . . . . . . . . . . . . . 2-10
2.1.1.2.12 Register 11, Internal I/O Mux Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.1.1.2.13 Register 12, Internal I/O Mux Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.1.1.2.14 Register 13, Imager Internal I/O Direction Register 1 . . . . . . . . . . . . . . . . . . . 2-12
2.1.1.2.15 Register 14, Imager Internal I/O Mux Register 2 . . . . . . . . . . . . . . . . . . . . . . 2-12
2.1.1.2.16 Register 15, Imager Internal I/O Mux Register 3 . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.1.1.2.17 Register 16, Imager Internal I/O Direction Register 2 . . . . . . . . . . . . . . . . . . . . 2-13
2.1.1.2.18 Register 17, Imager Internal I/O Mux Register 4 . . . . . . . . . . . . . . . . . . . . . . 2-14
2.1.1.2.19 Register 18, Imager Internal I/O Mux Register 5 . . . . . . . . . . . . . . . . . . . . . . 2-14
2.1.1.2.20 Register 19, Board RESET Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2.1.1.2.21 Register 720, CCD Internal I/O Direction Register 1 . . . . . . . . . . . . . . . . . . . . 2-15
2.1.1.2.22 Register 721, CCS Internal I/O Read/Write Register 1 . . . . . . . . . . . . . . . . . . 2-16
2.1.1.2.23 Register 722, CCD Internal I/O Direction Register 2 . . . . . . . . . . . . . . . . . . . . 2-16
2.1.1.2.24 Register 723, CCD Internal I/O Read/Write Register 2 . . . . . . . . . . . . . . . . . . 2-17
2.1.1.2.25 Register 724, CCD Internal I/O Direction Register 3 . . . . . . . . . . . . . . . . . . . . 2-17

2.1.1.2.26 Register 725, CCD Internal I/O Read/Write Register 3 . . . . . . . . . . . . . . . . . . 2-18
2.1.1.3 Key Pad Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2.1.2 DDR2 Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2.1.3 Media Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2.1.4 UART Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
2.1.5 USB Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
2.2 Input Video Port/Imager Input Port Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
2.2.1 On Chip Video Output DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
2.2.2 LCD Video Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
2.3 AIC3101 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
2.4 On Chip Voice Codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
2.5 On Chip ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
2.6 On Chip RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
2.7 Ethernet Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
2.8 I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
2.8.1 MSP430 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
2.9 Daughter Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
2.10 DM365 CPU Video Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
2.11 Battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26
3 Physical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Describes the physical layout of the DM365 Evaluation Module and its connectors.
3.1 Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.2 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3.2.1 J1, MiniAB USB Connector and Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
3.2.2 J2, 14 Pin External JTAG Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.2.3 J3, MSP430 JTAG Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.2.4 J4, Spare Jumper Holder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.2.5 J5, 20 Pin ARM JTAG Emulation Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.2.6 J6, USB Capacitance Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.2.7 J7, +5 Volts Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.2.8 J12, SD/MMC/MS Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.2.9 J10, Imager Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
3.2.10 J14, EMIF/UPI DC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
3.2.11 J8, Y Component Video In, RCA Jack (Green) . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
3.2.12 J9, Pb Component Video In, RCA Jack (Blue) . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
3.2.13 J11, Pr Component Video In, RCA Jack (Red) . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
3.2.14 J15, S-Video In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
3.2.15 J13, CVBS/Y Input, RCA Jack (Yellow) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
3.2.16 J16, Composite TV Out, RCA Jack (Yellow) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
3.2.17 J17, Y Component Video Out, RCA Jack (Green) . . . . . . . . . . . . . . . . . . . . . . . . 3-16
3.2.18 J20, Pb Component Video Out, RCA Jack (Blue) . . . . . . . . . . . . . . . . . . . . . . . . 3-16
3.2.19 J21, Pr Component Video Out, RCA Jack (Red) . . . . . . . . . . . . . . . . . . . . . . . . . 3-17
3.2.20 J18, J19, Video Output DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18
3.2.21 J22, CPLD Programming Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
3.2.22 J23, I/O Interface Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
3.2.23 J24, DILC Host Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
3.2.24 J25, MMC/SD Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
3.2.25 P1, RS-232 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22
3.2.26 P2, Ethernet Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23

3.2.27 P3, Microphone In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24
3.2.28 P4, Line In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24
3.2.29 P5, Line Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25
3.2.30 P6, Headphone Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25
3.2.31 U1, Infrared Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26
3.2.32 SPK1, Speaker Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26
3.2.33 BHT1, Battery Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27
3.2.34 M1, Microphone Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27
3.3 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28
3.4 Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29
3.4.1 SW1, EMU0/1 Select Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30
3.4.2 SW2, PWCTRO0 Pushbutton . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30
3.4.3 SW3, Non-Supported Pushbutton . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30
3.4.4 SW4, Boot Mode / Configuration Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31
3.4.5 SW5, Board Configuration Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32
3.4.6 SW6 - SW21, Function Pushbuttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32
3.4.7 SW22, MSP430 IO0 Pushbutton . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33
3.4.8 SW23, PRTSC Mode Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33
3.5 Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-34
3.5.1 JP1, Jumper Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-34
3.6 Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35
A Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
Contains the schematics for the DM365 Evaluation Module
B Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
Contains the mechanical information about the DM365 Evaluation Module

About This Manual
This document describes the board level operations of the DM365 Evaluation Module
(EVM). The EVM is based on the Texas Instruments TMS320DM365 Processor.
The DM365 Evaluation Module is a table top card that allows engineers and software
developers to evaluate certain characteristics of the DM365 processor to determine if
the processor meets the designers application requirements. Evaluators can create
software to execute on board or expand the system in a variety of ways.
Notational Conventions
This document uses the following conventions.
The DM365 Evaluation Module will sometimes be referred to as the DM365 EVM or
EVM.
Program listings, program examples, and interactive displays are shown in a special
italic typeface. Here is a sample program listing.
equations
!rd = !strobe&rw;
Information About Cautions
This book may contain cautions.
This is an example of a caution statement.
A caution statement describes a situation that could potentially damage your software,
or hardware, or other equipment. The information in a caution is provided for your
protection. Please read each caution carefully.

Related Documents, Application Notes and User Guides
Information regarding the TMS320DM365 can be found at the following Texas
Instruments website:
http://www.ti.com
Table 1: Manual History
Revision History
A Beta Release
Table 2: Board History
PWB
Revision History
C Beta Release

1-1
Chapter 1
Introduction to the
DM365 EVM
Chapter One provides a description of the DM365 EVM along with the key
features and a block diagram of the circuit board.
Topic Page
1.1 Key Features 1-2
1.2 Functional Overview of the DM365 EVM 1-4
1.3 Basic Operation 1-4
1.4 Memory Map 1-5
1.5 Boot / Configuration Switch Settings 1-6
1.6 Power Supply 1-7

Spectrum Digital, Inc
1-2 DM365 EVM Technical Reference
1.1 Key Features
The DM365 EVM is a standalone development platform that enables users to
evaluate and develop applications for the TMS320DM365 processor. Schematics,
logic equations and application notes are available to ease hardware development and
reduce time to market.
The EVM comes with a full complement of on board devices that suit a wide variety of
application environments. Key features include:
• A Texas Instruments DM365 processor with an ARM9 processor operating up to
300 MHz.
• 1 video input port, supports composite or S video (NTSC or PAL formats)
• 1 set of 3 component video inputs supports capture up to 720P resolution
• 1 composite video DAC output (NTSC or PAL formats)
• 1 set of 3 component video DACs supports resolution up to 720P resolution
• 128 Mbytes of DDR2 DRAM
• UART Interface
• Dual SD/MMC/MS, MMC/SD Media Card Interfaces
Figure 1-1, Block Diagram DM365 EVM
LEDs
Camera IF
16
SW
1
LINE OUT
LINE IN
MIC IN
Battery
ENET
RJ45 IR
MSP430
JTAG
I2C
ROM
HP OUT
12
TPS65530
Power
PWR
AIC
3101
SD/MMC
EMIF
JTAG
Digital
Video Out
Video In
SD Video
Decoder
TVP5146
Comp
I
2
C Bus
DDR2
HD Video
Decoder
TVP7002
Speaker
Y
Pb/Cb
Pr/Cr
Comp
Y
Pb/Cb
Pr/Cr
S-Video
HD Video In Connector
MIC
J23
J19 J18
THS7353
MUX
KSZ8001
PHY
MII
McBSP
UART0
USB
SPI0
DAC Out
USB
Reset
PRTSCC On
16
SW
1
12
SD/MMC
EMIF
JTAG
Digital
Video Out
Video In
MII
McBSP
UART0
USB
SPI0
DAC Out
1 2 3 4 5 6
1 2 3 4 5 6
SW4
SW5
Keypad
LCD Interface
DM365
JTAG (20)
MSP430
SPI
ROM
SD/MMC
SD0 on Top
SD1 on Bottom
RS-232 JTAG (14)
THS7303
One
NAND
J14 - EMIF
NAND
CPLD

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1-3
• 2 Gigabytes NAND Flash
• 128 Megabytes of One NAND
• AIC3101 stereo codec
• USB2 Interface
• 10/100 MBS RMII Ethernet Interface
• SPI EEPROM
• IR Remote Interface via MSP430
• Configurable boot load options
• 8 user LEDs/16 user push button switches
• Single voltage power supply (+5V)
• Expansion connectors for daughter card use
• 14 Pin TI JTAG/20 Pin ARM JTAG Interfaces
Figure 1-2, DM365 EVM

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1-4 DM365 EVM Technical Reference
1.2 Functional Overview of the DM365 EVM
The DM365 on the EVM interfaces to on-board peripherals through the 8/16-bit wide
Async EMIF peripheral interface pins. The DDR2 memory is connected to its own
dedicated 16 bit wide bus. The Async EMIF bus is also connected to the NAND and
One NAND flash.
On board video decoders and on chip encoders interface video streams to the DM365
processor. One composite channel and one set of 3 component channel
encoder/decoder are standard on the EVM. On screen display functions are
implemented in software on the DM365 processor.
An on-board AIC3101 codec allows the DSP to transmit and receive analog audio
signals. The I2C bus is used for the codec control interface, while the McBSP controls
the audio stream. Signal interfacing is done through 3.5mm audio jacks that correspond
to microphone input, headphone output, line input, and line output.
The EVM includes 8 user LEDs, 16 user push button switches, and an IR interface
which provide the user with application interaction.
An included +5V external power supply is used to power the board. On-board switching
voltage regulators provide the +1.2 to 1.35V CPU core voltage, +3.3V for peripherals
and +1.8V for DDR2 memory.
The DM365 EVM has a 10/100 ethernet interface which provides a standard high
speed link to other devices.
The on board media card interface allows the user to conveniently load/store data from
a variety of standard memory card formats. An on-chip Real Time Clock is integrated
into the DM365 for time based applications.
1.3 Basic Operation
The EVM is designed to work with TI’s Code Composer Studio IDETM, or standard GDB
tool environments. Code Composer communicates with the board through an external
JTAG emulator.

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1-5
1.4 Memory Map
The DM365 processor has a byte addressable address space. There are some
limitations to byte addressing which are determined by peripheral interconnection to the
DM365 device. Program code and data can be placed anywhere in the unified address
space. Addresses are multiple sizes depending on hardware implementation. Refer to
the appropriate device data sheets for more details.
The memory map shows the address space of a generic DM365 processor on the left
with specific details of how each region is used on the right. By default, the internal
memory sits at the beginning of the address space. Portions of memory can be
remapped in software as L2 cache rather than fixed RAM.
The part incorporates a dual EMIF interface. One dedicated EMIF directly interfaces to
the DDR2 memory. The other EMIF has 2 separate addressable regions called chip
enable spaces (CE0 & CE1). The NAND Flash, one NAND, and CPLD are mapped into
these chip enable spaces.
DM365 EVM
Address
0x00000000
0x00008000
0x00010000
0x04000000
0x20000000
0x80000000
CE1
DDR EMIF
Figure 1-3, Memory Map, DM365 EVM
ARM Instruction RAM
ARM Instruction ROM
CE0 - ASYNC EMIF (Data)
0x02000000
Memory Map Address Space
0x8FFFFFFF
DDR EMIF Control Regs
ARM RAM (Data)
CFG Bus Peripherals
0x01C00000
0x0000BFFF
0x00017FFF
0x01FFFFFF
0x03FFFFFF
0x05FFFFFF
0x2007FFFF
0x00007FFF
0x87FFFFFF
0x88000000 DDR Expansion
(reserved)

Spectrum Digital, Inc
1-6 DM365 EVM Technical Reference
Shown below is a break out of the memory spaces.
1.5 Boot / Configuration Switch Settings
The EVM has a configuration switch that allow users to control the Boot and EMIF
configuration state of the processor when it is released from reset. The switch SW4
determines the source for processor booting. By default the switches are configured to
NAND Flash boot. The EMIF configuration switch must be set accordingly. This switch
configures the DM365 pin muxing at RESET. The default for the pin muxing is shown
below. For additional pin muxing requirements please refer to the D365 data sheet.
*default setting
Table 1: SW4, ARM Boot Mode Select
Pos 3 Pos 2 Pos 1 HW Code Boot Mode
ON ON ON 0 0 0 NAND Boot *
ON ON OFF 0 0 1 ASYNC EMIF
ON OFF ON 0 1 0 MMC/SD Boot
ON OFF OFF 0 1 1 UART Boot
OFF ON ON 1 0 0 USB Boot
OFF ON OFF 1 0 1 SPI Boot
OFF OFF ON 1 1 0 EMAC Boot
OFF OFF OFF 1 1 1 HPI Boot
Table 2: SW4, ARM EMIF Configuration Mode Select
Pos 6 Pos 5 Pos 4 HW Code Configuration Mode
ON ON ON 0 0 0 8-bit AEMIF Configuration *
ON ON OFF 0 0 1 16-bit AEMIF Configuration
Address
0x02004000
Figure 1-4, DM365 EVM Chip Enable Memory Space
0x40000000
Memory Space
0x02000000 NAND Chip Select 0 / One NAND
NAND Chip Select 1
CPLD Control Registers

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1-7
1.6 Power Supply
The EVM operates from a single +5V external power supply connected to the main
power input (J7), a 2.5 MM. barrel-type plug. Internally, the +5V input is converted
into +1.2 to 1.35V, +1.8V and +3.3V using Texas Instruments TPS65530 power
management IC and various linear regulators. The +1.2 to 1.35V supply is used for the
DSP core while the +3.3V supply is used for the DSP's I/O buffers and other chips on
the board. The +1.8 volt supply is used for DM365 DDR2 memory, and other on chip
peripherals.

Spectrum Digital, Inc
1-8 DM365 EVM Technical Reference

2-1
Chapter 2
Board Components
This chapter describes the operation of the major board components on
the DM365 EVM.
Topic Page
2.1 Asychronous EMIF Interface 2-2
2.1.1 NAND Flash 2-2
2.1.1.1 One NAND 2-2
2.1.1.2 CPLD Interface 2-4
2.1.1.2.1 Register 0, CPLD Version 2-6
2.1.1.2.2 Register 1, Test Register 2-6
2.1.1.2.3 Register 2, LED Register 2-6
2.1.1.2.4 Register 3, Board Mux Control Register 2-6
2.1.1.2.5 Register 4, Board Switch Register 2-7
2.1.1.2.6 Register 5, Power Control Register 2-7
2.1.1.2.7 Register 6, GPIO Video Register 2-8
2.1.1.2.8 Register 7, Media Card Status 2-9
2.1.1.2.9 Register 8, DILC Output Pin Mapping 2-9
2.1.1.2.10 Register 9, DILC Input Pin Mapping 2-10
2.1.1.2.11 Register 10, Imager Internal I/O Direction Register 0 2-10
2.1.1.2.12 Register 11, Internal I/O Mux Register 0 2-11
2.1.1.2.13 Register 12, Internal I/O Mux Register 1 2-11
2.1.1.2.14 Register 13, Imager Internal I/O Direction Register 1 2-12
2.1.1.2.15 Register 14, Imager Internal I/O Mux Register 2 2-12
2.1.1.2.16 Register 15, Imager Internal I/O Mux Register 3 2-13
2.1.1.2.17 Register 16, Imager Internal I/O Direction Register 2 2-13
2.1.1.2.18 Register 17, Imager Internal I/O Mux Register 4 2-14
2.1.1.2.19 Register 18, Imager Internal I/O Mux Register 5 2-14
2.1.1.2.20 Register 19, Board RESET Register 2-15
2.1.1.2.21 Register 720, CCD Internal I/O Direction Register 1 2-15
2.1.1.2.22 Register 721, CCS Internal I/O Read/Write Register 1 2-16
2.1.1.2.23 Register 722, CCD Internal I/O Direction Register 2 2-16
2.1.1.2.24 Register 723, CCD Internal I/O Read/Write Register 2 2-17
2.1.1.2.25 Register 724, CCD Internal I/O Direction Register 3 2-17
2.1.1.2.26 Register 725, CCD Internal I/O Read/Write Register 3 2-18

Spectrum Digital, Inc
2-2 DM365 EVM Technical Reference
Topic Page
2.1.1.3 Key Pad Interface 2-19
2.1.2 DDR2 Memory Interface 2-19
2.1.3 Media Card Interface 2-19
2.1.4 UART Interface 2-20
2.1.5 USB Interface 2-20
2.2 Input Video Port/Imager Input Port Interfaces 2-20
2.2.1 On Chip Video Output DAC 2-21
2.2.2 LCD Video Connectors 2-21
2.3 AIC3101 Interface 2-22
2.4 On Chip Voice Codec 2-23
2.5 On Chip ADC 2-23
2.6 On Chip RTC 2-23
2.7 Ethernet Interface 2-24
2.8 I2C Interface 2-24
2.8.1 MSP430 2-25
2.9 Daughter Card Interface 2-25
2.10 DM365 CPU/Video Clocks 2-25
2.11 Battery 2-26