ST ST10 Series Owner's manual

1/197 Rev 8 September 2013
®
ST10 FAMILY
PROGRAMMING
MANUAL

PROGRAMMING MANUAL
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Table of Contents
1 Standard Instruction Set - - - - - - - - - - - - - - - - - - - 5
1.1 Addressing modes - - - - - - - - - - - - - - - - - - - - - - - 5
1.1.1 Short adressing modes - - - - - - - - - - - - - - - - - - - - - - - - -5
1.1.2 Long addressing mode - - - - - - - - - - - - - - - - - - - - - - - - - 6
1.1.3 DPP override mechanism - - - - - - - - - - - - - - - - - - - - - - - - 8
1.1.4 Indirect addressing modes - - - - - - - - - - - - - - - - - - - - - - - 9
1.1.5 Constants - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10
1.1.6 Branch target addressing modes - - - - - - - - - - - - - - - - - - - 11
1.2 Instruction execution times - - - - - - - - - - - - - - - - - - 12
1.2.1 Definition of measurement units - - - - - - - - - - - - - - - - - - - - 12
1.2.2 Minimum state times - - - - - - - - - - - - - - - - - - - - - - - - - 14
1.2.3 Additional state times - - - - - - - - - - - - - - - - - - - - - - - - - 15
1.3 Instruction set summary - - - - - - - - - - - - - - - - - - - 17
1.4 Instruction set ordered by functional group - - - - - - - - - - 21
1.5 Instruction set ordered by opcodes - - - - - - - - - - - - - - 37
1.6 Instruction conventions - - - - - - - - - - - - - - - - - - - - 45
1.6.1 Instruction name - - - - - - - - - - - - - - - - - - - - - - - - - - - 46
1.6.2 Syntax - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 46
1.6.3 Operation - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 46
1.6.4 Data types - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 48
1.6.5 Description - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 48
1.6.6 Condition code - - - - - - - - - - - - - - - - - - - - - - - - - - - - 48
1.6.7 Flags - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 50
1.6.8 Addressing modes - - - - - - - - - - - - - - - - - - - - - - - - - - 51
1.7 ATOMIC and EXTended instructions - - - - - - - - - - - - - 53
1.8 Instruction descriptions - - - - - - - - - - - - - - - - - - - - 54
2 MAC Instruction set - - - - - - - - - - - - - - - - - - - - - 139
2.1 Addressing modes - - - - - - - - - - - - - - - - - - - - - - 139
2.2 MAC instruction execution time - - - - - - - - - - - - - - - - 140
2.3 MAC instruction set summary - - - - - - - - - - - - - - - - - 141
2.4 MAC instruction conventions - - - - - - - - - - - - - - - - - 144
2.4.1 Operands - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 144
2.4.2 Operations - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 144
2.4.3 Abbreviations - - - - - - - - - - - - - - - - - - - - - - - - - - - - 145

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2.4.4 Data addressing modes - - - - - - - - - - - - - - - - - - - - - - 145
2.4.5 Instruction format - - - - - - - - - - - - - - - - - - - - - - - - - - 145
2.4.6 Flag states - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 146
2.4.7 Repeated instruction syntax - - - - - - - - - - - - - - - - - - - - 146
2.4.8 Shift value - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 147
2.5 MAC instruction descriptions - - - - - - - - - - - - - - - - - 147
3 Revision History - - - - - - - - - - - - - - - - - - - - - - 195

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Introduction
This programming manual details the instruction set for the ST10 family of products. The
manual is arranged in two sections. Section 1 details the standard instruction set and
includes all of the basic instructions. Section 2 details the extension to the instruction set
provided by the MAC. The MAC instructions are only available to devices containing the
MAC, refer to the datasheet for device-specific information.
In the standard instruction set, addressing modes, instruction execution times, minimum
state times and the causes of additional state times are defined. Cross reference tables of
instruction mnemonics, hexadecimal opcode, address modes and number of bytes, are
provided for the optimization of instruction sequences. Instruction set tables ordered by
functional group, can be used to identify the best instruction for a given application.
Instruction set tables ordered by hexadecimal opcode can be used to identify specific
instructions when reading executable code i.e. during the de-bugging phase. Finally, each
instruction is described individually on a page of standard format, using the conventions
defined in this manual. For ease of use, the instructions are listed alphabetically.
The MAC instruction set is divided into its 5 functional groups: Multiply and
Multiply-Accumulate, 32-Bit Arithmetic, Shift, Compare and Transfer Instructions. Two new
addressing modes supply the MAC with up to 2 new operands per instruction. Cross
reference tables of MAC instruction mnemonics by address mode, and MAC instruction
mnemonic by functional code can be used for quick reference. As for the standard instruction
set, each instruction has been described individually in a standard format according to
defined conventions. For convenience, the instructions are described in alphabetical order.

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1 Standard Instruction Set
1.1 Addressing modes
1.1.1 Short adressing modes
The ST10 family of devices use several powerful addressing modes for access to word, byte
and bit data. This section describes short, long and indirect address modes, constants and
branch target addressing modes.
Short addressing modes use an implicit base offset address to specify the 24-bit physical
address.
Short addressing modes give access to the GPR, SFR or bit-addressable memory space
Note: for byte GPRs, for word GPRs.
Mnemo Physical Address Short Address Range Scope of Access
Rw (CP) + 2*Rw Rw = 0...15 GPRs (Word) 16 values
Rb (CP) + 1*Rb Rb = 0...15 GPRs (Byte) 16 values
reg 00’FE00h + 2*reg reg = 00h...EFh SFRs (Word, Low byte)
00’F000h + 2*reg reg = 00h...EFh ESFRs (Word, Low byte)
(CP) + 2*(reg^0Fh) reg = F0h...FFh GPRs (Word) 16 values
(CP) + 1*(reg^0Fh) reg = F0h...FFh GPRs (Bytes) 16 values
bitoff 00’FD00h + 2*bitoff bitoff = 00h...7Fh RAM Bit word offset 128 values
00’FF00h + 2*(bitoff^FFh) bitoff = 80h...EFh SFR Bit word offset 128 values
(CP) + 2*(bitoff^0Fh) bitoff = F0h...FFh GPR Bit word offset 16 values
bitaddr Word offset as with bitoff. bitoff = 00h...FFh Any single bit
Immediate bit position. bitpos = 0...15
Table 1 Short addressing mode summary
PhysicalAddress BaseAddress ShortAddress+=
1=
2=

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1.1.2 Long addressing mode
Long addressing mode uses one of the four DPP registers to specify a physical 18-bit or
24-bit address. Any word or byte data within the entire address space can be accessed in
this mode. All devices support an override mechanism for the DPP addressing scheme (see
section 1.1.3).
Note Word accesses on odd byte addresses are not executed, but rather trigger a
hardware trap. After reset, the DPP registers are initialized so that all long
addresses are directly mapped onto the identical physical addresses, within
segment 0.
Rw, Rb: Specifies direct access to any GPR in the currently active context (register bank). Both
'Rw' and 'Rb' require four bits in the instruction format. The base address of the current
register bank is determined by the content of register CP. 'Rw' specifies a 4-bit word GPR
address relative to the base address (CP), while 'Rb' specifies a 4 bit byte GPR address
relative to the base address (CP).
reg: Specifies direct access to any (E)SFR or GPR in the currently active context (register
bank). 'reg' requires eight bits in the instruction format. Short 'reg' addresses from 00h to
EFh always specify (E)SFRs. In this case, the factor '' equals 2 and the base address is
00’F000h for the standard SFR area, or 00’FE00h for the extended ESFR area. ‘reg’
accesses to the ESFR area require a preceding EXT*R instruction to switch the base
address. Depending on the opcode of an instruction, either the total word (for word opera-
tions), or the low byte (for byte operations) of an SFR can be addressed via 'reg'. Note that
the high byte of an SFR cannot be accessed by the 'reg' addressing mode. Short 'reg'
addresses from F0h to FFh always specify GPRs. In this case, only the lower four bits of
'reg' are significant for physical address generation, therefore it can be regarded as identi-
cal to the address generation described for the 'Rb' and 'Rw' addressing modes.
bitoff: Specifies direct access to any word in the bit-addressable memory space. 'bitoff' requires
eight bits in the instruction format. Depending on the specified 'bitoff' range, different base
addresses are used to generate physical addresses: Short 'bitoff' addresses from 00h to
7Fh use 00’FD00h as a base address, therefore they specify the 128 highest internal RAM
word locations (00’FD00h to 00’FDFEh). Short 'bitoff' addresses from 80h to EFh use
00’FF00h as a base address to specify the highest internal SFR word locations (00’FF00h
to 00’FFDEh) or use 00’F100h as a base address to specify the highest internal ESFR
word locations (00’F100h to 00’F1DEh). ‘bitoff’ accesses to the ESFR area require a pre-
ceding EXT*R instruction to switch the base address. For short 'bitoff' addresses from F0h
to FFh, only the lowest four bits and the contents of the CP register are used to generate
the physical address of the selected word GPR.
bitaddr: Any bit address is specified by a word address within the bit-addressable memory space
(see 'bitoff'), and by a bit position ('bitpos') within that word. Thus, 'bitaddr' requires twelve
bits in the instruction format.

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Long addresses (16-bit) are treated in two parts. Bits 13...0 specify a 14-bit data page offset,
and bits 15...14 specify the Data Page Pointer (1 of 4). The DPP is used to generate the
physical 24-bit address (see figure below).
All ST10 devices support an address space of up to 16 MByte, so only the lower ten bits of
the selected DPP register content are concatenated with the 14-bit data page offset to build
the physical address.
The long addressing mode is referred to by the mnemonic “mem”.
Figure 1 Interpretation of a 16-bit long address
Mnemo Physical Address Long Address Range Scope of Access
mem (DPP0) || mem^3FFFh 0000h...3FFFh Any Word or Byte
(DPP1) || mem^3FFFh 4000h...7FFFh
(DPP2) || mem^3FFFh 8000h...BFFFh
(DPP3) || mem^3FFFh C000h...FFFFh
mem pag || mem^3FFFh 0000h...FFFFh (14-bit) Any Word or Byte
mem seg || mem 0000h...FFFFh (16-bit) Any Word or Byte
Table 2 Summary of long address modes
0
15 14 13
16-bit Long Address
DPP0
DPP1
DPP2
DPP3
14-bit page offset
24-bit Physical Address
selects Data Page Pointer
0
9
023 1314

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1.1.3 DPP override mechanism
The DPP override mechanism temporarily bypasses the DPP addressing scheme.
The EXTP(R) and EXTS(R) instructions override this addressing mechanism. Instruction
EXTP(R) replaces the content of the respective DPP register, while instruction EXTS(R)
concatenates the complete 16-bit long address with the specified segment base address.
The overriding page or segment may be specified directly as a constant (#pag, #seg) or by a
word GPR (Rw).
Figure 2 Overriding the DPP mechanism
0
15 14 13
16-bit Long Address
#pag 14-bit page offset
24-bit Physical Address
0
15
16-bit Long Address
#seg 16-bit segment offset
24-bit Physical Address
EXTP(R):
EXTS(R):

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1.1.4 Indirect addressing modes
Indirect addressing modes can be considered as a combination of short and long
addressing modes. In this mode, long 16-bit addresses are specified indirectly by the
contents of a word GPR, which is specified directly by a short 4-bit address ('Rw'=0 to 15).
Some indirect addressing modes add a constant value to the GPR contents before the long
16-bit address is calculated. Other indirect addressing modes allow decrementing or
incrementing of the indirect address pointers (GPR content) by 2 or 1 (referring to words or
bytes).
In each case, one of the four DPP registers is used to specify the physical 18-bit or 24-bit
addresses. Any word or byte data within the entire memory space can be addressed
indirectly. Note that EXTP(R) and EXTS(R) instructions override the DPP mechanism.
Instructions using the lowest four word GPRs (R3...R0) as indirect address pointers are
specified by short 2-bit addresses.
Word accesses on odd byte addresses are not executed, but rather trigger a hardware trap.
After reset, the DPP registers are initialized in a way that all indirect long addresses are
directly mapped onto the identical physical addresses.
Physical addresses are generated from indirect address pointers by the following algorithm:
1 Calculate the physical address of the word GPR which is used as indirect address
pointer, by using the specified short address ('Rw') and the current register bank base
address (CP).
2 Pre-decremented indirect address pointers (‘-Rw’) are decremented by a
data-type-dependent value ( for byte operations, for word operations),
before the long 16-bit address is generated:
3 Calculate the long 16-bit address by adding a constant value (if selected) to the content
of the indirect address pointer:
Long Address = (GPR Pointer) + Constant
4 Calculate the physical 18-bit or 24-bit address using the resulting long address and the
corresponding DPP register content (see long 'mem' addressing modes).
Physical Address = (DPPi) + Page offset
5 Post-Incremented indirect address pointers (‘Rw+’) are incremented by a
data-type-dependent value ( for byte operations, for word operations):
GPRAddress CP=2+ShortAddressoptionalstep!;–
1=
2=
GPRAddressGPRAddress=optionalstep!;–
1=
2=
GPRPointerGPRPointer=optionalstep!;+

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The following indirect addressing modes are provided:
1.1.5 Constants
The ST10 Family instruction set supports the use of wordwide or bytewide immediate
constants. For optimum utilization of the available code storage, these constants are
represented in the instruction formats by either 3, 4, 8 or 16 bits. Therefore, short constants
are always zero-extended, while long constants can be truncated to match the data format
required for the operation (see table below):
Note Immediate constants are always signified by a leading number sign “#”.
Mnemonic Notes
[Rw] Most instructions accept any GPR (R15...R0) as indirect address pointer.
Some instructions, however, only accept the lower four GPRs (R3...R0).
[Rw+] The specified indirect address pointer is automatically incremented by 2 or 1 (for
word or byte data operations) after the access.
[-Rw] The specified indirect address pointer is automatically decremented by 2 or 1 (for
word or byte data operations) before the access.
[Rw+#data16]A 16-bit constant and the contents of the indirect address pointer are added
before the long 16-bit address is calculated.
Table 3 Table of indirect address modes
Mnemonic Word operation Byte operation
#data30000h+ data300h+ data3
#data40000h+ data400h+ data4
#data80000h+ data8data8
#data16 data16 data16 ^ FFh
#mask 0000h+ mask mask
Table 4 Table of constants

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1.1.6 Branch target addressing modes
Jump and Call instructions use different addressing modes to specify the target address and
segment. Relative, absolute and indirect modes can be used to update the Instruction
Pointer register (IP), while the Code Segment Pointer register (CSP) can only be updated
with an absolute value. A special mode is provided to address the interrupt and trap jump
vector table situated in the lowest portion of code segment 0.
Mnemo Target Address Target Segment Valid Address Range
caddr (IP) = caddr -caddr = 0000h...FFFEh
rel (IP) = (IP) + 2*rel -rel = 00h...7Fh
(IP) = (IP) + 2*(~rel+1) -rel = 80h...FFh
[Rw] (IP) = ((CP) + 2*Rw) -Rw = 0...15
seg -(CSP) = seg seg = 0...255
#trap7(IP) = 0000h + 4*trap7(CSP) = 0000h trap7= 00h...7Fh
Table 5 Branch target address summary
caddr: Specifies an absolute 16-bit code address within the current segment. Branches MAY
NOT be taken to odd code addresses. Therefore, the least significant bit of 'caddr' must
always contain a '0', otherwise a hardware trap would occur.
rel: Represents an 8-bit signed word offset address relative to the current Instruction Pointer
contents which points to the instruction after the branch instruction. Depending on the off-
set address range, either forward ('rel'= 00h to 7Fh) or backward ('rel'= 80h to FFh)
branches are possible. The branch instruction itself is repeatedly executed, when 'rel' = '-1'
(FFh) for a word-sized branch instruction, or 'rel' = '-2' (FEh) for a double-word-sized
branch instruction.
[Rw]: The 16-bit branch target instruction address is determined indirectly by the content of a
word GPR. In contrast to indirect data addresses, indirectly specified code addresses are
NOT calculated by additional pointer registers (e.g. DPP registers). Branches MAY NOT
be taken to odd code addresses. Therefore, to prevent a hardware trap, the least signifi-
cant bit of the address pointer GPR must always contain a '0.
seg: Specifies an absolute code segment number. All devices support 256 different code seg-
ments, so only the eight lower bits of the 'seg' operand value are used for updating the
CSP register.
#trap7:Specifies a particular interrupt or trap number for branching to the corresponding interrupt
or trap service routine by a jump vector table. Trap numbers from 00h to 7Fh can be spec-
ified, which allows access to any double word code location within the address range
00’0000h...00’01FCh in code segment 0 (i.e. the interrupt jump vector table). For further
information on the relation between trap numbers and interrupt or trap sources, refer to the
device user manual section on “Interrupt and Trap Functions”.

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1.2 Instruction execution times
The instruction execution time depends on where the instruction is fetched from, and where
the operands are read from or written to. The fastest processing mode is to execute a
program fetched from the internal ROM. In this case most of the instructions can be
processed in just one machine cycle.
All external memory accesses are performed by the on-chip External Bus Controller (EBC)
which works in parallel with the CPU. Instructions from external memory cannot be
processed as fast as instructions from the internal ROM, because it is necessary to perform
data transfers sequentially via the external interface. In contrast to internal ROM program
execution, the time required to process an external program additionally depends on the
length of the instructions and operands, on the selected bus mode, and on the duration of an
external memory cycle.
Processing a program from the internal RAM space is not as fast as execution from the
internal ROM area, but it is flexible (i.e. for loading temporary programs into the internal RAM
via the chip's serial interface, or end-of-line programming via the bootstrap loader).
The following description evaluates the minimum and maximum program execution times.
which is sufficient for most requirements. For an exact determination of the instructions'
state times, the facilities provided by simulators or emulators should be used.
This section defines measurement units, summarizes the minimum (standard) state times of
the 16-bit microcontroller instructions, and describes the exceptions from the standard
timing.
1.2.1 Definition of measurement units
The following measurement units are used to define instruction processing times:
[fCPU]: CPU operating frequency (may vary from 1 MHz to 50 MHz).
[State]: One state time is specified by one CPU clock period. Therefore, one State is used as the
basic time unit, because it represents the shortest period of time which has to be considered
for instruction timing evaluations.
1 [State] = 1/fCPU[s] ; for fCPU = variable
= 50[ns] ; for fCPU = 20 MHz

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[ACT]: ALE (Address Latch Enable) Cycle Time specifies the time required to perform one external
memory access. One ALE Cycle Time consists of either two (for demultiplexed external bus
modes) or three (for multiplexed external bus modes) state times plus a number of state
times, which is determined by the number of waitstates programmed in the MCTC (Memory
Cycle Time Control) and MTTC (Memory Tristate Time Control) bit fields of the SYSCON/
BUSCONx registers.
For demultiplexed external bus modes:
1*ACT = (2 + (15 – MCTC) + (1 – MTTC)) * States
= 100 n... 900 ns ; for fCPU = 20 MHz
For multiplexed external bus modes:
1*ACT = (3 + (15 – MCTC) + (1 – MTTC)) * States
= 150 ns ... 950 ns ; for fCPU = 20 MHz
Ttot The total time (Ttot) taken to process a particular part of a program can be calculated by the
sum of the single instruction processing times (TIn) of the considered instructions plus an
offset value of 6 state times which takes into account the solitary filling of the pipeline:
Ttot =TI1 + TI2 + ... + TIn + 6 * States
TIn The time (TIn) taken to process a single instruction, consists of a minimum number (TImin)
plus an additional number (TIadd) of instruction state times and/or ALE Cycle Times:
TIn =TImin + TIadd
[fCPU]: CPU operating frequency (may vary from 1 MHz to 50 MHz).

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1.2.2 Minimum state times
The table below shows the minimum number of state times required to process an
instruction fetched from the internal ROM (TImin (ROM)). This table can also be used to
calculate the minimum number of state times for instructions fetched from the internal RAM
(TImin (RAM)), or ALE Cycle Times for instructions fetched from the external memory (TImin
(ext)).
Most of the 16-bit microcontroller instructions (except some branch, multiplication, division
and a special move instructions) require a minimum of two state times. For internal ROM
program execution, execution time has no dependence on instruction length, except for
some special branch situations.
To evaluate the execution time for the injected target instruction of a cache jump instruction,
it can be considered as if it was executed from the internal ROM, regardless of which
memory area the rest of the current program is really fetched from.
For some of the branch instructions the table below represents both the standard number of
state times (i.e. the corresponding branch is taken) and an additional TImin value in
parentheses, which refers to the case where, either the branch condition is not met, or a
cache jump is taken.
Instructions executed from the internal RAM require the same minimum time as they would
if they were fetched from the internal ROM, plus an instruction-length dependent number of
state times, as follows:
Instruction TImin (ROM) [States] TImin (ROM) (20MHz CPU clk)
CALLI, CALLA
CALLS, CALLR, PCALL
JB, JBC, JNB, JNBS
JMPS
JMPA, JMPI, JMPR
MUL, MULU
DIV, DIVL, DIVU, DIVLU
MOV[B] Rn, [Rm + #data16]
RET, RETI, RETP, RETS
TRAP
All other instructions
4
4
4
4
4
10
20
4
4
4
2
(2)
(2)
(2)
200
200
200
200
200
500
1000
200
200
200
100
(100)
(100)
(100)
Table 6 Minimum instruction state times [Unit = ns]

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•For 2-byte instructions: TImin(RAM) = TImin(ROM) + 4 * States
•For 4-byte instructions: TImin(RAM) = TImin(ROM) + 6 * States
Unlike internal ROM program execution, the minimum time TImin(ext) to process an external
instruction also depends on instruction length. TImin(ext) is either 1 ALE Cycle Time for most
of the 2-byte instructions, or 2 ALE Cycle Times for most of the 4-byte instructions. The
following formula represents the minimum execution time of instructions fetched from an
external memory via a 16-bit wide data bus:
•For 2-byte instructions: TImin(ext) = 1*ACT + (TImin(ROM) - 2) * States
•For 4-byte instructions: TImin(ext) = 2*ACTs + (TImin(ROM) - 2) * States
Note For instructions fetched from an external memory via an 8-bit wide data bus, the
minimum number of required ALE Cycle Times is twice the number for those of a
16-bit wide bus.
1.2.3 Additional state times
Some operand accesses can extend the execution time of an instruction TIn. Since the
additional time TIadd is generally caused by internal instruction pipelining, it may be possible
to minimize the effect by rearranging the instruction sequences. Simulators and emulators
offer a high level of programmer support for program optimization.
The following operands require additional state times:
Internal ROM operand reads:TIadd = 2 * States 
Both byte and word operand reads always require 2 additional state times.
Internal RAM operand reads via indirect addressing modes: TIadd = 0 or 1 * State
Reading a GPR or any other directly addressed operand within the internal RAM space does
NOT cause additional state times. However, reading an indirectly addressed internal RAM
operand will extend the processing time by 1 state time, if the preceding instruction
auto-increments or auto-decrements a GPR, as shown in the following example:
In this case, the additional time can be avoided by putting another suitable instruction before
the instruction In+1 indirectly reading the internal RAM.
In: MOV R1, [R0+] ; auto-increment R0
In+1 : MOV [R3], [R2] ; if R2 points into the internal RAM space:
; TIadd = 1 * State

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Internal SFR operand reads: TIadd = 0, 1 * State or 2 * States
SFR read accesses do NOT usually require additional processing time. In some rare cases,
however, either one or two additional state times will be caused by particular SFR
operations:
•Reading an SFR immediately after an instruction, which writes to the internal SFR
space, as shown in the following example:
•Reading the PSW register immediately after an instruction which implicitly updates the
flags as shown in the following example:
•Implicitly incrementing or decrementing the SP register immediately after an instruction
which explicitly writes to the SP register, as shown in the following example:
In each of these above cases, the extra state times can be avoided by putting other suitable
instructions before the instruction In+1 reading the SFR.
External operand reads: TIadd = 1 * ACT
Any external operand reading via a 16-bit wide data bus requires one additional ALE Cycle
Time. Reading word operands via an 8-bit wide data bus takes twice as much time (2 ALE
Cycle Times) as the reading of byte operands.
External operand writes: TIadd = 0 * State ... 1 * ACT
Writing an external operand via a 16-bit wide data bus takes one additional ALE Cycle Time.
For timing calculations of external program parts, this extra time must always be considered.
The value of TIadd which must be considered for timing evaluations of internal program
parts, may fluctuate between 0 state times and 1 ALE Cycle Time. This is because external
writes are normally performed in parallel to other CPU operations. Thus, TIadd could already
have been considered in the standard processing time of another instruction. Writing a word
operand via an 8-bit wide data bus requires twice as much time (2 ALE Cycle Times) as the
writing of a byte operand.
In: MOV T0, #1000h ; write to Timer 0
In+1 : ADD R3, T1 ; read from Timer 1: TIadd = 1 * State
In: ADD R0, #1000h ; implicit modification of PSW flags
In+1 : BAND C, Z ; read from PSW: TIadd = 2 * States
In: MOV SP, #0FB00h ; explicit update of the stack pointer
In+1 : SCXT R1, #1000h ; implicit decrement of the stack pointer:
; TIadd = 2 * States

PROGRAMMING MANUAL Standard Instruction Set
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Jumps into the internal ROM space: TIadd = 0 or 2 * States
The minimum time of 4 state times for standard jumps into the internal ROM space will be
extended by 2 additional state times, if the branch target instruction is a double word
instruction at a non-aligned double word location (xxx2h, xxx6h, xxxAh, xxxEh), as shown in
the following example:
A cache jump, which normally requires just 2 state times, will be extended by 2 additional
state times, if both the cached jump target instruction and the following instruction are
non-aligned double word instructions, as shown in the following example:
If necessary, these extra state times can be avoided by allocating double word jump target
instructions to aligned double word addresses (xxx0h, xxx4h, xxx8h, xxxCh).
Testing Branch Conditions: TIadd = 0 or 1 * States
NO extra time is usually required for a conditional branch instructions to decide whether a
branch condition is met or not. However, an additional state time is required if the preceding
instruction writes to the PSW register, as shown in the following example:
In this case, the extra state time can be intercepted by putting another suitable instruction
before the conditional branch instruction.
1.3 Instruction set summary
The following table lists the instruction mnemonic by hex-code with operand.
Table 7 Instruction mnemonic by hex-code with operand
label : .... ; any non-aligned double word instruction
; (e.g. at location 0FFEh)
.... : ....
In+1 : JMPA cc_UC, label ; if a standard branch is taken:
; TIadd = 2 *States (TIn = 6 *States)
label : .... ; any non-aligned double word instruction
; (e.g. at location 12FAh)
In+1 :.... ; any non-aligned double word instruction
; (e.g. at location 12FEh)
In+1 : JMPR cc_UC, label ; provided that a cache jump is taken:
; TIadd = 2 * States (TIn = 4 * States)
In: BSET USR0 ; implicit modification of PSW flags
In+1 : JMPR cc_Z, label ; test condition flag in PSW: TIadd= 1 * State

Standard Instruction Set PROGRAMMING MANUAL
18/197
0x 1x 2x 3x 4x 5x 6x 7x 8x 9x Ax Bx Cx Dx Ex Fx
x0
ADD
ADDC
SUB
SUBC
CMP
XOR
AND
OR
CMPI1 CMPI2
CMPD1 CMPD2
MOVBZ
MOVBS
MOV MOV
x0
x1
ADDB ADDCB SUBB SUBCB CMPB XORB ANDB ORB NEG
CPL
NEGB CPLB - ATOMIC /EXTR MOVB
MOVB
x1
x2
ADD
ADDC
SUB
SUBC
CMP
XOR
AND
OR
CMPI
CMPI2
CMPD1
CMPD2
MOVBZ
MOVBS
PCALL
MOV
x2
x3
ADDB ADDCB SUBB SUBCB CMPB XORB ANDB ORB
CoXXX CoXXX CoXXX
CoSTORE CoSTORE
CoMOV
-
MOVB
x3
x4
ADD
ADDC
SUB
SUBC
-
XOR
AND
OR
MOV MOV
MOVB MOVB
MOV MOV
MOVB MOVB
x4
x5
ADDB ADDCB SUBB SUBCB - XORB ANDB ORB
- -
DISWDT
EINIT
MOVBZ
MOVBS
- -
x5
x6
ADD
ADDC
SUB
SUBC
CMP
XOR
AND
OR
CMPI1 CMPI2
CMPD1 CMPD2
SCXT SCXT
MOV MOV
x6
x7
ADDB ADDCB SUBB SUBCB CMPB XORB ANDB ORB
IDLE
PWRDN
SRVWDT
SRST
-
EXTP(R)/ EXTS(R) MOVB MOVB
x7
x8
ADD
ADDC
SUB
SUBC
CMP
XOR
AND
OR
MOV MOV MOV MOV MOV MOV MOV
-
x8
x9
ADDB ADDCB SUBB SUBCB CMPB XORB ANDB ORB
MOVB MOVB MOVB MOVB MOVB MOVB MOVB
-
x9
xA
BFLDL
BFLDH
BCMP
BMOVN
BMOV
BOR
BAND
BXOR
JB
JNB
JBC
JNBS
CALLA CALLS
JMPA JMPS
xA
xB
MUL
MULU
PRIOR
-
DIV
DIVU
DIVL
DIVLU
-
TRAP
CALLI
CALLR
RET
RETS RETP
RETI
xB
xC
ROL ROL
ROR ROR
SHL SHL
SHR SHR
-
JMPI
ASHR ASHR
NOP
EXTP(R)/
EXTS(R)
PUSH
POP
xC
xD
JMPR xD
xE
BCLR xE
xF
BSET xF
0x 1x 2x 3x 4x 5x 6x 7x 8x 9x Ax Bx Cx Dx Ex Fx
Hi
Lo
Rwn, Rwm Rwn, Rwm Rwn, Rwm
REG, MEM REG, MEM REG, MEM REG, MEM
MEM, REG MEM, REG MEM, REG MEM, REG
REG, #data16 REG, #data16 REG, #data16 REG, #data16
Rwn,[Rwi]
Rwn,[Rwi+]
Rwn, #data3
Rwn,[Rwi]
Rwn,[Rwi+]
Rwn, #data3
Rwn,[Rwi]
Rwn,[Rwi+]
Rwn, #data3
Rwn,[Rwi]
Rwn,[Rwi+]
Rwn, #data3
BITOFF,
MASK, #data3
BITadd, BITadd BITadd, BITadd BITadd, BITadd BITadd, BITadd
BITadd, BITadd
BITadd, BITadd
BITadd, REL
BITadd, REL
Rwn, Rwm
Rwn, Rwm
Rwn Rwn
Rwn Rwn
cc, rel
Rwn, #d4
Rwn, #d4 Rwn, #d4
Rwn, Rwm
Rwn, Rwm
Rwn, Rwm
Rwn, #d4
BITaddrQ.q
BITaddrQ.q
Rwn, #d4 Rwn, #d4
Rwn, Rwm
Rwn Rwn
#data2
Rwn, #data4 Rwn, #data4
Rwn, MEM
Rwn, MEM
REG, MEM
REG,CADDR
REG, MEM
[Rwn],MEM
MEM,[Rwn]
[Rwn],MEM
[Rwm+#d16],Rwn
Rwn,[Rwm+#d16]
[Rwm+#d16],Rwn
Rwn,[Rwm+#d16]
MEM,REG
Rwn,#d16
Rwn,#d16
REG,#d16
REG,MEM
REG, Data#16
MEM, REG
#pag,#data2
[-Rwm], Rwn
Rwn, [Rwm+]
Rwn, [Rwm]
[Rwm], Rwn
[Rwn], [Rwm]
[Rwn+], [Rwm]
[Rwn], [Rwm+]
CC, CADDR
SEG, CADDR
CC, CADDR
SEG, CADDR
#trap
cc, [Rwn]
REL
cc, [Rwn]
Rwn, Rwm
Rwn, #d4
Rwm, #d2
REG REG
Rwn, Rwm
[Rwm+#d16],Rwn
Rwn, Rwm
Hi
Lo
Hi
Lo
Hi
Lo
Rwn,[Rwm]
Rwn,Rwm
Rwn,CoREG
[Rwn],CoREG
[IDXi],[Rwm]
[IDXi],[Rwm]

PROGRAMMING MANUAL Standard Instruction Set
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Table 8 lists the instructions by their mnemonic and identifies the addressing modes that
may be used with a specific instruction and the instruction length, depending on the selected
addressing mode (in bytes).
Mnemonic Addressing modes
Bytes
Mnemonic Addressing modes
Bytes
ADD[B] Rwn1, Rwm12CPL[B] Rwn12
ADDC[B] Rwn1, [Rwi] 2NEG[B]
AND[B] Rwn1, [Rwi+] 2 DIV Rwn2
OR[B] Rwn1, #data32DIVL
SUB[B] reg, #data16 4DIVLU
SUBC[B] reg, mem 4DIVU
XOR[B] mem, reg 4MUL Rwn, Rwm2
MULU
ASHR Rwn, Rwm2CMPD1/2 Rwn, #data42
ROL / ROR Rwn, #data42CMPI1/2 Rwn, #data16 4
SHL / SHR Rwn, mem 4
BAND bitaddrZ.z, bitaddrQ.q 4CMP[B] Rwn, Rwm1
BCMP Rwn, [Rwi] 12
BMOV Rwn, [Rwi+]12
BMOVN Rwn, #data312
BOR / BXOR reg, #data16 4
reg, mem 4
BCLR bitaddrQ.q, 2 CALLA cc, caddr 4
BSET JMPA
BFLDH bitoffQ,#mask8,#data84CALLI cc, [Rwn] 2
BFLDL JMPI
Table 8 Mnemonic vs address mode & number of bytes

Standard Instruction Set PROGRAMMING MANUAL
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MOV[B] Rwn1, Rwm12CALLS seg, caddr 4
Rwn1, #data42JMPS
Rwn1, [Rwm]2CALLR rel 2
Rwn1, [Rwm+] 2JMPR cc, rel 2
[Rwm], Rwn12JB bitaddrQ.q,rel 4
[-Rwm], Rwn12JBC
[Rwn], [Rwm] 2 JNB
[Rwn+], [Rwm] 2 JNBS
[Rwn], [Rwm+] 2PCALL reg, caddr 4
reg, #data16 4POP reg 2
Rwn, [Rwm+#data16]14PUSH
[Rwm+#data16], Rwn14RETP
[Rwn], mem 4SCXT reg, #data16 4
mem, [Rwn] 4 reg, mem 4
reg, mem 4PRIOR Rwn, Rwm2
mem, reg 4
MOVBS Rwn, Rbm2TRAP #trap7 2
MOVBZ reg, mem 4AT O M I C #data2 2
mem, reg 4EXTR
EXTS Rwm, #data2 2EXTP Rwm,#data22
EXTSR #seg, #data24EXTPR #pag, #data24
NOP - 2 SRST/IDLE - 4
RET PWRDN
RETI SRVWDT
RETS DISWDT
EINIT
1. Byte oriented instructions (suffix ‘B’) use Rb instead of Rw (not with [Rwi]!).
Mnemonic Addressing modes
Bytes
Mnemonic Addressing modes
Bytes
Table 8 Mnemonic vs address mode & number of bytes (Continued)