Infineon Technologies C166S V2 User manual

Never stop thinking.
Microcontrollers
User Manual, V 1.7, January 2001
C166S V2
16-Bit Microcontroller

Edition 2001-01
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 München, Germany
©Infineon Technologies AG 2001.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as warranted
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address
list).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.

Microcontrollers
User Manual, V 1.7, January 2001
Never stop thinking.
C166S V2
16-Bit Microcontroller

C166S V2
Revision History: 2001-01 V1.7
Previous Version: -
Page Subjects (major changes since last revision)
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
[email protected]

User Manual
C166S V2
Table of Contents Page
User Manual 5 V 1.7, 2001-01
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.1 Technical Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.2 System Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.2.1 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.2.2 On-Chip Memory Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.2.3 Data Management Unit (DMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.2.4 Program Memory Unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.2.5 Interrupt and PEC Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.2.6 OCDS and JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.2.7 External Bus Controller (EBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.2.8 System Control Unit (SCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.2.9 Clock Generation Unit (CGU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.2.10 On-Chip Bootstrap Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2 Central Processing Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1 Register Description Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2 CPU Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3 Instruction Fetch and Program Flow Control . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.1 Branch Target Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3.2 Branch Detection and Branch Prediction . . . . . . . . . . . . . . . . . . . . . . . . 22
2.3.3 Sequential and Mispredicted Instruction Flow . . . . . . . . . . . . . . . . . . . . 24
2.3.3.1 Correctly Predicted Instruction Flow . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.3.3.2 Incorrectly Predicted Instruction Flow . . . . . . . . . . . . . . . . . . . . . . . . 26
2.3.4 Atomic and Extend Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.3.5 Code Addressing via Code Segment and Instruction Pointer . . . . . . . . 28
2.3.6 IFU Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.3.6.1 The CPU Configuration Register CPUCON1 . . . . . . . . . . . . . . . . . . . 30
2.3.6.2 The CPU Configuration Register CPUCON2 . . . . . . . . . . . . . . . . . . . 31
2.4 Use of General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.4.1 Memory Mapped GPR Banks and the Global Register Bank . . . . . . . . 36
2.4.2 Local Register Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.4.3 Context Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.4.3.1 Changing the selected Physical Register Bank . . . . . . . . . . . . . . . . . 40
2.4.3.2 Context Switching of the Global Register Bank . . . . . . . . . . . . . . . . . 42
2.5 Data Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.5.1 Short Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
2.5.2 Long and Indirect Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 48
2.5.2.1 Addressing via Data Page Pointer DPP . . . . . . . . . . . . . . . . . . . . . . 49
2.5.2.2 DPP Override Mechanism in the C166S V2 CPU . . . . . . . . . . . . . . . 51
2.5.2.3 Long Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2.5.2.4 Indirect Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
2.5.3 DSP Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
2.5.4 The CoREG Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

User Manual
C166S V2
Table of Contents Page
User Manual 6 V 1.7, 2001-01
2.5.5 The System Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.6 Data Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
2.6.1 Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
2.6.2 Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
2.6.3 16-bit Adder/Subtracter, Barrel Shifter, and 16-bit Logic Unit . . . . . . . . 70
2.6.4 Bit Manipulation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
2.6.5 Multiply and Divide Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
2.6.6 The Processor Status Word PSW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
2.7 Parallel Data Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
2.7.1 Representation of Numbers and Rounding . . . . . . . . . . . . . . . . . . . . . . 79
2.7.2 The 16-bit by 16-bit signed/unsigned Multiplier and Scaler . . . . . . . . . . 80
2.7.3 Concatenation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
2.7.4 One-bit Scaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
2.7.5 The 40-bit Adder/Subtracter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
2.7.6 The Data Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
2.7.7 The Accumulator Shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
2.7.8 The 40-bit Signed Accumulator Register . . . . . . . . . . . . . . . . . . . . . . . . 82
2.7.9 The Repeat Counter MRW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
2.7.10 The MAC Unit Status Word MSW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
2.7.11 The MAC Unit Control Word MCW . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
2.8 Dedicated CSFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
3 C166S V2 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
3.1 Data Organization in Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
3.2 Internal Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
3.3 DPRAM, Internal SRAM, and SFR Areas . . . . . . . . . . . . . . . . . . . . . . . . . 94
3.3.1 Data Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
3.3.2 Special Function Register Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
3.3.3 IO Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
3.3.4 PEC Source and Destination Pointers . . . . . . . . . . . . . . . . . . . . . . . . . . 97
3.4 External Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
3.4.1 Boot and Debug/Monitor Program Memories . . . . . . . . . . . . . . . . . . . . 98
3.5 Crossing Memory Boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
3.6 System Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
3.6.1 Data Organization in Global General Purpose Registers . . . . . . . . . . 100
4 Instruction Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.1 Instruction Dependencies in Different Pipeline Stages . . . . . . . . . . . . . . 104
4.1.1 The General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
4.1.2 Indirect Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
4.1.3 Memory Bandwidth Conflicts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
4.1.4 CPU-SFRs and the Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
5 Interrupt and Exception Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

User Manual
C166S V2
User Manual 7 V 1.7, 2001-01
5.1 Interrupt System and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
5.1.1 General Interrupt System Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
5.1.2 Interrupt Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
5.1.3 Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
5.1.4 Interrupt Vector Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
5.1.5 Interrupt Jump Table Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
5.2 Status and Switch Context Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
5.2.1 Interrupt Control Functions in the PSW . . . . . . . . . . . . . . . . . . . . . . . . 127
5.2.2 Saving the Status during Interrupt Service . . . . . . . . . . . . . . . . . . . . . 129
5.2.3 Context Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
5.2.4 Fast Bank Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
5.3 Traps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
5.3.1 Software Traps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
5.3.2 Hardware Traps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
5.4 Peripheral Event Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
5.4.1 PEC Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
5.4.2 The PEC Source and Destination Pointer . . . . . . . . . . . . . . . . . . . . . . 145
5.4.3 PEC Handler Interrupt Actions Summary . . . . . . . . . . . . . . . . . . . . . . 147
5.4.4 PEC Channel Assignment and Arbitration . . . . . . . . . . . . . . . . . . . . . . 149
5.5 CPU Action Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
6 External Bus Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
6.2 Timing Principles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
6.2.1 A Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
6.2.2 B Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
6.2.3 C Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
6.2.4 D Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
6.2.5 E Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
6.2.6 F Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
6.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
6.3.1 Configuration Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
6.3.2 The EBC MODE Registers EBCMODx . . . . . . . . . . . . . . . . . . . . . . . . 158
6.3.3 The Timing Configuration registers TCONCSx . . . . . . . . . . . . . . . . . . 161
6.3.4 The Function Configuration Registers FCONCSx . . . . . . . . . . . . . . . . 163
6.3.5 The Address Window Selection Registers ADDRSELx . . . . . . . . . . . . 164
6.3.5.1 Definition of Address Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
6.3.5.2 Address Window Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
6.3.6 Ready Controlled Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
6.3.6.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
6.3.6.2 The Synchronous/Asynchronous READY . . . . . . . . . . . . . . . . . . . . 168
6.3.6.3 Combining the READY function with predefined wait states . . . . . . 168
6.3.7 EBC Idle State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

User Manual
C166S V2
User Manual 8 V 1.7, 2001-01
6.4 Multi Master Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
6.4.1 External Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
6.4.1.1 Initialization of Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
6.4.1.2 Arbitration Master Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
6.4.1.3 Arbitration Slave Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
6.4.1.4 Locking the Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
6.4.2 Connecting Multimaster Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
6.5 Fastest possible external access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
7 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
7.1 Short Instruction Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
7.2 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
7.3 Instruction Opcodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
8 Detailed Instruction Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
8.1 Normal Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
8.2 DSP Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
8.3 Instructions for OCDS/ITC injection and System Control . . . . . . . . . . . . 417
9 Summary of CPU/Subsystem Registers . . . . . . . . . . . . . . . . . . . . . . . 421
9.1 General Purpose Registers (GPRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
9.2 Core Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
9.2.1 Ordered by Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
9.2.2 Ordered by Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424
9.3 Register Overview Interrupt and Peripheral Event Controller . . . . . . . . . 426
9.3.1 Ordered by Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426
9.3.2 Ordered by Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427
9.4 Register Overview External Bus Controller . . . . . . . . . . . . . . . . . . . . . . . 430
9.4.1 Ordered by Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
9.4.2 Ordered by Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431
10 Keyword Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433

User Manual
C166S V2
Introduction
User Manual 1-9 V 1.7, 2001-01
1 Introduction
C166S V2 is a member of the most recent generation of the popular C166
microcontroller cores. C166S V2 combines high performance with enhanced modular
architecture. It was developed to provide easy migration from standard existing C16x to
the new C166S V2 core with its impressive DSP performance and advanced interrupt
handling. The system architecture inherits successful hardware and software concepts
that have been established in the C16x 16-bit microcontroller families. C166 code
compatibility enable re-use of existing code. This dramatically reduces the time-to-
market for new product development.
The following features position C166S V2 strategically for contemporary and emerging
markets for performance-hungry real-time applications:
– High CPU performance. Single clock cycle execution doubles the performance at the
same CPU frequency (relative to the performance of the C166).
– Built-in advanced MAC unit dramatically increases DSP performance.
– High Internal Program Memory bandwidth and the instruction fetch pipeline
significantly improve program flow regularity and optimize fetches into the execution
pipeline.
– Sophisticated Data Memory structure and multiple high-speed data buses provide
transparent data access (0 cycles) and broad bandwidth for efficient DSP processing.
– Advanced exceptions handling block with multi-stage arbitration capability yields
stellar interrupt performance with extremely small latency.
– Upgraded Peripheral Event Controller supports efficient and flexible DMA features to
support a broad range of fast peripherals.
– Highly modular architecture and flexible bus structure provide effective methods of
integrating application-specific peripherals to produce customer-oriented derivatives.
This User’s Manual describes the new standard C166S V2 core independently from its
use for the dedicated product. Differencies to existing standard products are therefore
described in the User’s Manual (or Target Specification) of the product.
1.1 Technical Overview
– 5-stage execution pipeline
– 2-stage instruction fetch pipeline with FIFO for instruction pre-fetching
– Pipeline with forwarding that controls data dependencies in hardware
– Linear address space for code and data (von Neumann architecture)
– Multiple high bandwidth internal busses for data and instructions
– Enhanced memory map with extended I/O areas
– 16 MBytes total linear address space
– C16x family compatible on-chip special function register area
– Fast multiplication (16-bit x 16-bit) in one CPU clock cycle
– Fast background execution of division (32-bit/16-bit) in 21 CPU clock cycles

User Manual
C166S V2
Introduction
User Manual 1-10 V 1.7, 2001-01
–Nearly all instructions executed in one CPU clock cycle
–Enhanced boolean bit manipulation facilities
–Zero cycle jump execution
–Additional instructions to support High Level Language (HLL) and operating systems
–Register-based design with multiple variable register banks
–Two additional fast register banks
–General purpose register architecture
–16 General-purpose registers (GPRs) for byte operands
–16 General-purpose registers (GPRs) for integer operands
–Overlapping 8-bit and 16-bit registers
–Opcode fully upward compatible with C166 family
–Variable stack with automatic stack overflow/underflow detection
–High performance branch-, call- and loop processing
–Multiply and accumulate instructions (MAC) executed in one CPU clock cycle
–Extremely short interrupt response time
–"Fast interrupt" and "Fast context switch" features
–Peripheral bus (PDBUS+) with bit protection
1.2 System Description
The basic C166S V2 System consists of the following main units:
•C166S V2 CPU
•On-Chip Data- and Code-Memories
•Data Management Unit (DMU)
•Program Management Unit (PMU)
•Interrupt and Peripheral Event Controller (PEC) Controller
•OCDS and JTAG-Interface
•External Bus Controller (EBC)
•System Control Unit (SCU)
•Clock Generation Unit (CGU)
The powerful C166S V2 core, the peripherals, and the internal memories of the
C166S V2 microcontroller are connected to various busses:
•16-bit high performance system bus
•16-bit enhanced peripheral bus (PDBUS+)
•64-bit internal program memory bus
•16-bit data memory bus

User Manual
C166S V2
Introduction
User Manual 1-11 V 1.7, 2001-01
Figure 1-1 shows a typical configuration of a C166S V2-based system.
Figure 1-1 C166S V2 System
1.2.1 CPU
–5-stage execution pipeline
–2-stage instruction fetch pipeline with FIFO for instruction pre-fetching
–Pipeline with forwarding that controls data dependencies in hardware
–Flexible PMU and DMU with cache capabilities
–Linear address space for code and data (von Neumann architecture)
–Multiple high bandwidth internal busses for data and instructions
–16 MBytes total linear address space
–Nearly all instructions executed in one CPU clock cycle
–Enhanced boolean bit manipulation facilities
–Zero cycle jump execution
–Additional instructions to support HLL and operating systems
–Register-based design with multiple variable register banks
–Two additional fast register banks
–General purpose register architecture
–16 General-purpose registers (GPRs) for byte operands
–16 General-purpose registers (GPRs) for integer operands
Data Memory
up tp 24 kBytes
SRAM
Program Memory
up to 4MBytes
JTAGOCDS
C166S V2 CPU
DMU
Injection
Interface
up tp 3 kBytes
DPRAM
C166S V2 MegaCore
Break
Interface
Trace
Interface
PMU
Dedicated Pins
Periheral
2
Peripheral
....
Peripheral
n
SCU
WDT PLL
OSC
16
16
16
64 64
PDBUS+
PORT PORT
CGU
External
Bus
JTAG
RESET
C166S V2
System
High Speed System Bus
PORT
EBC Config.
Block
External Bus Interface
CONFIG
Interrupt Controller
and
Peripheral Event Controller
XTAL1 XTAL2
CLKOUT
NMI
Peripheral
1
CLKOUT

User Manual
C166S V2
Introduction
User Manual 1-12 V 1.7, 2001-01
–Overlapping 8-bit and 16-bit registers
Multiply Accumulate Unit (MAC)
–Single cycle MAC with zero cycle latency including a 16*16 multiplier plus 40-bit barrel
shifter; single clock multiplication is ten times faster than C166 at the same CPU clock
–40-bit accumulator to handle overflows
–Automatic saturation to 32 bit or rounding included with the MAC instruction
–Fractional numbers supported directly
–One Finite Impulse Response Filter (FIR) tap per cycle with no circular buffer
management
1.2.2 On-Chip Memory Modules
–Up to 3 KBytes on-chip dual ported SRAM for DSP data and register banks
–Up to 24 KBytes on-chip internal single ported SRAM module for data storage
–Up to 4 MBytes on-chip memory module for program storage
Note: The on-chip memory configuration may differ from product to product. Product
specific on-chip memory configurations are defined in the corresponding product
specifications.
1.2.3 Data Management Unit (DMU)
The Data Management Unit (DMU) handles all data transfers external to the core (i.e.
external memory or on-chip special function registers on the PDBUS+) and instruction
fetches in external memory. The DMU acts as a data mover between the various
interfaces. By handling all these interfaces, it incorporates the C166S V2 System Bus.
An access prioritization between External BUS Controller (EBC) accesses from the core
and Program Memory Unit (PMU) is handled by the DMU. This allows an instruction
fetch from external memory in parallel with data access that is not on EBC.
1.2.4 Program Memory Unit (PMU)
The PMU has two basic functions: to provide the CPU with instructions and to provide
the CPU (through the DMU) with data located in the Internal Program Memory. The
Internal Program Memory is implemented within the PMU.
The instructions requested by the CPU can be located in the Internal Program Memory;
in which case, the instructions are requested to the internal memory. Alternatively, they
can be located in external memory; in which case, the PMU re-sends this request to the
EBC through the DMU, receives the data from the external memory, through the EBC/
DMU, and delivers it as the requested instruction to the CPU.

User Manual
C166S V2
Introduction
User Manual 1-13 V 1.7, 2001-01
1.2.5 Interrupt and PEC Controller
–16-Priority-level interrupt system with up to 128 sources on four group levels
–Eight PEC channels with 24-bit source and destination pointers with segment pointer
registers
–Enhanced PEC pointers. PEC source pointers and PEC destination pointers can be
simultaneously modified
–Independent programmable PEC level and "End of PEC" interrupt
1.2.6 OCDS and JTAG
The OCDS (level 1) provides facilities to the debugger to emulate resources and assist
in application program debug. The main features are:
–Real time emulation
–Extended trigger capability including: instruction pointer events, data events on
address and/or value, external inputs, counters, chaining of events, timers, etc.
–Software break support
–Break and “break before make”(on IP events only)
–Interrupt servicing during break or monitor mode
–Simple monitor mode or JTAG based debugging through instruction injection
The C166S V2 OCDS is controlled by the debugger1) through a set of registers
accessible from the JTAG interface. The OCDS also receives informations (such as IP,
data, status) from the core for monitoring the activity and generating triggers. Finally, the
OCDS interacts with the core through a break interface to suspend program execution,
and through an injection interface to allow execution of OCDS generated instructions.
1.2.7 External Bus Controller (EBC)
All external memory accesses are performed by a particular on-chip External Bus
Controller (EBC).
1.2.8 System Control Unit (SCU)
The System Control Unit supports all central control tasks and all product specific
features. The following typical sub-modules are implemented in this unit:
Reset Control
The reset function is controlled by the reset control unit.
1) Debugger refers to the tool connected to the emulator, and more specifically to the OCDS via the JTAG and
which manages the emulation/debugging task.

User Manual
C166S V2
Introduction
User Manual 1-14 V 1.7, 2001-01
Power Saving Control
The Power Saving Control block, known from the power management of the C166
derivatives, manages idle mode, power down mode, and sleep mode of the C166S V2.
ID Control
A set of six identification registers is defined for the most important silicon parameters,
including the chip manufacturer, the chip type and its properties. These ID registers can
be used for automatic test selection.
External Interrupt Control
The C166S V2 System provides asynchronous fast external interrupt inputs.
Central System Control
The central system behavior of the C166S V2 is controlled by this block. The frequency
of the PDBUS+ (bus clock) and of all peripherals connected to this bus is programmable
according to the maximum physical bus speed and the application requirements.
Furthermore, the clock generation status is indicated. Depending on the application
state, various security levels (such as protected and unprotected mode) are supported
by the security level control state machine.
Watchdog Timer (WDT)
The Watchdog Timer is one of the fail-safe mechanisms that have been implemented to
prevent the controller from malfunctioning. However, the Watchdog Timer can detect
only long term malfunctions.
1.2.9 Clock Generation Unit (CGU)
The C166S V2 Clock Generation Unit uses either an oscillator or crystal to generate the
system clock. A programmable on-chip PLL adds high flexibility to clock generation for
the C166S V2.
1.2.10 On-Chip Bootstrap Loader
As in the C166, the on-chip bootstrap loader allows the start code to be moved into
internal RAM via the serial interface.

User Manual
C166S V2
Central Processing Unit
User Manual 2-15 V 1.7, 2001-01
2 Central Processing Unit
C166S V2 CPU represents the third generation of the well known C166 core family. It
combines many powerful enhancements with compatibility to the C166 family. The new
architecture results in high CPU performance, fast and efficient access to different kinds
of memories, and proficient peripheral units integration.
.
Figure 2-1 CPU Architecture
address
data in
data out
CSP IP
CPUCON1
CPUCON2
FIFO
IFU
IDX0
IDX1
QX1
QX0
QR1
QR0
SP
SPSEG
VECSEG
STKOV
STKUN
DPP0
DPP1
DPP3
DPP2
+/-
+/-
ADU
MDLMDH
MAL
Division Unit
MAH
Multiply Unit
MSW
MCW
ALU
RF
+/- +/-
ZEROS
PSW
ONES
MRW
TFR
CPUID
MDC
Barrel-Shifter
Bit-Mask-Gen.
Multiply Unit
WB
MAC
CPU
CP
2-Stage
Prefetch
Pipeline
5-Stage
Pipeline
IPIP
DPRAM
address
data in
data out
DMU
R15
R14
R0
R1
SRAM
data in
address
data out
Peripheral-Bus
PMU
Internal Program Memory
System-Bus
address
data in
data out
System-Bus
Prefetch Unit
Branch Unit
Return Stack
Injection/Exception
Handler
GPRs
Buffer
R15
R14
R0
R1
GPRs
R15
R14
R0
R1
GPRs
R15
R14
R0
R1
GPRs

User Manual
C166S V2
Central Processing Unit
User Manual 2-16 V 1.7, 2001-01
The new core architecture of the C166S V2 CPU results in higher CPU clock frequencies
and reduces the number of clock cycles per executed instruction by half, compared to
the C166 core. C166S V2 CPU also integrates a multiplication and accumulation unit
which dramatically increases performance of the DSP-intensive tasks.
C166S V2 CPU has eight main units that are listed below. All of these units have been
optimized to achieve maximum performance and flexibility.
•High Performance Instruction Fetch Unit (IFU)
–High Bandwidth Fetch Interface
–Instruction FIFO
–High Performance Branch-, Call-, and Loop-Processing with instruction flow
prediction
•Return Stack
–Injection/Exception Handler
–Handling of Interrupt Requests
–Handling of Hardware Failures
•Instruction Pipeline (IPIP)
–Bypassable 2-stage Prefetch Pipeline
–5-stage Execution Pipeline
•Address and Data Unit (ADU)
–16-bit arithmetic unit for address generation
–DSP address unit with a set of dedicated address- and offset pointers
•Arithmetic and Logic Unit (ALU)
–8-bit and 16-bit Arithmetic Unit
–16-bit Barrel Shifter
–Multiplication and Division Unit
–8-bit and 16-bit Logic Unit
–Bit manipulation Unit
•Multiply and ACcumulate Unit (MAC)
–16-bit multiplier with 32-bit result generation1)
–40-bit Accumulator with 40-bit Barrel Shifter
–Repeat Control Unit
•Register File (RF)
–5-port Register File with three independent register banks
•Write Back Buffer (WB)
–3-entries buffer
1) The same hardware-multiplier is used in the ALU and in the MAC Unit.

User Manual
C166S V2
Central Processing Unit
User Manual 2-17 V 1.7, 2001-01
2.1 Register Description Format
C166S V2 CPU contains a set of Special Function Register (SFR) and Extended Special
Function Registers (ESFR). They are described in the respective chapter of this manual.
The example below shows how to interpret the format and notation used to describe
SFRs and ESFRs.
A word register looks like this:
A byte register looks like this:
Elements:
REG_NAME Name of this register
bitX Name of bit
bitfieldX Name of bitfield
A16 / A8 Long 16-bit address/Short 8-bit address
SFR(b)/ESFR(b) Register space (SFR or ESFR (bit addressable) Register)
XSFR Register located in the internal 4 k IO area
REG_NAME
Short Description SFR(b)/ESFR(b)/XSFR Reset Value: aaaaH
1514131211109876543210
000000 bitfield
A0 0 bit Cbit Bbit A
rrrrrr rwh rrrw rw rwh
REG_NAME
Short Description SFR(b)/ESFR(b)/XSFR Reset Value: aaH
76543210
0bitfield
A0bit Cbit Bbit A
rrwh rrw rw rwh
Field Bits Type Description
bitfieldX [m:n] type Description
value Function off(Default)
value Enable Function 1
... ...
bitX [n] type Description
0 Function off(Default)
1 Enable Function

User Manual
C166S V2
Central Processing Unit
User Manual 2-18 V 1.7, 2001-01
(* *) * * Register contents after reset
’0/1’: defined value,
’U’: unchanged (undefined (’X’) after power up)
’?’: defined by reset configuration
[n] Bit number
[m:n] n : Bit number first bit of the bitfield
m : Bit number of last bit of the bitfield
type ’r’: readable by software
’w’: writable by software
’h’: writable by hardware
value ’0/1’: defined value,
’X’: undefined,
’0’: reserved for future purpose, read access delivers 0,
must not be set to 1
2.2 CPU Special Function Registers
The core CPU requires a set of CPU Special Function Registers (CSFRs) to maintain
the system state information, to control system and bus configuration, and to manage
code memory segmentation and data memory paging. The CPU also uses CSFRs to
access the General Purpose Registers (GPRs) and the System Stack, to supply the ALU
with register-addressable constants, and to support multiply and divide ALU operations.
The access mechanism for these CSFRs in the CPU core is identical to the access
mechanism for any other SFR. Since all SFRs can be controlled by any instruction
capable of addressing the SFR/CSFR memory space, there is no need for special
system control instructions.
However, to ensure proper processor operations, certain restrictions on the user access
to some CSFRs must be imposed. For example, the Instruction Pointer (IP) and Code
Segment Pointer (CSP) cannot be accessed directly at all. They can only be changed
indirectly via branch instructions.
The PSW, SP, and MDC registers can be modified not only explicitly by the programmer,
but also implicitly by the CPU during normal instruction processing.
Note: Note that any explicit write request (via software) to an CSFR supersedes a
simultaneous modification by hardware of the same register.
Note: All SFRs may be accessed wordwise, or bytewise (some of them even bitwise).
Reading bytes from word SFRs is a non-critical operation. Any write operation to
a single byte of an CSFR clears the non-addressed complementary byte within the
specified CSFR.
Non-implemented (reserved) CSFR bits cannot be modified, and will always
supply a read value of 0.

User Manual
C166S V2
Central Processing Unit
User Manual 2-19 V 1.7, 2001-01
2.3 Instruction Fetch and Program Flow Control
The Instruction Fetch Unit (IFU) pre-fetches and pre-processes instructions to provide a
continuous instruction flow. The IFU can fetch simultaneously at least two instructions
via a 64-bit wide bus from the Program Management Unit (PMU). The pre-fetched
instructions are stored in an instruction FIFO. Pre-processing of branch instructions
enables the instruction flow to be predicted. While the CPU is in the process of executing
an instruction fetched from the FIFO, the pre-fetcher of the IFU starts to fetch a new
instruction at a predicted target address from the PMU. The latency time of this access
is hidden by the execution of the instructions which have been buffered in the FIFO
before. Even for a non-sequential instruction, execution the IFU can generally provide a
continuous instruction flow. The IFU contains two pipeline stages: the Prefetch Stage
and the Fetch Stage.
Figure 2-2 IFU Block Diagram
Instruction Buffer(up to 6 Instr.)
Instruction Buffer(up to 3 Instr.)
Instruction Buffer(up to 1 Instr.)
Instruction
FIFO
Branch Detection and Prediction Logic
64bit
data
Branch Folding
Unit
Bypass Fetch to Decode
Bypass Prefetch to Decode
Fetch
Stage
Prefetch
Stage
Injection and Exception Handler
Return Stack
TFRVECSEG
Decode
Stage
IP
CSP
+/-
CPUCON1
CPUCON2
CPUID
24-bit address
IFU PipelineIFU Control
Control Registers

User Manual
C166S V2
Central Processing Unit
User Manual 2-20 V 1.7, 2001-01
During the pre-fetch stage, the Branch Detection and Prediction Logic analyzes up to
three pre-fetched instructions stored in the first Instruction Buffer (up to six instructions).
If a branch is detected, then the IFU starts to fetch the next instructions from the PMU
according to the prediction rules. After having been analyzed, up to three instructions are
stored in the second Instruction Buffer (three instructions) which is the input register of
the Fetch Stage.
On the Fetch Stage, the pre-fetched instructions are stored in the instruction FIFO. The
Branch Folding Unit (BFU) allows processing of branch instructions in parallel with
preceding instructions. To achieve this the BFU pre-processes and re-formats the
branch instruction. First, BFU defines (calculates) the absolute target address. This
address—after being combined with branch condition and branch attribute bits—is
stored in the same FIFO step as the preceding instruction. The target address is also
used to pre-fetch the next instructions.
For the Execution Pipeline, both instructions are fetched from the FIFO again and are
executed in parallel. If the instruction flow was predicted incorrectly (or FIFO is empty),
the two stages of the IFU can be bypassed.
Note: Pipeline behavior in case of a incorrectly predicted instruction flow is described in
the following sections.
2.3.1 Branch Target Addressing Modes
The target address and the segment of jump or call instructions can be specified by
several addressing modes. The Instruction Pointer register (IP) may be updated using
relative, absolute, or indirect modes. The Code Segment Pointer register (CSP) can be
updated using an absolute value only. A special mode is provided to address the
interrupt and trap jump vector table which resides in the lowest portion of the code
segment selected by the VECSEG register contents.
Table 2-1 Branch Target Addressing Modes
Mnemonic Target Address Target Segment Valid Address Range
caddr (IP) = caddr - caddr = 0000H...FFFEH
rel (IP) = (IP) + 2*rel
(IP) = (IP) + 2*(rel+1)
-
-
rel = 00H...7FH
rel = 80H...FFH
[Rw] (IP) = (Rw) - Rw w = 0...15
seg - (CSP) = seg seg = 0...255(3)
#trap7 (IP) = 0000H+
VECSC*trap7
(CSP) = VECSEG trap7 = 00H...7FH