ST STA304 User manual

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AN1456
APPLICATION NOTE
January 2002
1 EVALUATION BOARD
The STA304 Digital Audio Processor is a single chip device implementing end to end digital solution for audio
application. In conjunction with STA500 Power Bridge it gives the full digital DSP-to-Power high quality chain
with no need for Digital-to Analog converters.
The STA304 Evaluation kit is an example for a general application involving all the STA304 and STA500 capa-
bilities, which gives the possibility to evaluate the system performances.
The evaluation kit consists of two boards, and control software. In the first board an STA304 and three STA500
are available, while the second is used to connect the main board to the PC. The control software allows then
to control all the evaluation board capabilities from a simple visual interface.
1.1 LPT Interface (LPT300)
In order to allow proper communication between the 3.3V powered (digital) evaluation board and a standard
LPT interface the STA304 evaluation kit includes also the LPT interface board (LPT300) shown in Figure 1.
Basically the interface will perform a signal level translation between 3.3V and 5V in both directions.
The LPT300 interface take the supply (both 3.3V and 5V) from pins 17 and 18 of the connector J2 (see Figure
2), so no regulators are on board. There is the possibility to have also the regulator on board (U3 and U4), but
in that case the pins 17 and 18 should be disconnected from the STA304 evaluation board. In Figure 2 the com-
ponents that are not needed for LPT300 (such as regulators) are drawn in dashed lines.
IMPORTANT: the LPT300 interface can have some problems if the PC LPT port is configured as "bi-direction-
al". In order to perform a quick test, after the LPT300 is connected to the STA304 board, switch on the supply
and try the "Test procedure" (see the SETUP section). If the test doesn't succeed, try to check the PC parallel
port settings: most PC in fact, can configure their LPT interface in different modes (SPP/EPP/ECP) and it could
happen that some of those configurations are not well suited to control our evaluation kit.
Figure 1. LPT300 Interface Layout
- JP1, JP3 open without U3
and U4. Supply from J2
connector (default for
LPT300).
by Luca Molinari
STA304 + STA500 DIGITAL AUDIO PROCESSOR
EVALUATION BOARD OPERATING MANUAL
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AN1456 APPLICATION NOTE
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Figure 2. LPT300 interface schematic
SCL
SDA
PWDN
AC97_MODE
RESET
PWRDN THWARN Left
THWARN Right
THWARN LFE
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AN1456 APPLICATION NOTE
1.2 STA304 Evaluation Board
The STA304 evaluation board layout is shown in Figure 3.
The board has one SPDIF input (differential, electrical single ended, and optical), and two serial inputs. Three
serial output are available, as well as five analog power outputs.
AC97 signals are available on connector J2 for an AC97 application (an AC97 external controller is needed).
Figure 3. STA304 eval. board layout
SPDIF
Electrical
Professional
(Differential)
SPDIF
Electrical
Consumer
(Single-end) SPDIF Optical
SPDIF
Interface
Selector LPT300 connector Ac97 connector
5.0V
3.3V
Supply
Serial
Interface I/O
Clock Input
(Remove the crystal
before using)
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AN1456 APPLICATION NOTE
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Three power stages (STA500) are mounted on board. The three devices take the analog supply from the termi-
nal J1 (10V up to 35V), as well as the digital supply from the IC6 regulator.
IC3 and IC4 are configured to drive 8 ohm load (up to 30 W) on LEFT,RIGHT,S-LEFT,S-RIGHT, while IC1 is
configured to drive 4 ohm load (up to 60 W) on LFE.
Some board behaviours are selectable from the Jumper and the switch on board, read carefully the "setup" sec-
tion to avoid board damages.
Before using the STA304 demo board, the jumper J4 and J5 must be shorted. This jumper could be used to
perform current measurement for STA304; in fact, they are in series to all the digital (J4) and the analog (J5)
STA304 supply.
In case of STA500 damage, it is possible to break the supply to the damaged device using the relative jumper
on the lower side of the board (near J1). Be sure that all the jumpers should be shorted if you want to use all the
three power chip.
6 CHANNELS APPLICATION SUGGESTIONS
For the 6 channels applications, like DTS and AC3 it is mandatory to use two STA304.
In order to obtain the best results in terms of Audio Quality, we suggest to drive each STA50X with two PWM
signals coming from a single STA304, otherwise some overlap of the PWM frames could generate undesired
noise.
One possible configuration is:
Left / Right / Surround L / Surround R from the first STA304, CENTRE and LFE from the second one.
If STA50X in mono configuration is used for LFE (4
Ω application), than this LFE can be fed from any of the two
STA304 because no crosstalk is present.
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AN1456 APPLICATION NOTE
Figure 4. For the STA304 evaluation board schematic
12
10
16
14
VDD
SCKI LRCKI SDI2 SDI1 CKOUT SCKO SDO3 SDO2 SDO1 LRCKO
RESET
VCC POWER
LFE
N.M.
N.M.
S-LEFT S-RIGHT
5-6-7-8
RIGHT
LEFT
N.M.
Ac97 MODE TEST MODE SA PWDN
SLEFT-B LEFT-A LEFT-B RIGHT-A RIGHT-B SRIGHT-A SRIGHT-B
TH_WAR-2 TH_WAR-3 TH_WAR-1
LFE-B LFE-A
TH_WAR-3
PWDN
SRIGHT-B SLEFT-A SLEFT-B
PWDN
TH_WAR-2
SLEFT-A
SRIGHT-A LEFT-A RIGHT-A RIGHT-B
PWRDN PWRDN
LEFT-B
PWRDN
PWRDN
TH_WAR-1
PWRDN
LFE-B LFE-A
+3.3
+3.3
+3.3
+5V
+3.3V
+3.3
+5V +3.3V
+3.3V VCCA
+3.3
VCC
+5V
+5V
+3.3V
+3.3V +3.3V
+3.3V
+3.3V
+3.3 +3.3V VCC VCCA
J12
J10
J9J8 J11
IC2
STA300
1 2 3 4 5 6 7 8 9
10 11
12
13
14
15
16
17
18
19
20
21
22
23 24 25 26 27 28 29 30 31 32 33
34
35
36
37
38
39
40
41
42
43
44
SDI1/SDATA_OUT SDI2/SDATA_IN LRCKI/SYNC BCKI/BIT_CLK VDD1 GND1 RESET AC97_MODE SDA SCL SA
TEST_MODE
VDD2
XTI
XTO
GND2
VCC
RXP
RXN
VSS
LFE_B
LFE_A
SRIGHT_B SRIGHT_A
GND3
VDD3
RIGHT_B RIGHT_A
LEFT_B LEFT_A
GND4
VDD4
SLEFT_B
SLEFT_A
EAPD
LRCKO
SDO1
SDO2
SDO3
SCKO
GND5
VDD5
CKOUT
PWDN
J4 J5 J7
C8 100nF
J3 J6
J2
1
2
3
4
5
6
7
8
9
10
C21 100nF
L11 L12
+
C68 10uF 16V
C73 100nF
C32 100nF
C42 100nF
C44 100nF
C45 100nF
L6
T1
15 26
R29 100
C58 100nF
C38 100nF
J20
R26 SMD0
Q1 6.144MHz
1 2
R25 1M
C56 18pF
C57 18pF
J17
RX178A
1
2
3
DATA
GND
+VS
J18
SW2-1
13
4 3
15
2 1
SW2-2
9
8 7
11
6 5
J23
1 2
TP8 TP9 TP1
C49 100nF
C72 100nF
IC6 LD1086DT33
IN
GND
OUT
C71 100nF
C70 100nF
IC5 LD1086DT50
IN
GND
OUT
+
C67 10uF 16V
+
C66
10uF 16V
+
C65
10uF 16V
J21
2
1
3
SW1
C25 1nF
R9 10K
J1
1 2
C10 220nF
C11 1uF
R4 10K
L1 10uH
R5 10K
R6 0
R2 202
C15 100nF
L2 10uH
R1 2.2
C14 100nF
C3 220nF
C17 100nF
C9 1uF
TP3
+
C5 1000uF 35V
R7 0
C4 100nF
C6 220nF
C2 1uF
C12 220nF
C7 680pF
J13
1 2
J15
1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19 20
R12 10K
C26 100nF C40 100nF
C30 1uF
C33 100nF
L4 22uH
C37 470nF
L5 22uH
TP5
R17 0
C41 100nF
C20 330pF
J16
1 2
C29 100nF
C27 100nF
R13 6
TP6
R8 6
C34 330pF
R14 10K
C16 100nF
L7 22uH
TP7
R18 0
C23 470nF
L3 22uH
C19 100nF
C31 100nF
R16 22
C36 100nF
J14
1 2
R15 6 R10 6
TP4
R19 10K R22 10K R20 10K
SW3
1 2 3 412
11 10 9
R21 10K R36 0
TP12
C48 330pF
C47 100nF
TP13 TP10
C69 470nF
C55 100nF
R32 10K
L9 22uH
R27 6
C64 100nF
C51 470nF
R28 22 IC4
STA500
1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19
20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
GND-SUB OUT2B OUT2B VCC2B GND2B GND2A VCC2A OUT2A OUT2A OUT1B OUT1B VCC1B GND1B GND1A VCC1A OUT1A OUT1A N.C. GND-Clean
GND-Reg
VDD VDD
IBIAS
CONFIG
PWRDN
TRI-STATE
FAULT
TH_WAR
IN1A IN1B IN2A IN2B
VSS VSS
VCCSign. VCCSign.
C74 100nF
C52 100nF
C59 1uF
J22
1 2
R30 10K
C62 330pF
R35 0
J19
1 2
R33 6
C75 100nF
L13 22uHC76 100nF
C61 100nF
L8 22uH
+
C50
470uF 35V
R31 6
C77 100nF
C46 100nF C60 100nF
TP11
C54 1uF
C53 100nF
R34 22
R23 6
JP4 JP5
LF1
1
2
3
C4A 100nF
+
C1
2200uF 35V
C28 1uF
IC1
STA500
1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19
20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
GND-SUB OUT2B OUT2B VCC2B GND2B GND2A VCC2A OUT2A OUT2A OUT1B OUT1B VCC1B GND1B GND1A VCC1A OUT1A OUT1A N.C. GND-Clean
GND-Reg
VDD VDD
IBIAS
CONFIG
PWRDN
TRI-STATE
FAULT
TH_WAR
IN1A IN1B IN2A IN2B
VSS VSS
VCCSign. VCCSign.
R24 75
C39 100nF C43 100nF
C24 100nF
IC3
STA500
1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19
20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
GND-SUB OUT2B OUT2B VCC2B GND2B GND2A VCC2A OUT2A OUT2A OUT1B OUT1B VCC1B GND1B GND1A VCC1A OUT1A OUT1A N.C. GND-Clean
GND-Reg
VDD VDD
IBIAS
CONFIG
PWRDN
TRI-STATE
FAULT
TH_WAR
IN1A IN1B IN2A IN2B
VSS VSS
VCCSign. VCCSign.
TP2
C27A 100nF
C18 100nF
C53A 100nF
L10 22uH
R3 22
R3A
22
R11 22
+
C50A
470uF 35V
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AN1456 APPLICATION NOTE
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1.3 Setup and configuration
Before connecting the LPT300 and STA304 boards, check the jumper configuration:
The SW3 switch should be configured in this way:
■AC97 "ON" (switch 1)
■TEST_MODE "OFF" (switch 2)
■SA "OFF" (switch 3)
■PWDN "ON" (switch 4)
It is mandatory that the second switch is OFF, otherwise the STA304 is set to TEST MODE.
To avoid board damages the switch 1 and 4 should not be OFF when the LPT interface is connected. The sec-
ond switch set the SA pin, so the I2C address can be changed. Up to now the demo board software can use
only the seven bit address 0x1E (011110), so SA should be OFF.
Now the LPT300 interface and the STA304 demo board could be plugged together (BE CAREFUL, See Figure
5 for the plug).
Connect the PC parallel port to the LPT board using a parallel cable, and turn on the board supply.
Run STA304.exe on the PC, and select the Register page. Push the "RESET" button. In this condition the board
should waste about 150-200mA.
Try now the "TEST" button, the software should read the first four, and the last four registers via I2C. If the val-
ues read are equal to the default the "Pass" message should appear, and the I2C interface is working.
If the test fail, try first of all to check the PC configuration. Try to change the parallel port configuration (EPP,
ECP, etc.) and retry the test procedure starting from the RESET.
If the test is still fail, check the supply on the LPT interface, and on the STA304 demo board. Try to check also
if the I2C signals (SCL, SDA) are moving while the TEST button is pressed. If SDA or SCL are not moving, may-
be the LPT interface could be damaged.
Figure 5.
To select the SPDIF input way, the switch SW2 must be configured:
The numbers in the first column mean that a slider in the SW2 switch must be put in that position: for example
2-4-6-8 means that a slider must be in position 2, an other in position 4, an other in position 6, and the last in
position 8.
When the Electrical Professional interface is selected, it is mandatory that the STA304 be configured as SPDIF
SW2 config. Selected Interface
2-4-6-8 Electrical Professional
1-3-6-8 Electrical consumer
1-3-5-7 Optical
Component side
Component side
STA300 Evaluation Board
LPT300
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AN1456 APPLICATION NOTE
Analog (I/O Page in the control panel) . For the other interfaces, both Analog and digital could be used depend-
ing on input SPDIF levels. SPDIF digital could be used only if the RXP signal is in the range 0.2*VDD for ViL,
and 0.8*VDD for ViH. SPDIF Analog could be used if the input SPDIF signal is above 400 mV peak to peak.
1.4 DDX Output
To activate the five DDX outputs the following procedure must be used:
– Select the input interface (the presets 1, 2 ,3 could be used) from I/O Page;
– Select ST Table in Main Page;
– Remove the mute in the Main Page (*);
– Remove the DDX Reset in Main Page;
– Push Turn ON in Main Page.
At this point Sound should exit from the STA500.
(*) To avoid potential malfunctionings, it is recommended to remove the DDX mute only when both SRC and SPDIF are locked, i.e.:
- If SPDIF is used, the first two bits of 77h address must be: bit 0 = 0, bit 1 = 0.
- If I2S is used, the first two bits of 77h address must be bit 0 = 0, bit 1 = don’t care because it is referred to SPDIF.
2 CONTROL SOFTWARE
In order to control and evaluate the STA304 board a dedicated control panel has been developed. It runs on
Win95/98 operating system and allows complete DSP control (volume, mute, tone, etc.), full Serial and SPDIF
configuration, and demo board status monitoring (thermal warning, SPDIF and sample rate converter lock).
2.1 Main Page
1) The "Controls" section groups the volume, mute and tone controls for the STA304 demo board. There is a
master mute that automatically check all the mute controls, and a Left/Right Lock that link together L-R SL-
SR and CNT-LFE volume sliders. The range for the volume sliders depends on the full compliant bit in reg.
1
2
3
4
6
5
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5Ah (see I/O Page) as described in the datasheet.
2) In this section some configuration bits are grouped (see the registers on data sheet for more info).
3) The section 3 groups the status 'led' for the board. There are 3 thermal warning (red if a STA500 goes in
over heat), and two lock led for the Sample Rate Converter (SRC) and for the SPDIF.
When a thermal warning is detected, the corresponding STA500 channels will be automatically muted to
avoid the part destruction (in this case a by hand power off should be suggested). All the led are updated
every 300 ms.
4) Some default control presets are already present in those 6 memories. To store the current control position
just press down one of those buttons until it's automatically released. The presets buttons store and restore
not only the volume, the tone and the mute settings, but the all registers that define the fundamental behav-
iour of STA304 demo board, such as if using SPDIF or I2S, the DDX table, etc. (registers
0x02;0x03;0x08;0x09;0x26;0x27;0x36:0x39;0x5A:0x77). As soon as the software is started, in the memory
M1,M4,M5 and M6 are stored the default STA304 settings (i.e. the RESET values), while in the memory M2
there are the "SPDIF differential" settings, and finally in the memory M3 there are the "SPDIF digital".
5) Use this check-box to globally enable or disable the ToolTip function.
6) The "Turn off/on" button is used to put in power down or resume from the power down the STA500, while
the "Standby/Resume" button put (resume) the STA304 in (from) powerdown, leaving the I2C and AC97 in-
terface alive.
When entering in this page, all the controls are updated reading the STA304 registers.
2.2 I/O Page
In this page, all the input/output interfaces can be configured.
1) This 3 radio buttons are used to select from the 3 input interfaces supported by the STA304.
2) Regarding AC97, the software controls only the full compliant bit (if checked the STA304 works in full com-
pliant mode as described in the datasheet).
12
3
4
5
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AN1456 APPLICATION NOTE
3) The Serial interface has different configurations. Choosing "Bit Clock Polarity" and "LR Clock Polarity", the
bit and word clock polarity can be changed; the 'Alignment' field changes the data alignment respect to the
word clock, and the number of active bit clock edges (see DAP input Stage section in the datasheet).
4) If 'Digital Input' is checked, the internal SPDIF trigger is bypassed, and only the RXP signal is used by
STA304. In this configuration the input signal range is 0.2*VDD for ViL and 0.8*VDD for ViH. Otherwise RXP
and RXN pass through a Differential schmitt trigger, and the signal should follow the AES3 specifications.
5) The output serial interface is configured in the same way of the input one (see I2S Output Interface section
in the datasheet).
When entering in this page, all the controls are updated reading the STA304 registers.
2.3 Download Page
Using this page it is possible to read and download the coefficients in STA304. It is possible also to save and
load from file the values.
■Load: pushing the load button a load dialog will appear, and selecting a coefficients file the table 2 will
be updated with the new values read.
■Save: pushing the save button a save dialog will appear, selecting a file name the coefficient table will
be saved.
■Download: pushing this button the current table value will be stored in STA304.
■Read: pushing this button all the coefficientvalues will be read from STA304,and the table updatedwith
the read values.
Itis possibleto write a commentfor the coefficients file (inbox 1), and itwill be saved during the save procedure,
and loaded in the load procedure.
1
2
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A coefficients file is made of two comment lines at the top (comments begin with '#'), and a list of pair address-
value for every coefficient. Note that is not mandatory to put all the coefficients in the file, but only the needed
coefficient can be put. The numeric format for address and values can be either decimal or hexadecimal (ex.
0x1A). To have an example, the suggestion is to try to save the current coefficients, and to take a look to the
saved file.
The C code linked to the Download button is:
The whole coefficients table is parsed with the "for(int i…" loop. A coefficient is written using the procedure de-
scribed in Chapter 10 of the datasheet.
Regarding the read button, the code is:
In this case all the coefficients are read, and stored in the table m_coeff_list.
The code above is just to show the read/write coefficient procedure, is not intended to show a real application
code. Every application could have different code.
BOOL DownloadPage::DownloadCoeff()
{BOOL result=TRUE;
char elem[8];
int val;
for(int i=0;i<NCOEF;++i)
{m_coeff_list.GetItemText(i,1,elem,7);
sscanf(elem,"%x",&val);
result = result && WriteByte(0x78,(val & 0x0ff00)>>8);
result = result && WriteByte(0x79,(val & 0x000ff)>>0);
result = result && WriteByte(0x7A,(i+0x40));
result = result && WriteByte(0x7B,0x0f & ((val & 0xf0000)>>16));
}
return(result);
}
void DownloadPage::OnCoeffRead()
{// TODO: Add your control notification handler code here
int add,coe;
char st[6];
unsigned char dataL,dataM,dataH;
for(add=0;add<NCOEF;++add)
{WriteByte(Coefficent_1H_ADD,(unsigned char)add+0x40);
WriteByte(Coefficent_1L_ADD,(1<<7));
ReadByte(Coefficent_0H_ADD,&dataM);
ReadByte(Coefficent_0L_ADD,&dataL);
ReadByte(Coefficent_1L_ADD,&dataH);
dataH&=0xF;
coe=(unsigned int)dataL+((unsigned int)dataM *256)+
((unsigned int)dataH *256*256);
sprintf(st, "%05x", coe);
m_coeff_list.SetItemText(add,1,st);
}
}
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AN1456 APPLICATION NOTE
2.4 Register Page
1 Using the controls in this section it's possible to manually access all the device control/configuration regis-
ters. Selecting a register in the list box 'Register Name', its value is automatically read. A register address
can be inserted directly in the 'Address' edit box, but in this case only when the read button is pressed the
register content is read. To write a register value, first select the register or insert its address in the edit box,
then write the new value in the 'Data' edit box, finally press the 'Write' button.
2) To find the LPT port address, just use the 'Autofind' button. Typically there should be no need to use it, since
the software automatically detects the parallel port address every time you run it. To change the I2C device
address, the I2C box should be used. When the SApin is hold to gnd (using SW3 switch on the demo board)
ADD0 must be used, otherwise if SA is tie to Vdd ADD1 must be selected.
3) To put the STA304 in HW power down (all clocks off), or to perform an HW reset, this two button can be
used. The HW reset will initialise all the device registers with their default values. To resume an HW power-
down the HW reset is mandatory.
4) In order to check the I2C connection and, basically, the correct setup of the evaluation kit a 'Test' button has
been included in this page. It just read the first four and the last four registers of STA304, and compares
theirs values with the default ones. This test must be done, obviously, after the 'Reset' button was pressed,
and before any change in the 8 checked registers.
2
1
34
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3 CAUTIONS
■Leaving an STA500 outputwithout load while this channel is playing some signal could damage the de-
vice.
■Switch on the STA500 supply only if the STA304 isworking and the buttonin 6 inthe main page displays
"Turn ON".
■Be sure that ST table is selected before switch on the three STA500
4 RELIABLE CIRCUIT DESIGN
■Power Supply Decoupling
Minimize inductance loop area for SMD ceramic bypass capacitors configured to pins VCC1, VCC2,
VCCSign, Vss, Vdd, and Ibias on STA500.
Poor decoupling on VCC1,2 and VCCSign could generate catastrophic failures on STA500 (especially
in mono configuration) during continuous full power functioning. In these conditions the devices fail to
prior activating thermal warning.
■Power Routing
Provide star configuration power routing to each STA500 on a multichannel amplifier. Minimize induct-
ance loop area between each STA500 and its respective bulk bypass capacitor.
■Snubber Circuits
Locate the snubber circuits (C4+R3, C14+R8, C27+R12, C39+R17) as close as pratical between the
outputs of the STA500.
■Output Routing
1. Inductor Placement: maintain a minimum physical separation of one inductor's diameter, particularly be-
tween inductors of different channels.
2. Output traces: balance the impedance of traces in the output circuit so as to maintain source matching.
Match pcb traces on each output circuit to within 10 milliohms.
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AN1456 APPLICATION NOTE
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